/Zephyr-Core-3.6.0/drivers/adc/ |
D | adc_common.c | 14 uint8_t div; in adc_gain_invert() member 17 [ADC_GAIN_1_6] = {.mul = 6, .div = 1}, in adc_gain_invert() 18 [ADC_GAIN_1_5] = {.mul = 5, .div = 1}, in adc_gain_invert() 19 [ADC_GAIN_1_4] = {.mul = 4, .div = 1}, in adc_gain_invert() 20 [ADC_GAIN_1_3] = {.mul = 3, .div = 1}, in adc_gain_invert() 21 [ADC_GAIN_2_5] = {.mul = 5, .div = 2}, in adc_gain_invert() 22 [ADC_GAIN_1_2] = {.mul = 2, .div = 1}, in adc_gain_invert() 23 [ADC_GAIN_2_3] = {.mul = 3, .div = 2}, in adc_gain_invert() 24 [ADC_GAIN_4_5] = {.mul = 5, .div = 4}, in adc_gain_invert() 25 [ADC_GAIN_1] = {.mul = 1, .div = 1}, in adc_gain_invert() [all …]
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/Zephyr-Core-3.6.0/soc/arc/snps_arc_iot/ |
D | sysconf.c | 106 void arc_iot_ahb_clk_divisor(uint8_t div) in arc_iot_ahb_clk_divisor() argument 108 sysconf_reg_ptr->AHBCLKDIV = div; in arc_iot_ahb_clk_divisor() 129 void arc_iot_apb_clk_divisor(uint8_t div) in arc_iot_apb_clk_divisor() argument 131 sysconf_reg_ptr->APBCLKDIV = div; in arc_iot_apb_clk_divisor() 152 void arc_iot_dio_clk_divisor(uint8_t div) in arc_iot_dio_clk_divisor() argument 157 void arc_iot_spi_master_clk_divisor(uint8_t id, uint8_t div) in arc_iot_spi_master_clk_divisor() argument 161 (sysconf_reg_ptr->SPI_MST_CLKDIV & 0xffffff00) | div; in arc_iot_spi_master_clk_divisor() 164 (sysconf_reg_ptr->SPI_MST_CLKDIV & 0xffff00ff) | (div << 8); in arc_iot_spi_master_clk_divisor() 167 (sysconf_reg_ptr->SPI_MST_CLKDIV & 0xff00ffff) | (div << 16); in arc_iot_spi_master_clk_divisor() 171 void arc_iot_gpio8b_dbclk_div(uint8_t bank, uint8_t div) in arc_iot_gpio8b_dbclk_div() argument [all …]
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D | sysconf.h | 143 extern void arc_iot_ahb_clk_divisor(uint8_t div); 146 extern void arc_iot_sdio_clk_divisor(uint8_t div); 147 extern void arc_iot_spi_master_clk_divisor(uint8_t id, uint8_t div); 148 extern void arc_iot_gpio8b_dbclk_div(uint8_t bank, uint8_t div); 149 extern void arc_iot_gpio4b_dbclk_div(uint8_t bank, uint8_t div); 150 extern void arc_iot_i2s_tx_clk_div(uint8_t div); 151 extern void arc_iot_i2s_rx_clk_div(uint8_t div); 155 extern void arc_iot_dvfs_clk_divisor(uint8_t level, uint8_t div); 159 extern void arc_iot_uart3_clk_divisor(uint8_t div); 161 extern void arc_iot_eflash_clk_div(uint8_t div);
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/Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/ |
D | core_init.overlay | 25 /delete-property/ hsi-div; 41 /delete-property/ div-m; 43 /delete-property/ div-p; 44 /delete-property/ div-q; 45 /delete-property/ div-r; 51 /delete-property/ div-m; 53 /delete-property/ div-p; 54 /delete-property/ div-q; 55 /delete-property/ div-r; 61 /delete-property/ div-m; [all …]
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/Zephyr-Core-3.6.0/doc/connectivity/networking/conn_mgr/figures/ |
D | integration_diagram_detailed.drawio | 13 …b8zi3n4dXzB52SZQf6J-10" value="<div>network</div><div>readiness</div><d… 16 …<mxCell id="Db8zi3n4dXzB52SZQf6J-11" value="<div>Application</div>" style="rounded=0;w… 19 …div><br></div><div><br></div><div><br></div><… 31 …ue="<div>Zephyr ifaces (unbound)</div><div><br></div><div><… 46 …<mxCell id="Db8zi3n4dXzB52SZQf6J-32" value="<div>binding</div>" style="rounded=0;white… 57 …<mxCell id="Db8zi3n4dXzB52SZQf6J-33" value="<div>binding</div>" style="rounded=0;white… 60 …<mxCell id="Db8zi3n4dXzB52SZQf6J-34" value="<div>binding</div>" style="rounded=0;white… 70 …n4dXzB52SZQf6J-45" value="<div>Connectivity</div><div>Implementation</div>… 80 …4dXzB52SZQf6J-46" value="<div>Connectivity</div><div>Implementation</div>&… 83 …l id="Db8zi3n4dXzB52SZQf6J-55" value="<div>Connectivity</div><div>Bindings<br… [all …]
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D | integration_diagram_simplified.drawio | 10 …b8zi3n4dXzB52SZQf6J-10" value="<div>network</div><div>readiness</div><d… 13 …<mxCell id="Db8zi3n4dXzB52SZQf6J-11" value="<div>Application</div>" style="rounded=0;w… 19 …l id="Db8zi3n4dXzB52SZQf6J-71" value="<div>connectivity</div><div>commands<br… 22 …Cell id="Db8zi3n4dXzB52SZQf6J-89" value="<div>iface commands</div><div>and event… 25 …ell id="Db8zi3n4dXzB52SZQf6J-113" value="<div>iface commands</div><div>and event… 40 …ell id="Db8zi3n4dXzB52SZQf6J-135" value="<div>network</div><div>commands<br&g… 68 …<mxCell id="Db8zi3n4dXzB52SZQf6J-144" value="<div>Zephyr ifaces</div>" style="rounded=… 91 …B52SZQf6J-162" value="<div>connectivity</div><div>commands</div><div>… 94 …<mxCell id="Db8zi3n4dXzB52SZQf6J-167" value="<div>iface events</div>" style="text;html…
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/Zephyr-Core-3.6.0/soc/arm/nxp_imx/rt/ |
D | soc_rt11xx.c | 225 rootCfg.div = 1; in clock_init() 230 rootCfg.div = 1; in clock_init() 234 rootCfg.div = 1; in clock_init() 240 rootCfg.div = 1; in clock_init() 244 rootCfg.div = 1; in clock_init() 311 rootCfg.div = 1; in clock_init() 318 rootCfg.div = 2; in clock_init() 323 rootCfg.div = 1; in clock_init() 331 rootCfg.div = 2; in clock_init() 336 rootCfg.div = 2; in clock_init() [all …]
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/Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/ |
D | clear_clocks.overlay | 20 /delete-property/ hsi-div; 36 /delete-property/ div-m; 38 /delete-property/ div-p; 39 /delete-property/ div-q; 40 /delete-property/ div-r; 46 /delete-property/ div-m; 48 /delete-property/ div-p; 49 /delete-property/ div-q; 50 /delete-property/ div-r;
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D | pll_hsi_96.overlay | 13 hsi-div = <8>; /* HSI RC: 64MHz, hsi_clk = 8MHz */ 18 div-m = <1>; 20 div-p = <2>; 21 div-q = <4>; 22 div-r = <2>;
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/Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/ |
D | clear_clocks.overlay | 31 /delete-property/ hsi-div; 39 /delete-property/ div-m; 41 /delete-property/ div-p; 42 /delete-property/ div-q; 43 /delete-property/ div-r; 50 /delete-property/ div-m; 52 /delete-property/ div-p; 53 /delete-property/ div-q; 54 /delete-property/ div-r;
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D | pll_hsi_240.overlay | 14 hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */ 19 div-m = <4>; 21 div-p = <2>; 22 div-q = <2>; 23 div-r = <2>;
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D | pll_csi_100.overlay | 17 /* Test another couple of M-div N-mul to obtain 100MHz from the CSI */ 19 div-m = <1>; 21 div-p = <2>; 22 div-q = <2>; 23 div-r = <2>;
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D | pll_csi_240.overlay | 17 /* Test another couple of M-div N-mul to obtain 240MHz from the CSI */ 19 div-m = <1>; 21 div-p = <2>; 22 div-q = <2>; 23 div-r = <2>;
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/Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/ |
D | g0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay | 22 /delete-property/ div-m; 24 /delete-property/ div-p; 25 /delete-property/ div-q; 26 /delete-property/ div-r; 50 div-m = <1>; 52 div-p = <20>; /* 6.4 MHz */ 53 div-q = <2>; 54 div-r = <2>;
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D | g0_i2c1_sysclk_lptim1_lsi.overlay | 22 /delete-property/ div-m; 24 /delete-property/ div-p; 25 /delete-property/ div-q; 26 /delete-property/ div-r; 50 div-m = <1>; 52 div-p = <2>; 53 div-q = <2>; 54 div-r = <2>;
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D | g4_i2c1_hsi_adc1_pllp.overlay | 22 /delete-property/ div-m; 24 /delete-property/ div-p; 25 /delete-property/ div-q; 26 /delete-property/ div-r; 46 div-m = <1>; 48 div-p = <20>; /* 6.4 MHz */ 49 div-q = <2>; 50 div-r = <2>;
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D | wl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay | 21 /delete-property/ hsi-div; 30 /delete-property/ div-m; 32 /delete-property/ div-p; 33 /delete-property/ div-q; 34 /delete-property/ div-r; 64 div-m = <1>; 66 div-p = <20>; /* 12.8 MHz */ 67 div-q = <2>; 68 div-r = <2>;
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D | l4_i2c1_hsi_lptim1_lse.overlay | 27 /delete-property/ div-m; 29 /delete-property/ div-p; 30 /delete-property/ div-q; 31 /delete-property/ div-r; 55 div-m = <1>; 57 div-p = <7>; 58 div-q = <2>; 59 div-r = <4>;
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D | l4_i2c1_sysclk_lptim1_lsi.overlay | 27 /delete-property/ div-m; 29 /delete-property/ div-p; 30 /delete-property/ div-q; 31 /delete-property/ div-r; 55 div-m = <1>; 57 div-p = <7>; 58 div-q = <2>; 59 div-r = <4>;
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/Zephyr-Core-3.6.0/doc/safety/images/ |
D | zephyr-safety-process.svg | 1 …div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify…
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/Zephyr-Core-3.6.0/boards/arm/cy8cproto_063_ble/ |
D | cy8cproto_063_ble.dts | 98 clock-div = <1>; 103 * &fll clock-frequency / &clk_hf0 clock-div / &clk_fast clock-div = 100MHz / 1 / 1 = 100MHz 106 clock-div = <1>; 110 * &fll clock-frequency / &clk_hf0 clock-div / &clk_slow clock-div = 100MHz / 1 / 2 = 50MHz 113 clock-div = <2>; 117 * &fll clock-frequency / &clk_hf0 clock-div / &clk_peri clock-div = 100MHz / 1 / 1 = 100MHz 120 clock-div = <1>;
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/Zephyr-Core-3.6.0/drivers/pwm/ |
D | pwm_mchp_xec.c | 63 uint8_t div; member 193 uint8_t div; in xec_select_best_div_on_off() local 195 div = xec_select_div(target_freq, max_freq); in xec_select_best_div_on_off() 197 for (div_comp = (int)div - 1; div_comp >= 0; div_comp--) { in xec_select_best_div_on_off() 198 div = xec_compare_div_on_off(target_freq, dc, max_freq, in xec_select_best_div_on_off() 199 div, div_comp, on, off); in xec_select_best_div_on_off() 202 return div; in xec_select_best_div_on_off() 213 if (hc_params->div < NUM_DIV_ELEMS) { in xec_compare_params() 215 max_freq_high_on_div[hc_params->div], in xec_compare_params() 220 if (lc_params->div < NUM_DIV_ELEMS) { in xec_compare_params() [all …]
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/Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/ |
D | clear_clocks.overlay | 22 /delete-property/ hsi-div; 26 /delete-property/ div-m; 28 /delete-property/ div-p; 29 /delete-property/ div-q; 30 /delete-property/ div-r;
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D | pll_48_hsi_16.overlay | 17 div-m = <1>; 19 div-p = <2>; 20 div-q = <2>; 21 div-r = <2>;
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D | pll_g0_64_hsi_16.overlay | 14 hsi-div = <1>; 18 div-m = <1>; 20 div-q = <2>; 21 div-r = <2>;
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