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/Zephyr-Core-3.6.0/tests/boards/intel_adsp/cache/src/
Dmain.c13 uint32_t *cached, *uncached; in ZTEST() local
15 cached = (uint32_t *)LP_SRAM_BASE; in ZTEST()
16 uncached = sys_cache_uncached_ptr_get(cached); in ZTEST()
18 *cached = 42; in ZTEST()
22 zassert_equal(*cached, 42, NULL); in ZTEST()
28 zassert_equal(*cached, 42, NULL); in ZTEST()
36 zassert_equal(*cached, 80, NULL); in ZTEST()
39 *cached = 82; in ZTEST()
42 zassert_equal(*cached, 82, NULL); in ZTEST()
48 zassert_equal(*cached, 82, NULL); in ZTEST()
[all …]
/Zephyr-Core-3.6.0/arch/xtensa/core/
Dmem_manage.c16 uintptr_t cached = (uintptr_t)sys_cache_cached_ptr_get((void *)phys); in sys_mm_is_phys_addr_in_range() local
21 valid |= ((cached >= CONFIG_SRAM_BASE_ADDRESS) && in sys_mm_is_phys_addr_in_range()
22 (cached < (CONFIG_SRAM_BASE_ADDRESS + (CONFIG_SRAM_SIZE * 1024UL)))); in sys_mm_is_phys_addr_in_range()
32 uintptr_t cached = (uintptr_t)sys_cache_cached_ptr_get(virt); in sys_mm_is_virt_addr_in_range() local
37 valid |= ((cached >= CONFIG_KERNEL_VM_BASE) && in sys_mm_is_virt_addr_in_range()
38 (cached < (CONFIG_KERNEL_VM_BASE + CONFIG_KERNEL_VM_SIZE))); in sys_mm_is_virt_addr_in_range()
/Zephyr-Core-3.6.0/subsys/logging/
Dlog_mgmt.c214 uint8_t *cached; in link_source_name_get() local
224 if (!log_cache_get(&sname_cache, id.raw, &cached)) { in link_source_name_get()
232 cached, &cache_size); in link_source_name_get()
237 log_cache_put(&sname_cache, cached); in link_source_name_get()
240 return (const char *)cached; in link_source_name_get()
263 uint8_t *cached; in link_domain_name_get() local
269 if (!log_cache_get(&dname_cache, id, &cached)) { in link_domain_name_get()
276 err = log_link_get_domain_name(link, rel_domain_id, cached, &cache_size); in link_domain_name_get()
278 log_cache_release(&dname_cache, cached); in link_domain_name_get()
282 log_cache_put(&dname_cache, cached); in link_domain_name_get()
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/Zephyr-Core-3.6.0/soc/arm/aspeed/ast10x0/
DKconfig.soc17 The non-cached SRAM size in kB. The default value comes from reg[1]
24 The non-cached SRAM base address. The default value comes from from
/Zephyr-Core-3.6.0/doc/develop/sca/
Dsparse.rst14 ``__cache`` used to identify pointers from the cached address range on the
15 Xtensa architecture. This helps identify cases where cached and uncached
/Zephyr-Core-3.6.0/tests/kernel/mp/
DKconfig6 # the shared variables in cached/incoherent memory.
/Zephyr-Core-3.6.0/boards/arm/mr_canhubk3/
Dmr_canhubk3_defconfig18 # Use no-cached memory for HAL
/Zephyr-Core-3.6.0/arch/common/
Dnocache.ld10 /* Non-cached region of RAM */
/Zephyr-Core-3.6.0/arch/xtensa/
DKconfig53 so that it can be seen in both (incoherent) cached mappings
62 Region Protection Option) contains the "cached" mapping.
151 bool "Map memory in cached and uncached region"
154 distinct region, cached and uncached.
/Zephyr-Core-3.6.0/boards/arm/mimxrt1160_evk/
Dmimxrt1160_evk_cm4.dts19 * a memory region that is not cached by the chip. If the chosen
/Zephyr-Core-3.6.0/soc/xtensa/intel_adsp/ace/
Dace-link.ld353 /* This section is cached. By default it contains only declared
356 .cached SEGSTART_CACHED : {
358 *(.cached .cached.*)
426 /* Non-loadable sections below. Back to cached memory so
/Zephyr-Core-3.6.0/boards/arm/mimxrt1170_evk/
Dmimxrt1170_evk_cm4.dts19 * a memory region that is not cached by the chip. If the chosen
/Zephyr-Core-3.6.0/include/zephyr/linker/
Dsection_tags.h59 #define __incoherent __in_section_unique(cached)
/Zephyr-Core-3.6.0/soc/xtensa/intel_adsp/cavs/include/
Dxtensa-cavs-linker.ld385 /* This section is cached. By default it contains only declared
388 .cached SEGSTART_CACHED : {
390 *(.cached .cached.*)
440 /* Non-loadable sections below. Back to cached memory so
/Zephyr-Core-3.6.0/arch/arc/
DCMakeLists.txt17 # Instruct compiler to use proper register as cached thread pointer for thread local storage.
/Zephyr-Core-3.6.0/subsys/bluetooth/controller/ll_sw/
Dull_conn_types.h78 struct pdu_data_llctrl_version_ind cached; member
Dull_llcp_pdu.c289 p->version_number = conn->llcp.vex.cached.version_number; in llcp_ntf_encode_version_ind()
290 p->company_id = sys_cpu_to_le16(conn->llcp.vex.cached.company_id); in llcp_ntf_encode_version_ind()
291 p->sub_version_number = sys_cpu_to_le16(conn->llcp.vex.cached.sub_version_number); in llcp_ntf_encode_version_ind()
297 conn->llcp.vex.cached.version_number = pdu->llctrl.version_ind.version_number; in llcp_pdu_decode_version_ind()
298 conn->llcp.vex.cached.company_id = sys_le16_to_cpu(pdu->llctrl.version_ind.company_id); in llcp_pdu_decode_version_ind()
299 conn->llcp.vex.cached.sub_version_number = in llcp_pdu_decode_version_ind()
/Zephyr-Core-3.6.0/cmake/modules/
DFindHostTools.cmake99 # Set cached ZEPHYR_TOOLCHAIN_VARIANT.
/Zephyr-Core-3.6.0/tests/cmake/zephyr_get/
DCMakeLists.txt103 # Environment value is cached after it's retrieved.
184 # Environment is not cached when using MERGE.
329 # If an environment value wins, it is cached afterwards.
563 # If an environment value wins, it gets cached and promoted above snippets.
/Zephyr-Core-3.6.0/boards/arm/frdm_k82f/
Dfrdm_k82f.dts36 * a memory region that is not cached by the chip. If the chosen
/Zephyr-Core-3.6.0/drivers/modem/
DKconfig.gsm138 helpful if your modem has a tendency to get stuck due to cached
/Zephyr-Core-3.6.0/boards/arm/twr_ke18f/
Dtwr_ke18f.dts43 * a memory region that is not cached by the chip. If the chosen
/Zephyr-Core-3.6.0/share/zephyr-package/cmake/
DZephyrConfig.cmake97 include_boilerplate("Zephyr base (cached)")
/Zephyr-Core-3.6.0/boards/arm/rddrone_fmuk66/
Drddrone_fmuk66.dts33 * a memory region that is not cached by the chip. If the chosen
/Zephyr-Core-3.6.0/arch/
DKconfig388 not be cached. This memory section can be used to perform DMA
641 arch_mem_coherent() API and can link into incoherent/cached
642 memory using the ".cached" linker section.
941 point to the same cached/uncached memory at different locations.

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