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/Zephyr-Core-3.6.0/arch/xtensa/core/
Ddebug_helpers_asm.S29 l32i a7, a6, ___xtensa_irq_bsa_t_pc_OFFSET
31 s32i a7, a2, 0
33 l32i a7, a6, ___xtensa_irq_bsa_t_a0_OFFSET
35 s32i a7, a4, 0
Dwindow_vectors.S142 s32e a7, a0, -20 /* save a7 to call[j]'s stack frame */
165 l32e a7, a1, -12 /* a7 <- call[i-1]'s sp
168 l32e a4, a7, -32 /* restore a4 from call[i]'s stack frame */
169 l32e a5, a7, -28 /* restore a5 from call[i]'s stack frame */
170 l32e a6, a7, -24 /* restore a6 from call[i]'s stack frame */
171 l32e a7, a7, -20 /* restore a7 from call[i]'s stack frame */
200 s32e a7, a0, -36 /* save a7 to end of call[j]'s stack frame */
233 l32e a7, a11, -36 /* restore a7 from end of call[i]'s stack frame */
Dcrt1.S42 # define ARG2 a7 /* 2nd outgoing call argument */
163 movi a7, _bss_table_end
164 bgeu a6, a7, .L3zte
186 bltu a6, a7, .L0zte /* loop until end of table of *.bss sections */
Duserspace.S124 l32i a7, a3, ___xtensa_irq_bsa_t_a3_OFFSET
222 mov a1, a7 /* stack start (low address) */
237 s32i a7, a1, 0
261 l32i a7, a1, 16
Dcoredump.c71 uint32_t a7; member
161 arch_blk.r.a7 = frame->blks[regs_blk_remaining].r3; in arch_coredump_info_dump()
Dthread.c96 frame->a7 = (uintptr_t)arg1; /* a7 */ in init_stack()
Dxtensa_asm2_util.S65 s32i a7, a1, 12
112 l32i a7, a2, 12
/Zephyr-Core-3.6.0/include/zephyr/arch/arm64/
Darm-smccc.h22 unsigned long a7; member
43 unsigned long a6, unsigned long a7,
56 unsigned long a6, unsigned long a7,
/Zephyr-Core-3.6.0/arch/xtensa/core/startup/
Dreset_vector.S111 rer a7, a2
113 extui a4, a7, 1, 2
243 movi a7, PWRSTAT_WAKEUP_RESET
246 bbci.l a7, PWRSTAT_WAKEUP_RESET_SHIFT, 1f
249 addi a5, a7, - PWRSTAT_WAKEUP_RESET
251 movnez a7, a5, a4
256 bbci.l a7, PWRSTAT_CACHES_LOST_POWER_SHIFT, .Lpso_restore
334 bbci.l a7, PWRSTAT_WAKEUP_RESET_SHIFT, .Lcoldstart
403 movi a7, 1 /* MPU entry vaddr 0, with valid bit set */
423 sub a7, a7, a4 /* next 512MB region (last to first) */
[all …]
/Zephyr-Core-3.6.0/arch/riscv/core/
Dcoredump.c27 uint32_t a7; member
79 arch_blk.r.a7 = esf->a7; in arch_coredump_info_dump()
Dfatal.c48 LOG_ERR(" a7: " PR_REG, esf->a7); in z_riscv_fatal_error()
/Zephyr-Core-3.6.0/arch/xtensa/include/
Dxtensa_asm2_context.h180 uintptr_t a7; member
201 uintptr_t a7; member
217 uintptr_t a7; member
/Zephyr-Core-3.6.0/include/zephyr/drivers/sip_svc/
Dsip_svc_driver.h74 unsigned long *a7, char *buf, size_t size);
273 unsigned long *a7, char *buf, size_t size);
278 unsigned long *a7, char *buf, size_t size) in z_impl_sip_svc_plat_async_res_req() argument
292 __ASSERT(a7, "a7 shouldn't be NULL"); in z_impl_sip_svc_plat_async_res_req()
295 return api->sip_svc_plat_async_res_req(dev, a0, a1, a2, a3, a4, a5, a6, a7, buf, size); in z_impl_sip_svc_plat_async_res_req()
Dsip_svc_proto.h142 unsigned long a7; member
/Zephyr-Core-3.6.0/include/zephyr/arch/riscv/
Dexception.h72 unsigned long a7; /* function argument */ member
/Zephyr-Core-3.6.0/drivers/sip_svc/
Dsip_smc_intel_socfpga.c120 unsigned long *a7, char *buf, size_t size) in intel_sip_smc_plat_async_res_req() argument
202 LOG_DBG("\tres->a7 %08lx", res->a7); in intel_sip_secure_monitor_call()
/Zephyr-Core-3.6.0/soc/xtensa/intel_adsp/ace/
Dpower_down.S35 #define temp_reg1 a7
/Zephyr-Core-3.6.0/soc/xtensa/intel_adsp/cavs/
Dpower_down_cavs.S40 #define temp_reg1 a7
/Zephyr-Core-3.6.0/subsys/sip_svc/
Dsip_svc_agilex_mailbox_shell.c143 request.a7 = 0; in cmd_close()
311 request.a7 = 0; in cmd_send()
Dsip_svc_subsys.c516 request.a5, request.a6, request.a7, &res); in sip_svc_request_handler()
562 unsigned long a7 = 0; in sip_svc_async_response_handler() local
576 if (sip_svc_plat_async_res_req(ctrl->dev, &a0, &a1, &a2, &a3, &a4, &a5, &a6, &a7, in sip_svc_async_response_handler()
586 sip_supervisory_call(ctrl->dev, a0, a1, a2, a3, a4, a5, a6, a7, &res); in sip_svc_async_response_handler()
Dsip_svc_shell.c307 request.a7 = strtoul(argv[10], &endptr, 16); in cmd_send()
/Zephyr-Core-3.6.0/arch/riscv/core/offsets/
Doffsets.c108 GEN_OFFSET_SYM(z_arch_esf_t, a7);
/Zephyr-Core-3.6.0/boards/riscv/litex_vexriscv/doc/
Dindex.rst20 <https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists>`_
104 ./make.py --board=arty --variant=a7-35 --build --toolchain=symbiflow
110 ./make.py --board=arty --variant=a7-100 --build --toolchain=symbiflow
/Zephyr-Core-3.6.0/tests/lib/cmsis_dsp/common/
Dtest_common.h65 #define DEFINE_TEST_VARIANT7(suite, name, variant, a1, a2, a3, a4, a5, a6, a7) \ argument
68 test_##name(a1, a2, a3, a4, a5, a6, a7); \
/Zephyr-Core-3.6.0/include/zephyr/
Ddevicetree.h4460 #define DT_CAT7(a1, a2, a3, a4, a5, a6, a7) \ argument
4461 a1 ## a2 ## a3 ## a4 ## a5 ## a6 ## a7
4463 #define DT_CAT8(a1, a2, a3, a4, a5, a6, a7, a8) \ argument
4464 a1 ## a2 ## a3 ## a4 ## a5 ## a6 ## a7 ## a8

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