1 /* 2 * Copyright (c) 2023 Synopsys. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * @brief ARC Cluster registers and accessors 10 */ 11 12 #ifndef ZEPHYR_INCLUDE_ARCH_ARC_CLUSTER_H_ 13 #define ZEPHYR_INCLUDE_ARCH_ARC_CLUSTER_H_ 14 15 #include <zephyr/arch/arc/v2/aux_regs.h> 16 #include <zephyr/sys/util_macro.h> 17 18 /* Cluster AUX */ 19 #define _ARC_REG_CLN_BCR 0xcf 20 21 #define _ARC_CLNR_ADDR 0x640 /* CLN address for CLNR_DATA */ 22 #define _ARC_CLNR_DATA 0x641 /* CLN data indicated by CLNR_ADDR */ 23 #define _ARC_CLNR_DATA_NXT 0x642 /* CLNR_DATA and then CLNR_ADDR++ */ 24 #define _ARC_CLNR_BCR_0 0xF61 25 #define _ARC_CLNR_BCR_1 0xF62 26 #define _ARC_CLNR_BCR_2 0xF63 27 #define _ARC_CLNR_SCM_BCR_0 0xF64 28 #define _ARC_CLNR_SCM_BCR_1 0xF65 29 30 #define _ARC_REG_CLN_BCR_VER_MAJOR_ARCV3_MIN 32 /* Minimal version of cluster in ARCv3 */ 31 #define _ARC_CLN_BCR_VER_MAJOR_MASK 0xff 32 #define _ARC_CLNR_BCR_0_HAS_SCM BIT(29) 33 34 /* Cluster registers (not in the AUX address space - indirect access via CLNR_ADDR + CLNR_DATA) */ 35 #define ARC_CLN_MST_NOC_0_BCR 0 36 #define ARC_CLN_MST_NOC_1_BCR 1 37 #define ARC_CLN_MST_NOC_2_BCR 2 38 #define ARC_CLN_MST_NOC_3_BCR 3 39 #define ARC_CLN_MST_PER_0_BCR 16 40 #define ARC_CLN_MST_PER_1_BCR 17 41 #define ARC_CLN_PER_0_BASE 2688 42 #define ARC_CLN_PER_0_SIZE 2689 43 #define ARC_CLN_PER_1_BASE 2690 44 #define ARC_CLN_PER_1_SIZE 2691 45 46 #define ARC_CLN_SCM_BCR_0 100 47 #define ARC_CLN_SCM_BCR_1 101 48 49 #define ARC_CLN_MST_NOC_0_0_ADDR 292 50 #define ARC_CLN_MST_NOC_0_0_SIZE 293 51 #define ARC_CLN_MST_NOC_0_1_ADDR 2560 52 #define ARC_CLN_MST_NOC_0_1_SIZE 2561 53 #define ARC_CLN_MST_NOC_0_2_ADDR 2562 54 #define ARC_CLN_MST_NOC_0_2_SIZE 2563 55 #define ARC_CLN_MST_NOC_0_3_ADDR 2564 56 #define ARC_CLN_MST_NOC_0_3_SIZE 2565 57 #define ARC_CLN_MST_NOC_0_4_ADDR 2566 58 #define ARC_CLN_MST_NOC_0_4_SIZE 2567 59 60 #define ARC_CLN_PER0_BASE 2688 61 #define ARC_CLN_PER0_SIZE 2689 62 63 #define ARC_CLN_SHMEM_ADDR 200 64 #define ARC_CLN_SHMEM_SIZE 201 65 #define ARC_CLN_CACHE_ADDR_LO0 204 66 #define ARC_CLN_CACHE_ADDR_LO1 205 67 #define ARC_CLN_CACHE_ADDR_HI0 206 68 #define ARC_CLN_CACHE_ADDR_HI1 207 69 #define ARC_CLN_CACHE_CMD 207 70 #define ARC_CLN_CACHE_CMD_OP_NOP 0b0000 71 #define ARC_CLN_CACHE_CMD_OP_LOOKUP 0b0001 72 #define ARC_CLN_CACHE_CMD_OP_PROBE 0b0010 73 #define ARC_CLN_CACHE_CMD_OP_IDX_INV 0b0101 74 #define ARC_CLN_CACHE_CMD_OP_IDX_CLN 0b0110 75 #define ARC_CLN_CACHE_CMD_OP_IDX_CLN_INV 0b0111 76 #define ARC_CLN_CACHE_CMD_OP_REG_INV 0b1001 77 #define ARC_CLN_CACHE_CMD_OP_REG_CLN 0b1010 78 #define ARC_CLN_CACHE_CMD_OP_REG_CLN_INV 0b1011 79 #define ARC_CLN_CACHE_CMD_OP_ADDR_INV 0b1101 80 #define ARC_CLN_CACHE_CMD_OP_ADDR_CLN 0b1110 81 #define ARC_CLN_CACHE_CMD_OP_ADDR_CLN_INV 0b1111 82 #define ARC_CLN_CACHE_CMD_INCR BIT(4) 83 84 #define ARC_CLN_CACHE_STATUS 209 85 #define ARC_CLN_CACHE_STATUS_BUSY BIT(23) 86 #define ARC_CLN_CACHE_STATUS_DONE BIT(24) 87 #define ARC_CLN_CACHE_STATUS_MASK BIT(26) 88 #define ARC_CLN_CACHE_STATUS_EN BIT(27) 89 #define ARC_CLN_CACHE_ERR 210 90 #define ARC_CLN_CACHE_ERR_ADDR0 211 91 #define ARC_CLN_CACHE_ERR_ADDR1 212 92 93 arc_cln_read_reg_nolock(unsigned int reg)94static inline unsigned int arc_cln_read_reg_nolock(unsigned int reg) 95 { 96 z_arc_v2_aux_reg_write(_ARC_CLNR_ADDR, reg); 97 return z_arc_v2_aux_reg_read(_ARC_CLNR_DATA); 98 } 99 arc_cln_write_reg_nolock(unsigned int reg,unsigned int data)100static inline void arc_cln_write_reg_nolock(unsigned int reg, unsigned int data) 101 { 102 z_arc_v2_aux_reg_write(_ARC_CLNR_ADDR, reg); 103 z_arc_v2_aux_reg_write(_ARC_CLNR_DATA, data); 104 } 105 106 #endif /* ZEPHYR_INCLUDE_ARCH_ARC_CLUSTER_H_ */ 107
