TIMER_MCLK_DIV_ADDR (reference) in projects: Zephyr-Core-3.6.0

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Searched refs:TIMER_MCLK_DIV_ADDR (Results 1 – 2 of 2) sorted by relevance

/Zephyr-Core-3.6.0/drivers/audio/
D	tlv320dac310x.h	`124 #define TIMER_MCLK_DIV_ADDR (struct reg_addr){3, 16} macro`
D	tlv320dac310x.c	`349 codec_write_reg(dev, TIMER_MCLK_DIV_ADDR, in codec_configure_clocks() 508 codec_read_reg(dev, TIMER_MCLK_DIV_ADDR, &val); in codec_read_all_regs()`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
acpica-3.5.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
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babblesim_ext_2G4_modem_BLE_simple-3.6.0-3.5.0
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babblesim_ext_2G4_modem_magic-3.6.0-3.5.0-3.4.0
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