1 /*gpio_dw_registers.h - Private gpio's registers header*/ 2 3 /* 4 * Copyright (c) 2015 Intel Corporation. 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 9 #ifndef ZEPHYR_DRIVERS_GPIO_GPIO_DW_REGISTERS_H_ 10 #define ZEPHYR_DRIVERS_GPIO_GPIO_DW_REGISTERS_H_ 11 12 /** This definition of GPIO related registers supports four ports: A, B, C, D 13 * yet only PORTA supports interrupts and debounce. 14 */ 15 #define SWPORTA_DR 0x00 16 #define SWPORTA_DDR 0x04 17 #define SWPORTA_CTL 0x08 18 #define SWPORTB_DR 0x0c 19 #define SWPORTB_DDR 0x10 20 #define SWPORTB_CTL 0x14 21 #define SWPORTC_DR 0x18 22 #define SWPORTC_DDR 0x1c 23 #define SWPORTC_CTL 0x20 24 #define SWPORTD_DR 0x24 25 #define SWPORTD_DDR 0x28 26 #define SWPORTD_CTL 0x2c 27 #define INTEN 0x30 28 #define INTMASK 0x34 29 #define INTTYPE_LEVEL 0x38 30 #define INT_POLARITY 0x3c 31 #define INTSTATUS 0x40 32 #define RAW_INTSTATUS 0x44 33 #define PORTA_DEBOUNCE 0x48 34 #define PORTA_EOI 0x4c 35 #define EXT_PORTA 0x50 36 #define EXT_PORTB 0x54 37 #define EXT_PORTC 0x58 38 #define EXT_PORTD 0x5c 39 #define INT_CLOCK_SYNC 0x60 /* alias LS_SYNC */ 40 #define VER_ID_CODE 0x6c 41 #define CONFIG_REG2 0x70 42 #define CONFIG_REG1 0x74 43 44 #define LS_SYNC_POS (0) 45 46 #endif /* ZEPHYR_DRIVERS_GPIO_GPIO_DW_REGISTERS_H_ */ 47
