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Searched refs:STM32_SRC_PLL_P (Results 1 – 12 of 12) sorted by relevance

/Zephyr-Core-3.6.0/include/zephyr/dt-bindings/clock/
Dstm32f4_clock.h32 #define STM32_SRC_PLL_P (STM32_SRC_LSI + 1) macro
33 #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1)
Dstm32wb_clock.h36 #define STM32_SRC_PLL_P (STM32_SRC_PCLK + 1) macro
37 #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1)
Dstm32wl_clock.h36 #define STM32_SRC_PLL_P (STM32_SRC_PCLK + 1) macro
37 #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1)
Dstm32g0_clock.h34 #define STM32_SRC_PLL_P (STM32_SRC_PCLK + 1) macro
35 #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1)
Dstm32f7_clock.h34 #define STM32_SRC_PLL_P (STM32_SRC_HSI + 1) macro
35 #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1)
Dstm32g4_clock.h37 #define STM32_SRC_PLL_P (STM32_SRC_PCLK + 1) macro
38 #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1)
Dstm32l4_clock.h35 #define STM32_SRC_PLL_P (STM32_SRC_PCLK + 1) macro
36 #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1)
/Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/
Dtest_stm32_clock_configuration_adc.c90 #if defined(STM32_SRC_PLL_P) in ZTEST()
91 case STM32_SRC_PLL_P: in ZTEST()
/Zephyr-Core-3.6.0/drivers/clock_control/
Dclock_stm32_ll_common.c164 #if defined(STM32_SRC_PLL_P) in enabled_clock()
165 case STM32_SRC_PLL_P: in enabled_clock()
352 #if defined(STM32_SRC_PLL_P) & STM32_PLL_P_ENABLED in stm32_clock_control_get_subsys_rate()
353 case STM32_SRC_PLL_P: in stm32_clock_control_get_subsys_rate()
517 #if defined(STM32_SRC_PLL_P) & STM32_PLL_P_ENABLED in set_up_plls()
/Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Dg0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay81 <&rcc STM32_SRC_PLL_P ADC_SEL(1)>;
Dg4_i2c1_hsi_adc1_pllp.overlay72 <&rcc STM32_SRC_PLL_P ADC12_SEL(1)>;
Dwl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay100 <&rcc STM32_SRC_PLL_P ADC_SEL(2)>;