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Searched refs:STM32_SRC_PLL2_Q (Results 1 – 7 of 7) sorted by relevance

/Zephyr-Core-3.6.0/boards/arm/stm32h735g_disco/
Dstm32h735g_disco.dts207 <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
221 <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
235 <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
/Zephyr-Core-3.6.0/include/zephyr/dt-bindings/clock/
Dstm32h7_clock.h29 #define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1) macro
30 #define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1)
Dstm32u5_clock.h29 #define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1) macro
30 #define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1)
Dstm32h5_clock.h28 #define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1) macro
29 #define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1)
/Zephyr-Core-3.6.0/drivers/clock_control/
Dclock_stm32_ll_h5.c133 ((src_clk == STM32_SRC_PLL2_Q) && IS_ENABLED(STM32_PLL2_Q_ENABLED)) || in enabled_clock()
297 case STM32_SRC_PLL2_Q: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_u5.c137 ((src_clk == STM32_SRC_PLL2_Q) && IS_ENABLED(STM32_PLL2_Q_ENABLED)) || in enabled_clock()
310 case STM32_SRC_PLL2_Q: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_h7.c348 ((src_clk == STM32_SRC_PLL2_Q) && IS_ENABLED(STM32_PLL2_Q_ENABLED)) || in enabled_clock()
527 case STM32_SRC_PLL2_Q: in stm32_clock_control_get_subsys_rate()