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Searched refs:STM32_SRC_MSIK (Results 1 – 3 of 3) sorted by relevance

/Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/
Dspi1_msik.overlay21 <&rcc STM32_SRC_MSIK SPI1_SEL(3)>;
/Zephyr-Core-3.6.0/include/zephyr/dt-bindings/clock/
Dstm32u5_clock.h23 #define STM32_SRC_MSIK (STM32_SRC_MSIS + 1) macro
25 #define STM32_SRC_PLL1_P (STM32_SRC_MSIK + 1)
/Zephyr-Core-3.6.0/drivers/clock_control/
Dclock_stm32_ll_u5.c132 ((src_clk == STM32_SRC_MSIK) && IS_ENABLED(STM32_MSIK_ENABLED)) || in enabled_clock()
258 case STM32_SRC_MSIK: in stm32_clock_control_get_subsys_rate()