STM32_PLL_SRC_HSI (reference) in projects: Zephyr-Core-3.6.0

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Searched refs:STM32_PLL_SRC_HSI (Results 1 – 17 of 17) sorted by relevance

/Zephyr-Core-3.6.0/drivers/clock_control/
D	clock_stm32f0_f3.c	`81 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in config_pll_sysclock() 92 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in config_pll_sysclock() 141 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pllout_frequency() 152 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pllout_frequency()`
D	clock_stm32g4.c	`28 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pll_source() 44 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pllsrc_frequency()`
D	clock_stm32g0.c	`29 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pll_source() 45 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pllsrc_frequency()`
D	clock_stm32l0_l1.c	`34 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pll_source() 50 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pllsrc_frequency()`
D	clock_stm32l4_l5_wb_wl.c	`36 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pll_source() 54 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pllsrc_frequency()`
D	clock_stm32f2_f4_f7.c	`27 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pll_source() 43 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pllsrc_frequency()`
D	clock_stm32f1.c	`59 if (!IS_ENABLED(STM32_PLL_SRC_HSI)) { in config_pll_sysclock() 92 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in config_pll_sysclock()`
D	clock_stm32_ll_wba.c	`130 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pllsrc_frequency() 144 if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in get_pllsrc() 373 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in set_up_plls()`
D	clock_stm32_ll_h5.c	`53 if ((IS_ENABLED(STM32_PLL_SRC_HSI) && pll_id == PLL1_ID) \|\| in get_pllsrc_frequency() 442 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in set_up_plls() 620 if (IS_ENABLED(STM32_PLL_SRC_HSI) \|\| in set_up_fixed_clock_sources()`
D	clock_stm32_ll_u5.c	`56 if ((IS_ENABLED(STM32_PLL_SRC_HSI) && pll_id == PLL1_ID) \|\| in get_pllsrc_frequency() 495 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in set_up_plls()`
D	clock_stm32_ll_h7.c	`51 #if defined(STM32_PLL_SRC_HSI) 696 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) { in set_up_plls()`
/Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/src/
D	test_stm32_clock_configuration.c	`59 #elif STM32_PLL_SRC_HSI in ZTEST()`
/Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/src/
D	test_stm32_clock_configuration.c	`64 #elif STM32_PLL_SRC_HSI in ZTEST()`
/Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/src/
D	test_stm32_clock_configuration.c	`64 #elif STM32_PLL_SRC_HSI in ZTEST()`
/Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/src/
D	test_stm32_clock_configuration.c	`64 #elif STM32_PLL_SRC_HSI in ZTEST()`
/Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/src/
D	test_stm32_clock_configuration.c	`73 #elif STM32_PLL_SRC_HSI in ZTEST()`
/Zephyr-Core-3.6.0/include/zephyr/drivers/clock_control/
D	stm32_clock_control.h	`231 #define STM32_PLL_SRC_HSI 1 macro`

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