STM32_PLL_P_ENABLED (reference) in projects: Zephyr-Core-3.6.0

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Searched refs:STM32_PLL_P_ENABLED (Results 1 – 6 of 6) sorted by relevance

/Zephyr-Core-3.6.0/drivers/clock_control/
D	clock_stm32_ll_common.c	`166 if (!IS_ENABLED(STM32_PLL_P_ENABLED)) { in enabled_clock() 352 #if defined(STM32_SRC_PLL_P) & STM32_PLL_P_ENABLED in stm32_clock_control_get_subsys_rate() 517 #if defined(STM32_SRC_PLL_P) & STM32_PLL_P_ENABLED in set_up_plls()`
D	clock_stm32_ll_wba.c	`52 ((src_clk == STM32_SRC_PLL1_P) && IS_ENABLED(STM32_PLL_P_ENABLED)) \|\| in enabled_clock() 393 if (IS_ENABLED(STM32_PLL_P_ENABLED)) { in set_up_plls()`
D	clock_stm32_ll_h5.c	`129 ((src_clk == STM32_SRC_PLL1_P) && IS_ENABLED(STM32_PLL_P_ENABLED)) \|\| in enabled_clock() 467 if (IS_ENABLED(STM32_PLL_P_ENABLED)) { in set_up_plls()`
D	clock_stm32_ll_u5.c	`133 ((src_clk == STM32_SRC_PLL1_P) && IS_ENABLED(STM32_PLL_P_ENABLED)) \|\| in enabled_clock() 527 if (IS_ENABLED(STM32_PLL_P_ENABLED)) { in set_up_plls()`
D	clock_stm32_ll_h7.c	`344 ((src_clk == STM32_SRC_PLL1_P) && IS_ENABLED(STM32_PLL_P_ENABLED)) \|\| in enabled_clock() 721 if (IS_ENABLED(STM32_PLL_P_ENABLED)) { in set_up_plls()`
/Zephyr-Core-3.6.0/include/zephyr/drivers/clock_control/
D	stm32_clock_control.h	`140 #define STM32_PLL_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_p) macro`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
acpica-3.5.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
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