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Searched refs:STM32_PLL_M_DIVISOR (Results 1 – 10 of 10) sorted by relevance

/Zephyr-Core-3.6.0/drivers/clock_control/
Dclock_stm32_ll_wba.c214 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
220 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
226 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
380 r = get_vco_input_range(STM32_PLL_M_DIVISOR, &vco_input_range); in set_up_plls()
385 LL_RCC_PLL1_SetDivider(STM32_PLL_M_DIVISOR); in set_up_plls()
Dclock_stm32g4.c66 pllm(STM32_PLL_M_DIVISOR), in config_pll_sysclock()
Dclock_stm32g0.c62 pllm(STM32_PLL_M_DIVISOR), in config_pll_sysclock()
Dclock_stm32_ll_u5.c106 STM32_PLL_M_DIVISOR, in get_sysclk_frequency()
286 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
292 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
298 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
432 tmp = MIN(tmp / STM32_PLL_M_DIVISOR / 8000000, 16); in set_epod_booster()
509 r = get_vco_input_range(STM32_PLL_M_DIVISOR, &vco_input_range, PLL1_ID); in set_up_plls()
514 LL_RCC_PLL1_SetDivider(STM32_PLL_M_DIVISOR); in set_up_plls()
Dclock_stm32_ll_h5.c103 STM32_PLL_M_DIVISOR, in get_sysclk_frequency()
273 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
279 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
285 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
449 r = get_vco_input_range(STM32_PLL_M_DIVISOR, &vco_input_range, PLL1_ID); in set_up_plls()
456 LL_RCC_PLL1_SetM(STM32_PLL_M_DIVISOR); in set_up_plls()
Dclock_stm32l4_l5_wb_wl.c81 pllm(STM32_PLL_M_DIVISOR), in config_pll_sysclock()
Dclock_stm32_ll_h7.c68 STM32_PLL_M_DIVISOR,\
220 STM32_PLL_M_DIVISOR, in get_hclk_frequency()
503 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
509 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
515 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
704 r = get_vco_input_range(STM32_PLL_M_DIVISOR, &vco_input_range); in set_up_plls()
711 LL_RCC_PLL1_SetM(STM32_PLL_M_DIVISOR); in set_up_plls()
Dclock_stm32f2_f4_f7.c63 pllm(STM32_PLL_M_DIVISOR), in config_pll_sysclock()
Dclock_stm32_ll_common.c355 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
363 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
371 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
/Zephyr-Core-3.6.0/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h138 #define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m) macro
152 #define STM32_PLLI2S_M_DIVISOR STM32_PLL_M_DIVISOR