STM32_PLL3_P_DIVISOR (reference) in projects: Zephyr-Core-3.6.0

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/Zephyr-Core-3.6.0/drivers/clock_control/
D	clock_stm32_ll_h5.c	`315 STM32_PLL3_P_DIVISOR); in stm32_clock_control_get_subsys_rate() 575 LL_RCC_PLL3_SetP(STM32_PLL3_P_DIVISOR); in set_up_plls()`
D	clock_stm32_ll_u5.c	`328 STM32_PLL3_P_DIVISOR); in stm32_clock_control_get_subsys_rate() 634 LL_RCC_PLL3_SetP(STM32_PLL3_P_DIVISOR); in set_up_plls()`
D	clock_stm32_ll_h7.c	`545 STM32_PLL3_P_DIVISOR); in stm32_clock_control_get_subsys_rate() 798 LL_RCC_PLL3_SetP(STM32_PLL3_P_DIVISOR); in set_up_plls()`
/Zephyr-Core-3.6.0/include/zephyr/drivers/clock_control/
D	stm32_clock_control.h	`187 #define STM32_PLL3_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_p, 1) macro`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
acpica-3.5.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
babblesim_ext_2G4_modem_BLE_simple-3.4.0
babblesim_ext_2G4_modem_BLE_simple-3.6.0-3.5.0
babblesim_ext_2G4_modem_BLE_simple-3.7.0
babblesim_ext_2G4_modem_magic-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_modem_magic-3.7.0
babblesim_ext_2G4_phy_v1-3.4.0
babblesim_ext_2G4_phy_v1-3.6.0-3.5.0
babblesim_ext_2G4_phy_v1-3.7.0
babblesim_ext_libCryptov1-3.7.0-3.6.0-3.5.0-3.4.0
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zscilib-3.4.0