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Searched refs:STM32_PLL2_P_ENABLED (Results 1 – 4 of 4) sorted by relevance

/Zephyr-Core-3.6.0/drivers/clock_control/
Dclock_stm32_ll_h5.c132 ((src_clk == STM32_SRC_PLL2_P) && IS_ENABLED(STM32_PLL2_P_ENABLED)) || in enabled_clock()
520 if (IS_ENABLED(STM32_PLL2_P_ENABLED)) { in set_up_plls()
Dclock_stm32_ll_u5.c136 ((src_clk == STM32_SRC_PLL2_P) && IS_ENABLED(STM32_PLL2_P_ENABLED)) || in enabled_clock()
581 if (IS_ENABLED(STM32_PLL2_P_ENABLED)) { in set_up_plls()
Dclock_stm32_ll_h7.c347 ((src_clk == STM32_SRC_PLL2_P) && IS_ENABLED(STM32_PLL2_P_ENABLED)) || in enabled_clock()
759 if (IS_ENABLED(STM32_PLL2_P_ENABLED)) { in set_up_plls()
/Zephyr-Core-3.6.0/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h171 #define STM32_PLL2_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_p) macro