1 /* 2 * Copyright (c) 2017 Linaro Limited 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32_PINCTRL_H_ 8 #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32_PINCTRL_H_ 9 10 #include <zephyr/dt-bindings/pinctrl/stm32-pinctrl-common.h> 11 12 /* Adapted from Linux: include/dt-bindings/pinctrl/stm32-pinfunc.h */ 13 14 /** 15 * @brief Pin modes 16 */ 17 18 #define STM32_AF0 0x0 19 #define STM32_AF1 0x1 20 #define STM32_AF2 0x2 21 #define STM32_AF3 0x3 22 #define STM32_AF4 0x4 23 #define STM32_AF5 0x5 24 #define STM32_AF6 0x6 25 #define STM32_AF7 0x7 26 #define STM32_AF8 0x8 27 #define STM32_AF9 0x9 28 #define STM32_AF10 0xa 29 #define STM32_AF11 0xb 30 #define STM32_AF12 0xc 31 #define STM32_AF13 0xd 32 #define STM32_AF14 0xe 33 #define STM32_AF15 0xf 34 #define STM32_ANALOG 0x10 35 #define STM32_GPIO 0x11 36 37 /** 38 * @brief Macro to generate pinmux int using port, pin number and mode arguments 39 * This is inspired from Linux equivalent st,stm32f429-pinctrl binding 40 */ 41 42 #define STM32_MODE_SHIFT 0U 43 #define STM32_MODE_MASK 0x1FU 44 #define STM32_LINE_SHIFT 5U 45 #define STM32_LINE_MASK 0xFU 46 #define STM32_PORT_SHIFT 9U 47 #define STM32_PORT_MASK 0xFU 48 49 /** 50 * @brief Pin configuration configuration bit field. 51 * 52 * Fields: 53 * 54 * - mode [ 0 : 4 ] 55 * - line [ 5 : 8 ] 56 * - port [ 9 : 12 ] 57 * 58 * @param port Port ('A'..'K') 59 * @param line Pin (0..15) 60 * @param mode Mode (ANALOG, GPIO_IN, ALTERNATE). 61 */ 62 #define STM32_PINMUX(port, line, mode) \ 63 (((((port) - 'A') & STM32_PORT_MASK) << STM32_PORT_SHIFT) | \ 64 (((line) & STM32_LINE_MASK) << STM32_LINE_SHIFT) | \ 65 (((STM32_ ## mode) & STM32_MODE_MASK) << STM32_MODE_SHIFT)) 66 67 /** 68 * @brief PIN configuration bitfield 69 * 70 * Pin configuration is coded with the following 71 * fields 72 * Alternate Functions [ 0 : 3 ] 73 * GPIO Mode [ 4 : 5 ] 74 * GPIO Output type [ 6 ] 75 * GPIO Speed [ 7 : 8 ] 76 * GPIO PUPD config [ 9 : 10 ] 77 * GPIO Output data [ 11 ] 78 * 79 */ 80 81 /* GPIO Mode */ 82 #define STM32_MODER_INPUT_MODE (0x0 << STM32_MODER_SHIFT) 83 #define STM32_MODER_OUTPUT_MODE (0x1 << STM32_MODER_SHIFT) 84 #define STM32_MODER_ALT_MODE (0x2 << STM32_MODER_SHIFT) 85 #define STM32_MODER_ANALOG_MODE (0x3 << STM32_MODER_SHIFT) 86 #define STM32_MODER_MASK 0x3 87 #define STM32_MODER_SHIFT 4 88 89 /* GPIO Output type */ 90 #define STM32_OTYPER_PUSH_PULL (0x0 << STM32_OTYPER_SHIFT) 91 #define STM32_OTYPER_OPEN_DRAIN (0x1 << STM32_OTYPER_SHIFT) 92 #define STM32_OTYPER_MASK 0x1 93 #define STM32_OTYPER_SHIFT 6 94 95 /* GPIO speed */ 96 #define STM32_OSPEEDR_LOW_SPEED (0x0 << STM32_OSPEEDR_SHIFT) 97 #define STM32_OSPEEDR_MEDIUM_SPEED (0x1 << STM32_OSPEEDR_SHIFT) 98 #define STM32_OSPEEDR_HIGH_SPEED (0x2 << STM32_OSPEEDR_SHIFT) 99 #define STM32_OSPEEDR_VERY_HIGH_SPEED (0x3 << STM32_OSPEEDR_SHIFT) 100 #define STM32_OSPEEDR_MASK 0x3 101 #define STM32_OSPEEDR_SHIFT 7 102 103 /* GPIO High impedance/Pull-up/pull-down */ 104 #define STM32_PUPDR_NO_PULL (0x0 << STM32_PUPDR_SHIFT) 105 #define STM32_PUPDR_PULL_UP (0x1 << STM32_PUPDR_SHIFT) 106 #define STM32_PUPDR_PULL_DOWN (0x2 << STM32_PUPDR_SHIFT) 107 #define STM32_PUPDR_MASK 0x3 108 #define STM32_PUPDR_SHIFT 9 109 110 /* GPIO plain output value */ 111 #define STM32_ODR_0 (0x0 << STM32_ODR_SHIFT) 112 #define STM32_ODR_1 (0x1 << STM32_ODR_SHIFT) 113 #define STM32_ODR_MASK 0x1 114 #define STM32_ODR_SHIFT 11 115 116 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32_PINCTRL_H_ */ 117
