1 /* 2 * Copyright 2022-2023 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /* 8 * SD card specification 9 */ 10 11 #ifndef ZEPHYR_SUBSYS_SD_SPEC_H_ 12 #define ZEPHYR_SUBSYS_SD_SPEC_H_ 13 14 #include <stdint.h> 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 /** 21 * @brief SD specification command opcodes 22 * 23 * SD specification command opcodes. Note that some command opcodes are 24 * specific to SDIO cards, or cards running in SPI mode instead of native SD 25 * mode. 26 */ 27 enum sd_opcode { 28 SD_GO_IDLE_STATE = 0, 29 MMC_SEND_OP_COND = 1, 30 SD_ALL_SEND_CID = 2, 31 SD_SEND_RELATIVE_ADDR = 3, 32 MMC_SEND_RELATIVE_ADDR = 3, 33 SDIO_SEND_OP_COND = 5, /* SDIO cards only */ 34 SD_SWITCH = 6, 35 SD_SELECT_CARD = 7, 36 SD_SEND_IF_COND = 8, 37 MMC_SEND_EXT_CSD = 8, 38 SD_SEND_CSD = 9, 39 SD_SEND_CID = 10, 40 SD_VOL_SWITCH = 11, 41 SD_STOP_TRANSMISSION = 12, 42 SD_SEND_STATUS = 13, 43 MMC_CHECK_BUS_TEST = 14, 44 SD_GO_INACTIVE_STATE = 15, 45 SD_SET_BLOCK_SIZE = 16, 46 SD_READ_SINGLE_BLOCK = 17, 47 SD_READ_MULTIPLE_BLOCK = 18, 48 SD_SEND_TUNING_BLOCK = 19, 49 MMC_SEND_BUS_TEST = 19, 50 MMC_SEND_TUNING_BLOCK = 21, 51 SD_SET_BLOCK_COUNT = 23, 52 SD_WRITE_SINGLE_BLOCK = 24, 53 SD_WRITE_MULTIPLE_BLOCK = 25, 54 SD_ERASE_BLOCK_START = 32, 55 SD_ERASE_BLOCK_END = 33, 56 SD_ERASE_BLOCK_OPERATION = 38, 57 SDIO_RW_DIRECT = 52, 58 SDIO_RW_EXTENDED = 53, 59 SD_APP_CMD = 55, 60 SD_SPI_READ_OCR = 58, /* SPI mode only */ 61 SD_SPI_CRC_ON_OFF = 59, /* SPI mode only */ 62 }; 63 64 /** 65 * @brief SD application command opcodes. 66 * 67 * all application command opcodes must be prefixed with a CMD55 command 68 * to inform the SD card the next command is an application-specific one. 69 */ 70 enum sd_app_cmd { 71 SD_APP_SET_BUS_WIDTH = 6, 72 SD_APP_SEND_STATUS = 13, 73 SD_APP_SEND_NUM_WRITTEN_BLK = 22, 74 SD_APP_SET_WRITE_BLK_ERASE_CNT = 23, 75 SD_APP_SEND_OP_COND = 41, 76 SD_APP_CLEAR_CARD_DETECT = 42, 77 SD_APP_SEND_SCR = 51, 78 }; 79 80 /** 81 * @brief Native SD mode R1 response status flags 82 * 83 * Native response flags for SD R1 response, used to check for error in command. 84 */ 85 enum sd_r1_status { 86 /* Bits 0-2 reserved */ 87 SD_R1_AUTH_ERR = BIT(3), 88 /* Bit 4 reserved for SDIO */ 89 SD_R1_APP_CMD = BIT(5), 90 SD_R1_FX_EVENT = BIT(6), 91 /* Bit 7 reserved */ 92 SD_R1_RDY_DATA = BIT(8), 93 SD_R1_CUR_STATE = (0xFU << 9), 94 SD_R1_ERASE_RESET = BIT(13), 95 SD_R1_ECC_DISABLED = BIT(14), 96 SD_R1_ERASE_SKIP = BIT(15), 97 SD_R1_CSD_OVERWRITE = BIT(16), 98 /* Bits 17-18 reserved */ 99 SD_R1_ERR = BIT(19), 100 SD_R1_CC_ERR = BIT(20), 101 SD_R1_ECC_FAIL = BIT(21), 102 SD_R1_ILLEGAL_CMD = BIT(22), 103 SD_R1_CRC_ERR = BIT(23), 104 SD_R1_UNLOCK_FAIL = BIT(24), 105 SD_R1_CARD_LOCKED = BIT(25), 106 SD_R1_WP_VIOLATION = BIT(26), 107 SD_R1_ERASE_PARAM = BIT(27), 108 SD_R1_ERASE_SEQ_ERR = BIT(28), 109 SD_R1_BLOCK_LEN_ERR = BIT(29), 110 SD_R1_ADDR_ERR = BIT(30), 111 SD_R1_OUT_OF_RANGE = BIT(31), 112 SD_R1_ERR_FLAGS = (SD_R1_AUTH_ERR | 113 SD_R1_ERASE_SKIP | 114 SD_R1_CSD_OVERWRITE | 115 SD_R1_ERR | 116 SD_R1_CC_ERR | 117 SD_R1_ECC_FAIL | 118 SD_R1_ILLEGAL_CMD | 119 SD_R1_CRC_ERR | 120 SD_R1_UNLOCK_FAIL | 121 SD_R1_WP_VIOLATION | 122 SD_R1_ERASE_PARAM | 123 SD_R1_ERASE_SEQ_ERR | 124 SD_R1_BLOCK_LEN_ERR | 125 SD_R1_ADDR_ERR | 126 SD_R1_OUT_OF_RANGE), 127 SD_R1ERR_NONE = 0, 128 }; 129 130 #define SD_R1_CURRENT_STATE(x) (((x) & SD_R1_CUR_STATE) >> 9U) 131 132 /** 133 * @brief SD current state values 134 * 135 * SD current state values, contained in R1 response data. 136 */ 137 enum sd_r1_current_state { 138 SDMMC_R1_IDLE = 0U, 139 SDMMC_R1_READY = 1U, 140 SDMMC_R1_IDENTIFY = 2U, 141 SDMMC_R1_STANDBY = 3U, 142 SDMMC_R1_TRANSFER = 4U, 143 SDMMC_R1_SEND_DATA = 5U, 144 SDMMC_R1_RECIVE_DATA = 6U, 145 SDMMC_R1_PROGRAM = 7U, 146 SDMMC_R1_DISCONNECT = 8U, 147 }; 148 149 /** 150 * @brief SPI SD mode R1 response status flags 151 * 152 * SPI mode R1 response flags. Used to check for error in SD SPI mode command. 153 */ 154 enum sd_spi_r1_error_flag { 155 SD_SPI_R1PARAMETER_ERR = BIT(6), 156 SD_SPI_R1ADDRESS_ERR = BIT(5), 157 SD_SPI_R1ERASE_SEQ_ERR = BIT(4), 158 SD_SPI_R1CMD_CRC_ERR = BIT(3), 159 SD_SPI_R1ILLEGAL_CMD_ERR = BIT(2), 160 SD_SPI_R1ERASE_RESET = BIT(1), 161 SD_SPI_R1IDLE_STATE = BIT(0), 162 }; 163 164 /** 165 * @brief SPI SD mode R2 response status flags 166 * 167 * SPI mode R2 response flags. Sent in response to SEND_STATUS command. Used 168 * to check status of SD card. 169 */ 170 enum sd_spi_r2_status { 171 SDHC_SPI_R2_CARD_LOCKED = BIT(8), 172 SDHC_SPI_R2_UNLOCK_FAIL = BIT(9), 173 SDHC_SPI_R2_ERR = BIT(10), 174 SDHC_SPI_R2_CC_ERR = BIT(11), 175 SDHC_SPI_R2_ECC_FAIL = BIT(12), 176 SDHC_SPI_R2_WP_VIOLATION = BIT(13), 177 SDHC_SPI_R2_ERASE_PARAM = BIT(14), 178 SDHC_SPI_R2_OUT_OF_RANGE = BIT(15), 179 }; 180 181 /* Byte length of SD SPI mode command */ 182 #define SD_SPI_CMD_SIZE 6 183 #define SD_SPI_CMD_BODY_SIZE (SD_SPI_CMD_SIZE - 1) 184 /* Byte length of CRC16 appended to data blocks in SPI mode */ 185 #define SD_SPI_CRC16_SIZE 2 186 187 /* SPI Command flags */ 188 #define SD_SPI_START 0x80 189 #define SD_SPI_TX 0x40 190 #define SD_SPI_CMD 0x3F 191 192 /* SPI Data block tokens */ 193 #define SD_SPI_TOKEN_SINGLE 0xFE 194 #define SD_SPI_TOKEN_MULTI_WRITE 0xFC 195 #define SD_SPI_TOKEN_STOP_TRAN 0xFD 196 197 /* SPI Data block responses */ 198 #define SD_SPI_RESPONSE_ACCEPTED 0x05 199 #define SD_SPI_RESPONSE_CRC_ERR 0x0B 200 #define SD_SPI_RESPONSE_WRITE_ERR 0x0C 201 202 /* Masks used in SD interface condition query (CMD8) */ 203 #define SD_IF_COND_VHS_MASK (0x0F << 8) 204 #define SD_IF_COND_VHS_3V3 BIT(8) 205 #define SD_IF_COND_CHECK 0xAA 206 207 /** 208 * @brief SD response types 209 * 210 * SD response types. Note that SPI mode has difference response types than 211 * cards in native SD mode. 212 */ 213 enum sd_rsp_type { 214 /* Native response types (lower 4 bits) */ 215 SD_RSP_TYPE_NONE = 0U, 216 SD_RSP_TYPE_R1 = 1U, 217 SD_RSP_TYPE_R1b = 2U, 218 SD_RSP_TYPE_R2 = 3U, 219 SD_RSP_TYPE_R3 = 4U, 220 SD_RSP_TYPE_R4 = 5U, 221 SD_RSP_TYPE_R5 = 6U, 222 SD_RSP_TYPE_R5b = 7U, 223 SD_RSP_TYPE_R6 = 8U, 224 SD_RSP_TYPE_R7 = 9U, 225 /* SPI response types (bits [7:4]) */ 226 SD_SPI_RSP_TYPE_R1 = (1U << 4), 227 SD_SPI_RSP_TYPE_R1b = (2U << 4), 228 SD_SPI_RSP_TYPE_R2 = (3U << 4), 229 SD_SPI_RSP_TYPE_R3 = (4U << 4), 230 SD_SPI_RSP_TYPE_R4 = (5U << 4), 231 SD_SPI_RSP_TYPE_R5 = (6U << 4), 232 SD_SPI_RSP_TYPE_R7 = (7U << 4), 233 }; 234 235 /** 236 * @brief SD support flags 237 * 238 * flags used by SD subsystem to determine support for SD card features. 239 */ 240 enum sd_support_flag { 241 SD_HIGH_CAPACITY_FLAG = BIT(1), 242 SD_4BITS_WIDTH = BIT(2), 243 SD_SDHC_FLAG = BIT(3), 244 SD_SDXC_FLAG = BIT(4), 245 SD_1800MV_FLAG = BIT(5), 246 SD_3000MV_FLAG = BIT(6), 247 SD_CMD23_FLAG = BIT(7), 248 SD_SPEED_CLASS_CONTROL_FLAG = BIT(8), 249 SD_MEM_PRESENT_FLAG = BIT(9), 250 }; 251 252 253 /** 254 * @brief SD OCR bit flags 255 * 256 * bit flags present in SD OCR response. Used to determine status and 257 * supported functions of SD card. 258 */ 259 enum sd_ocr_flag { 260 SD_OCR_PWR_BUSY_FLAG = BIT(31), 261 /*!< Power up busy status */ 262 SD_OCR_HOST_CAP_FLAG = BIT(30), 263 /*!< Card capacity status */ 264 SD_OCR_CARD_CAP_FLAG = SD_OCR_HOST_CAP_FLAG, 265 /*!< Card capacity status */ 266 SD_OCR_SWITCH_18_REQ_FLAG = BIT(24), 267 /*!< Switch to 1.8V request */ 268 SD_OCR_SWITCH_18_ACCEPT_FLAG = SD_OCR_SWITCH_18_REQ_FLAG, 269 /*!< Switch to 1.8V accepted */ 270 SD_OCR_VDD27_28FLAG = BIT(15), 271 /*!< VDD 2.7-2.8 */ 272 SD_OCR_VDD28_29FLAG = BIT(16), 273 /*!< VDD 2.8-2.9 */ 274 SD_OCR_VDD29_30FLAG = BIT(17), 275 /*!< VDD 2.9-3.0 */ 276 SD_OCR_VDD30_31FLAG = BIT(18), 277 /*!< VDD 2.9-3.0 */ 278 SD_OCR_VDD31_32FLAG = BIT(19), 279 /*!< VDD 3.0-3.1 */ 280 SD_OCR_VDD32_33FLAG = BIT(20), 281 /*!< VDD 3.1-3.2 */ 282 SD_OCR_VDD33_34FLAG = BIT(21), 283 /*!< VDD 3.2-3.3 */ 284 SD_OCR_VDD34_35FLAG = BIT(22), 285 /*!< VDD 3.3-3.4 */ 286 SD_OCR_VDD35_36FLAG = BIT(23), 287 /*!< VDD 3.4-3.5 */ 288 }; 289 290 /** 291 * @brief MMC OCR bit flags 292 * 293 * bit flags present in MMC OCR response. Used to determine status and 294 * supported functions of MMC card. 295 */ 296 enum mmc_ocr_flag { 297 MMC_OCR_VDD170_195FLAG = BIT(7), 298 MMC_OCR_VDD20_26FLAG = 0x7F << 8, 299 MMC_OCR_VDD27_36FLAG = 0x1FF << 15, 300 MMC_OCR_SECTOR_MODE = BIT(30), 301 MMC_OCR_PWR_BUSY_FLAG = BIT(31) 302 }; 303 304 #define SDIO_OCR_IO_NUMBER_SHIFT 28 305 /* Lower 24 bits hold SDIO I/O OCR */ 306 #define SDIO_IO_OCR_MASK 0xFFFFFF 307 308 /** 309 * @brief SDIO OCR bit flags 310 * 311 * bit flags present in SDIO OCR response. Used to determine status and 312 * supported functions of SDIO card. 313 */ 314 enum sdio_ocr_flag { 315 SDIO_OCR_IO_READY_FLAG = BIT(31), 316 SDIO_OCR_IO_NUMBER = (7U << 28U), /*!< Number of io function */ 317 SDIO_OCR_MEM_PRESENT_FLAG = BIT(27), /*!< Memory present flag */ 318 SDIO_OCR_180_VOL_FLAG = BIT(24), /*!< Switch to 1.8v signalling */ 319 SDIO_OCR_VDD20_21FLAG = BIT(8), /*!< VDD 2.0-2.1 */ 320 SDIO_OCR_VDD21_22FLAG = BIT(9), /*!< VDD 2.1-2.2 */ 321 SDIO_OCR_VDD22_23FLAG = BIT(10), /*!< VDD 2.2-2.3 */ 322 SDIO_OCR_VDD23_24FLAG = BIT(11), /*!< VDD 2.3-2.4 */ 323 SDIO_OCR_VDD24_25FLAG = BIT(12), /*!< VDD 2.4-2.5 */ 324 SDIO_OCR_VDD25_26FLAG = BIT(13), /*!< VDD 2.5-2.6 */ 325 SDIO_OCR_VDD26_27FLAG = BIT(14), /*!< VDD 2.6-2.7 */ 326 SDIO_OCR_VDD27_28FLAG = BIT(15), /*!< VDD 2.7-2.8 */ 327 SDIO_OCR_VDD28_29FLAG = BIT(16), /*!< VDD 2.8-2.9 */ 328 SDIO_OCR_VDD29_30FLAG = BIT(17), /*!< VDD 2.9-3.0 */ 329 SDIO_OCR_VDD30_31FLAG = BIT(18), /*!< VDD 2.9-3.0 */ 330 SDIO_OCR_VDD31_32FLAG = BIT(19), /*!< VDD 3.0-3.1 */ 331 SDIO_OCR_VDD32_33FLAG = BIT(20), /*!< VDD 3.1-3.2 */ 332 SDIO_OCR_VDD33_34FLAG = BIT(21), /*!< VDD 3.2-3.3 */ 333 SDIO_OCR_VDD34_35FLAG = BIT(22), /*!< VDD 3.3-3.4 */ 334 SDIO_OCR_VDD35_36FLAG = BIT(23), /*!< VDD 3.4-3.5 */ 335 }; 336 337 338 /** 339 * @brief SD switch arguments 340 * 341 * SD CMD6 can either check or set a function. Bitfields are used to indicate 342 * feature support when checking a function, and when setting a function an 343 * integer value is used to select it. 344 */ 345 enum sd_switch_arg { 346 SD_SWITCH_CHECK = 0U, 347 /*!< SD switch mode 0: check function */ 348 SD_SWITCH_SET = 1U, 349 /*!< SD switch mode 1: set function */ 350 }; 351 352 /** 353 * @brief SD switch group numbers 354 * 355 * SD CMD6 has multiple function groups it can check/set. These indicies are 356 * used to determine which group CMD6 will interact with. 357 */ 358 enum sd_group_num { 359 SD_GRP_TIMING_MODE = 0U, 360 /*!< access mode group*/ 361 SD_GRP_CMD_SYS_MODE = 1U, 362 /*!< command system group*/ 363 SD_GRP_DRIVER_STRENGTH_MODE = 2U, 364 /*!< driver strength group*/ 365 SD_GRP_CURRENT_LIMIT_MODE = 3U, 366 /*!< current limit group*/ 367 }; 368 369 /* Maximum data rate possible for SD high speed cards */ 370 enum hs_max_data_rate { 371 HS_MAX_DTR = 50000000, 372 }; 373 374 /** 375 * @brief SD bus speed support bit flags 376 * 377 * Bit flags indicating support for SD bus speeds. 378 * these bit flags are provided as a response to CMD6 by the card 379 */ 380 enum sd_bus_speed { 381 UHS_SDR12_BUS_SPEED = BIT(0), 382 HIGH_SPEED_BUS_SPEED = BIT(1), 383 UHS_SDR25_BUS_SPEED = BIT(1), 384 UHS_SDR50_BUS_SPEED = BIT(2), 385 UHS_SDR104_BUS_SPEED = BIT(3), 386 UHS_DDR50_BUS_SPEED = BIT(4), 387 }; 388 389 /** 390 * @brief SD timing mode function selection values. 391 * 392 * sent to the card via CMD6 to select a card speed, and used by SD host 393 * controller to identify timing of card. 394 */ 395 enum sd_timing_mode { 396 SD_TIMING_SDR12 = 0U, 397 /*!< Default mode & SDR12 */ 398 SD_TIMING_SDR25 = 1U, 399 /*!< High speed mode & SDR25 */ 400 SD_TIMING_SDR50 = 2U, 401 /*!< SDR50 mode*/ 402 SD_TIMING_SDR104 = 3U, 403 /*!< SDR104 mode */ 404 SD_TIMING_DDR50 = 4U, 405 /*!< DDR50 mode */ 406 }; 407 408 /** 409 * @brief SD host controller clock speed 410 * 411 * Controls the SD host controller clock speed on the SD bus. 412 */ 413 enum sdhc_clock_speed { 414 SDMMC_CLOCK_400KHZ = 400000U, 415 SD_CLOCK_25MHZ = 25000000U, 416 SD_CLOCK_50MHZ = 50000000U, 417 SD_CLOCK_100MHZ = 100000000U, 418 SD_CLOCK_208MHZ = 208000000U, 419 MMC_CLOCK_26MHZ = 26000000U, 420 MMC_CLOCK_52MHZ = 52000000U, 421 MMC_CLOCK_DDR52 = 52000000U, 422 MMC_CLOCK_HS200 = 200000000U, 423 MMC_CLOCK_HS400 = 200000000U, /* Same clock freq as HS200, just DDR */ 424 }; 425 426 /** 427 * @brief SD current setting values 428 * 429 * Used with CMD6 to inform the card what its maximum current draw is. 430 */ 431 enum sd_current_setting { 432 SD_SET_CURRENT_200MA = 0, 433 SD_SET_CURRENT_400MA = 1, 434 SD_SET_CURRENT_600MA = 2, 435 SD_SET_CURRENT_800MA = 3, 436 }; 437 438 /** 439 * @brief SD current support bitfield 440 * 441 * Used with CMD6 to determine the maximum current the card will draw. 442 */ 443 enum sd_current_limit { 444 SD_MAX_CURRENT_200MA = BIT(0), 445 /*!< default current limit */ 446 SD_MAX_CURRENT_400MA = BIT(1), 447 /*!< current limit to 400MA */ 448 SD_MAX_CURRENT_600MA = BIT(2), 449 /*!< current limit to 600MA */ 450 SD_MAX_CURRENT_800MA = BIT(3), 451 /*!< current limit to 800MA */ 452 }; 453 454 /** 455 * @brief SD driver types 456 * 457 * Used with CMD6 to determine the driver type the card should use. 458 */ 459 enum sd_driver_type { 460 SD_DRIVER_TYPE_B = 0x1, 461 SD_DRIVER_TYPE_A = 0x2, 462 SD_DRIVER_TYPE_C = 0x4, 463 SD_DRIVER_TYPE_D = 0x8, 464 }; 465 466 /** 467 * @brief SD switch drive type selection 468 * 469 * These values are used to select the preferred driver type for an SD card. 470 */ 471 enum sd_driver_strength { 472 SD_DRV_STRENGTH_TYPEB = 0U, 473 /*!< default driver strength*/ 474 SD_DRV_STRENGTH_TYPEA = 1U, 475 /*!< driver strength TYPE A */ 476 SD_DRV_STRENGTH_TYPEC = 2U, 477 /*!< driver strength TYPE C */ 478 SD_DRV_STRENGTH_TYPED = 3U, 479 /*!< driver strength TYPE D */ 480 }; 481 482 /** 483 * @brief SD switch capabilities 484 * 485 * records switch capabilities for SD card. These capabilities are set 486 * and queried via CMD6 487 */ 488 struct sd_switch_caps { 489 enum hs_max_data_rate hs_max_dtr; 490 enum sdhc_clock_speed uhs_max_dtr; 491 enum sd_bus_speed bus_speed; 492 enum sd_driver_type sd_drv_type; 493 enum sd_current_limit sd_current_limit; 494 }; 495 496 497 #define SD_PRODUCT_NAME_BYTES 5 498 499 /** 500 * @brief SD card identification register 501 * 502 * Layout of SD card identification register 503 */ 504 struct sd_cid { 505 uint8_t manufacturer; 506 /*!< Manufacturer ID [127:120] */ 507 uint16_t application; 508 /*!< OEM/Application ID [119:104] */ 509 uint8_t name[SD_PRODUCT_NAME_BYTES]; 510 /*!< Product name [103:64] */ 511 uint8_t version; 512 /*!< Product revision [63:56] */ 513 uint32_t ser_num; 514 /*!< Product serial number [55:24] */ 515 uint16_t date; 516 /*!< Manufacturing date [19:8] */ 517 }; 518 519 /** 520 * @brief SD card specific data register. 521 * 522 * Card specific data register. contains additional data about SD card. 523 */ 524 struct sd_csd { 525 uint8_t csd_structure; 526 /*!< CSD structure [127:126] */ 527 uint8_t read_time1; 528 /*!< Data read access-time-1 [119:112] */ 529 uint8_t read_time2; 530 /*!< Data read access-time-2 in clock cycles (NSAC*100) [111:104] */ 531 uint8_t xfer_rate; 532 /*!< Maximum data transfer rate [103:96] */ 533 uint16_t cmd_class; 534 /*!< Card command classes [95:84] */ 535 uint8_t read_blk_len; 536 /*!< Maximum read data block length [83:80] */ 537 uint16_t flags; 538 /*!< Flags in _sd_csd_flag */ 539 uint32_t device_size; 540 /*!< Device size [73:62] */ 541 uint8_t read_current_min; 542 /*!< Maximum read current at VDD min [61:59] */ 543 uint8_t read_current_max; 544 /*!< Maximum read current at VDD max [58:56] */ 545 uint8_t write_current_min; 546 /*!< Maximum write current at VDD min [55:53] */ 547 uint8_t write_current_max; 548 /*!< Maximum write current at VDD max [52:50] */ 549 uint8_t dev_size_mul; 550 /*!< Device size multiplier [49:47] */ 551 uint8_t erase_size; 552 /*!< Erase sector size [45:39] */ 553 uint8_t write_prtect_size; 554 /*!< Write protect group size [38:32] */ 555 uint8_t write_speed_factor; 556 /*!< Write speed factor [28:26] */ 557 uint8_t write_blk_len; 558 /*!< Maximum write data block length [25:22] */ 559 uint8_t file_fmt; 560 /*!< File format [11:10] */ 561 }; 562 563 /** 564 * @brief MMC Maximum Frequency 565 * 566 * Max freq in MMC csd 567 */ 568 enum mmc_csd_freq { 569 MMC_MAXFREQ_100KHZ = 0U << 0U, 570 MMC_MAXFREQ_1MHZ = 1U << 0U, 571 MMC_MAXFREQ_10MHZ = 2U << 0U, 572 MMC_MAXFREQ_100MHZ = 3U << 0U, 573 MMC_MAXFREQ_MULT_10 = 1U << 3U, 574 MMC_MAXFREQ_MULT_12 = 2U << 3U, 575 MMC_MAXFREQ_MULT_13 = 3U << 3U, 576 MMC_MAXFREQ_MULT_15 = 4U << 3U, 577 MMC_MAXFREQ_MULT_20 = 5U << 3U, 578 MMC_MAXFREQ_MULT_26 = 6U << 3U, 579 MMC_MAXFREQ_MULT_30 = 7U << 3U, 580 MMC_MAXFREQ_MULT_35 = 8U << 3U, 581 MMC_MAXFREQ_MULT_40 = 9U << 3U, 582 MMC_MAXFREQ_MULT_45 = 0xAU << 3U, 583 MMC_MAXFREQ_MULT_52 = 0xBU << 3U, 584 MMC_MAXFREQ_MULT_55 = 0xCU << 3U, 585 MMC_MAXFREQ_MULT_60 = 0xDU << 3U, 586 MMC_MAXFREQ_MULT_70 = 0xEU << 3U, 587 MMC_MAXFREQ_MULT_80 = 0xFU << 3u 588 }; 589 590 /** 591 * @brief MMC Timing Modes 592 * 593 * MMC Timing Mode, encoded in EXT_CSD 594 */ 595 enum mmc_timing_mode { 596 MMC_LEGACY_TIMING = 0U, 597 MMC_HS_TIMING = 1U, 598 MMC_HS200_TIMING = 2U, 599 MMC_HS400_TIMING = 3U 600 }; 601 602 /** 603 * @brief MMC Driver Strengths 604 * 605 * Encoded in EXT_CSD 606 */ 607 enum mmc_driver_strengths { 608 mmc_driv_type0 = 0U, 609 mmc_driv_type1 = 1U, 610 mmc_driv_type2 = 2U, 611 mmc_driv_type3 = 3U, 612 mmc_driv_type4 = 4U 613 }; 614 615 616 /** 617 * @brief MMC Device Type 618 * 619 * Encoded in EXT_CSD 620 */ 621 struct mmc_device_type { 622 bool MMC_HS400_DDR_1200MV; 623 bool MMC_HS400_DDR_1800MV; 624 bool MMC_HS200_SDR_1200MV; 625 bool MMC_HS200_SDR_1800MV; 626 bool MMC_HS_DDR_1200MV; 627 bool MMC_HS_DDR_1800MV; 628 bool MMC_HS_52_DV; 629 bool MMC_HS_26_DV; 630 }; 631 632 /** 633 * @brief CSD Revision 634 * 635 * Value of CSD rev in EXT_CSD 636 */ 637 enum mmc_ext_csd_rev { 638 MMC_5_1 = 8U, 639 MMC_5_0 = 7U, 640 MMC_4_5 = 6U, 641 MMC_4_4 = 5U, 642 MMC_4_3 = 3U, 643 MMC_4_2 = 2U, 644 MMC_4_1 = 1U, 645 MMC_4_0 = 0U 646 }; 647 648 /** 649 * @brief MMC extended card specific data register 650 * 651 * Extended card specific data register. 652 * Contains additional additional data about MMC card. 653 */ 654 struct mmc_ext_csd { 655 uint32_t sec_count; 656 /*!< Sector Count [215:212] >*/ 657 uint8_t bus_width; 658 /*!< Bus Width Mode [183] >*/ 659 enum mmc_timing_mode hs_timing; 660 /*!< High Speed Timing Mode [185] >*/ 661 struct mmc_device_type device_type; 662 /*!< Device Type [196] >*/ 663 enum mmc_ext_csd_rev rev; 664 /*!< Extended CSD Revision [192] >*/ 665 uint8_t power_class; 666 /*!< Selected power class [187]>*/ 667 uint8_t mmc_driver_strengths; 668 /*!< Driver strengths [197] >*/ 669 uint8_t pwr_class_200MHZ_VCCQ195; 670 /*!< Power class information for HS200 at VCC!=1.95V [237] >*/ 671 uint8_t pwr_class_HS400; 672 /*!< Power class information for HS400 [253] >*/ 673 uint32_t cache_size; 674 /*!< Size of eMMC cache [252:249]>*/ 675 }; 676 677 /** 678 * @brief SD card specific data flags 679 * 680 * flags used in decoding the SD card specific data register 681 */ 682 enum sd_csd_flag { 683 SD_CSD_READ_BLK_PARTIAL_FLAG = BIT(0), 684 /*!< Partial blocks for read allowed [79:79] */ 685 SD_CSD_WRITE_BLK_MISALIGN_FLAG = BIT(1), 686 /*!< Write block misalignment [78:78] */ 687 SD_CSD_READ_BLK_MISALIGN_FLAG = BIT(2), 688 /*!< Read block misalignment [77:77] */ 689 SD_CSD_DSR_IMPLEMENTED_FLAG = BIT(3), 690 /*!< DSR implemented [76:76] */ 691 SD_CSD_ERASE_BLK_EN_FLAG = BIT(4), 692 /*!< Erase single block enabled [46:46] */ 693 SD_CSD_WRITE_PROTECT_GRP_EN_FLAG = BIT(5), 694 /*!< Write protect group enabled [31:31] */ 695 SD_CSD_WRITE_BLK_PARTIAL_FLAG = BIT(6), 696 /*!< Partial blocks for write allowed [21:21] */ 697 SD_CSD_FILE_FMT_GRP_FLAG = BIT(7), 698 /*!< File format group [15:15] */ 699 SD_CSD_COPY_FLAG = BIT(8), 700 /*!< Copy flag [14:14] */ 701 SD_CSD_PERMANENT_WRITE_PROTECT_FLAG = BIT(9), 702 /*!< Permanent write protection [13:13] */ 703 SD_CSD_TMP_WRITE_PROTECT_FLAG = BIT(10), 704 /*!< Temporary write protection [12:12] */ 705 }; 706 707 /** 708 * @brief SD card configuration register 709 * 710 * Even more SD card data. 711 */ 712 struct sd_scr { 713 uint8_t scr_structure; 714 /*!< SCR Structure [63:60] */ 715 uint8_t sd_spec; 716 /*!< SD memory card specification version [59:56] */ 717 uint16_t flags; 718 /*!< SCR flags in _sd_scr_flag */ 719 uint8_t sd_sec; 720 /*!< Security specification supported [54:52] */ 721 uint8_t sd_width; 722 /*!< Data bus widths supported [51:48] */ 723 uint8_t sd_ext_sec; 724 /*!< Extended security support [46:43] */ 725 uint8_t cmd_support; 726 /*!< Command support bits [33:32] 33-support CMD23, 32-support cmd20*/ 727 uint32_t rsvd; 728 /*!< reserved for manufacturer usage [31:0] */ 729 }; 730 731 /** 732 * @brief SD card configuration register 733 * 734 * flags used in decoding the SD card configuration register 735 */ 736 enum sd_scr_flag { 737 SD_SCR_DATA_STATUS_AFTER_ERASE = BIT(0), 738 /*!< Data status after erases [55:55] */ 739 SD_SCR_SPEC3 = BIT(1), 740 /*!< Specification version 3.00 or higher [47:47]*/ 741 }; 742 743 /** 744 * @brief SD specification version 745 * 746 * SD spec version flags used in decoding the SD card configuration register 747 */ 748 enum sd_spec_version { 749 SD_SPEC_VER1_0 = BIT(0), 750 /*!< SD card version 1.0-1.01 */ 751 SD_SPEC_VER1_1 = BIT(1), 752 /*!< SD card version 1.10 */ 753 SD_SPEC_VER2_0 = BIT(2), 754 /*!< SD card version 2.00 */ 755 SD_SPEC_VER3_0 = BIT(3), 756 /*!< SD card version 3.0 */ 757 }; 758 759 760 #define SDMMC_DEFAULT_BLOCK_SIZE 512 761 #define MMC_EXT_CSD_BYTES 512 762 /** 763 * @brief SDIO function number 764 * 765 * SDIO function number used to select function when performing I/O on SDIO card 766 */ 767 enum sdio_func_num { 768 SDIO_FUNC_NUM_0 = 0, 769 SDIO_FUNC_NUM_1 = 1, 770 SDIO_FUNC_NUM_2 = 2, 771 SDIO_FUNC_NUM_3 = 3, 772 SDIO_FUNC_NUM_4 = 4, 773 SDIO_FUNC_NUM_5 = 5, 774 SDIO_FUNC_NUM_6 = 6, 775 SDIO_FUNC_NUM_7 = 7, 776 SDIO_FUNC_MEMORY = 8, 777 }; 778 779 /** 780 * @brief SDIO I/O direction 781 * 782 * SDIO I/O direction (read or write) 783 */ 784 enum sdio_io_dir { 785 SDIO_IO_READ = 0, 786 SDIO_IO_WRITE = 1, 787 }; 788 789 #define SDIO_CMD_ARG_RW_SHIFT 31 /*!< read/write flag shift */ 790 #define SDIO_CMD_ARG_FUNC_NUM_SHIFT 28 /*!< function number shift */ 791 #define SDIO_DIRECT_CMD_ARG_RAW_SHIFT 27 /*!< direct raw flag shift */ 792 #define SDIO_CMD_ARG_REG_ADDR_SHIFT 9 /*!< direct reg addr shift */ 793 #define SDIO_CMD_ARG_REG_ADDR_MASK 0x1FFFF /*!< direct reg addr mask */ 794 #define SDIO_DIRECT_CMD_DATA_MASK 0xFF /*!< data mask */ 795 796 #define SDIO_EXTEND_CMD_ARG_BLK_SHIFT 27 /*!< extended write block mode */ 797 #define SDIO_EXTEND_CMD_ARG_OP_CODE_SHIFT 26 /*!< op code (increment address) */ 798 799 /** 800 * @brief Card common control register definitions 801 * 802 * Card common control registers, present on all SDIO cards 803 */ 804 #define SDIO_CCCR_CCCR 0x00 /*!< SDIO CCCR revision register */ 805 #define SDIO_CCCR_CCCR_REV_MASK 0x0F 806 #define SDIO_CCCR_CCCR_REV_SHIFT 0x0 807 #define SDIO_CCCR_CCCR_REV_1_00 0x0 /*!< CCCR/FBR Version 1.00 */ 808 #define SDIO_CCCR_CCCR_REV_1_10 0x1 /*!< CCCR/FBR Version 1.10 */ 809 #define SDIO_CCCR_CCCR_REV_2_00 0x2 /*!< CCCR/FBR Version 2.00 */ 810 #define SDIO_CCCR_CCCR_REV_3_00 0x3 /*!< CCCR/FBR Version 3.00 */ 811 812 #define SDIO_CCCR_SD 0x01 /*!< SD spec version register */ 813 #define SDIO_CCCR_SD_SPEC_MASK 0x0F 814 #define SDIO_CCCR_SD_SPEC_SHIFT 0x0 815 816 #define SDIO_CCCR_IO_EN 0x02 /*!< SDIO IO Enable register */ 817 818 #define SDIO_CCCR_IO_RD 0x03 /*!< SDIO IO Ready register */ 819 820 #define SDIO_CCCR_INT_EN 0x04 /*!< SDIO Interrupt enable register */ 821 822 #define SDIO_CCCR_INT_P 0x05 /*!< SDIO Interrupt pending register */ 823 824 #define SDIO_CCCR_ABORT 0x06 /*!< SDIO IO abort register */ 825 826 #define SDIO_CCCR_BUS_IF 0x07 /*!< SDIO bus interface control register */ 827 #define SDIO_CCCR_BUS_IF_WIDTH_MASK 0x3 /*!< SDIO bus width setting mask */ 828 #define SDIO_CCCR_BUS_IF_WIDTH_1_BIT 0x00 /*!< 1 bit SDIO bus setting */ 829 #define SDIO_CCCR_BUS_IF_WIDTH_4_BIT 0x02 /*!< 4 bit SDIO bus setting */ 830 #define SDIO_CCCR_BUS_IF_WIDTH_8_BIT 0x03 /*!< 8 bit SDIO bus setting */ 831 832 #define SDIO_CCCR_CAPS 0x08 /*!< SDIO card capabilities */ 833 #define SDIO_CCCR_CAPS_SDC BIT(0) /*!< support CMD52 while data transfer */ 834 #define SDIO_CCCR_CAPS_SMB BIT(1) /*!< support multiple block transfer */ 835 #define SDIO_CCCR_CAPS_SRW BIT(2) /*!< support read wait control */ 836 #define SDIO_CCCR_CAPS_SBS BIT(3) /*!< support bus control */ 837 #define SDIO_CCCR_CAPS_S4MI BIT(4) /*!< support block gap interrupt */ 838 #define SDIO_CCCR_CAPS_E4MI BIT(5) /*!< enable block gap interrupt */ 839 #define SDIO_CCCR_CAPS_LSC BIT(6) /*!< low speed card */ 840 #define SDIO_CCCR_CAPS_BLS BIT(7) /*!< low speed card with 4 bit support */ 841 842 #define SDIO_CCCR_CIS 0x09 /*!< SDIO CIS tuples pointer */ 843 844 #define SDIO_CCCR_SPEED 0x13 /*!< SDIO bus speed select */ 845 #define SDIO_CCCR_SPEED_SHS BIT(0) /*!< high speed support */ 846 #define SDIO_CCCR_SPEED_MASK 0xE /*!< bus speed select mask*/ 847 #define SDIO_CCCR_SPEED_SHIFT 0x1 /*!< bus speed select shift */ 848 #define SDIO_CCCR_SPEED_SDR12 0x0 /*!< select SDR12 */ 849 #define SDIO_CCCR_SPEED_HS 0x1 /*!< select High speed mode */ 850 #define SDIO_CCCR_SPEED_SDR25 0x1 /*!< select SDR25 */ 851 #define SDIO_CCCR_SPEED_SDR50 0x2 /*!< select SDR50 */ 852 #define SDIO_CCCR_SPEED_SDR104 0x3 /*!< select SDR104 */ 853 #define SDIO_CCCR_SPEED_DDR50 0x4 /*!< select DDR50 */ 854 855 #define SDIO_CCCR_UHS 0x14 /*!< SDIO UHS support */ 856 #define SDIO_CCCR_UHS_SDR50 BIT(0) /*!< SDR50 support */ 857 #define SDIO_CCCR_UHS_SDR104 BIT(1) /*!< SDR104 support */ 858 #define SDIO_CCCR_UHS_DDR50 BIT(2) /*!< DDR50 support */ 859 860 #define SDIO_CCCR_DRIVE_STRENGTH 0x15 /*!< SDIO drive strength */ 861 #define SDIO_CCCR_DRIVE_STRENGTH_A BIT(0) /*!< drive type A */ 862 #define SDIO_CCCR_DRIVE_STRENGTH_C BIT(1) /*!< drive type C */ 863 #define SDIO_CCCR_DRIVE_STRENGTH_D BIT(2) /*!< drive type D */ 864 865 #define SDIO_FBR_BASE(n) ((n) * 0x100) /*!< Get function base register addr */ 866 867 #define SDIO_FBR_CIS 0x09 /*!< SDIO function base register CIS pointer */ 868 #define SDIO_FBR_CSA 0x0C /*!< SDIO function base register CSA pointer */ 869 #define SDIO_FBR_BLK_SIZE 0x10 /*!< SDIO function base register block size */ 870 871 872 #define SDIO_MAX_IO_NUMS 7 /*!< Maximum number of I/O functions for SDIO */ 873 874 #define SDIO_TPL_CODE_NULL 0x00 /*!< NULL CIS tuple code */ 875 #define SDIO_TPL_CODE_MANIFID 0x20 /*!< manufacturer ID CIS tuple code */ 876 #define SDIO_TPL_CODE_FUNCID 0x21 /*!< function ID CIS tuple code */ 877 #define SDIO_TPL_CODE_FUNCE 0x22 /*!< function extension CIS tuple code */ 878 #define SDIO_TPL_CODE_END 0xFF /*!< End CIS tuple code */ 879 880 /** 881 * @brief Card common control register flags 882 * 883 * flags to indicate capabilities supported by an SDIO card, read from the CCCR 884 * registers 885 */ 886 enum sdio_cccr_flags { 887 SDIO_SUPPORT_HS = BIT(0), 888 SDIO_SUPPORT_SDR50 = BIT(1), 889 SDIO_SUPPORT_SDR104 = BIT(2), 890 SDIO_SUPPORT_DDR50 = BIT(3), 891 SDIO_SUPPORT_4BIT_LS_BUS = BIT(4), 892 SDIO_SUPPORT_MULTIBLOCK = BIT(5), 893 }; 894 895 /** 896 * @brief SDIO common CIS tuple properties 897 * 898 * CIS tuple properties. Note that additional properties exist for 899 * functions 1-7, but we do not read this data as the stack does not utilize it. 900 */ 901 struct sdio_cis { 902 /* Manufacturer ID string tuple */ 903 uint16_t manf_id; /*!< manufacturer ID */ 904 uint16_t manf_code; /*!< manufacturer code */ 905 /* Function identification tuple */ 906 uint8_t func_id; /*!< sdio device class function id */ 907 /* Function extension table */ 908 uint16_t max_blk_size; /*!< Max transfer block size */ 909 uint8_t max_speed; /*!< Max transfer speed */ 910 uint16_t rdy_timeout; /*!< I/O ready timeout */ 911 }; 912 913 #ifdef __cplusplus 914 } 915 #endif 916 917 #endif /* ZEPHYR_SUBSYS_SD_SPEC_H_ */ 918
