Searched refs:SDMMC_SEL (Results 1 – 9 of 9) sorted by relevance
/Zephyr-Core-3.6.0/include/zephyr/dt-bindings/clock/ |
D | stm32f427_clock.h | 19 #define SDMMC_SEL(val) STM32_CLOCK(val, 1, 28, DCKCFGR_REG) macro
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D | stm32l4_clock.h | 101 #define SDMMC_SEL(val) STM32_CLOCK(val, 1, 14, CCIPR2_REG) macro
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D | stm32h7_clock.h | 103 #define SDMMC_SEL(val) STM32_CLOCK(val, 1, 16, D1CCIPR_REG) macro
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D | stm32u5_clock.h | 109 #define SDMMC_SEL(val) STM32_CLOCK(val, 1, 14, CCIPR2_REG) macro
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/Zephyr-Core-3.6.0/dts/arm/st/f4/ |
D | stm32f469.dtsi | 15 <&rcc STM32_SRC_SYSCLK SDMMC_SEL(1)>;
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/Zephyr-Core-3.6.0/boards/arm/stm32h747i_disco/ |
D | stm32h747i_disco_m7.dts | 216 <&rcc STM32_SRC_PLL2_R SDMMC_SEL(1)>;
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/Zephyr-Core-3.6.0/dts/arm/st/u5/ |
D | stm32u5.dtsi | 739 <&rcc STM32_SRC_HSI48 SDMMC_SEL(0)>; 749 <&rcc STM32_SRC_HSI48 SDMMC_SEL(0)>;
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/Zephyr-Core-3.6.0/dts/arm/st/h7/ |
D | stm32h7.dtsi | 997 <&rcc STM32_SRC_PLL1_Q SDMMC_SEL(0)>; 1007 <&rcc STM32_SRC_PLL1_Q SDMMC_SEL(0)>;
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/Zephyr-Core-3.6.0/dts/arm/st/l5/ |
D | stm32l5.dtsi | 400 <&rcc STM32_SRC_HSI48 SDMMC_SEL(0)>;
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