Home
last modified time | relevance | path

Searched refs:RCU_CFG0_APB2PSC_MSK (Results 1 – 9 of 9) sorted by relevance

/Zephyr-Core-3.6.0/soc/arm/gd_gd32/gd32l23x/
Dgd32_regs.h22 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS) macro
/Zephyr-Core-3.6.0/soc/arm/gd_gd32/gd32e50x/
Dgd32_regs.h23 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS) macro
/Zephyr-Core-3.6.0/soc/arm/gd_gd32/gd32f403/
Dgd32_regs.h23 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS) macro
/Zephyr-Core-3.6.0/soc/arm/gd_gd32/gd32f3x0/
Dgd32_regs.h23 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS) macro
/Zephyr-Core-3.6.0/soc/arm/gd_gd32/gd32e10x/
Dgd32_regs.h23 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS) macro
/Zephyr-Core-3.6.0/soc/riscv/gd_gd32/gd32vf103/
Dgd32_regs.h23 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS) macro
/Zephyr-Core-3.6.0/soc/arm/gd_gd32/gd32a50x/
Dgd32_regs.h24 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS) macro
/Zephyr-Core-3.6.0/soc/arm/gd_gd32/gd32f4xx/
Dgd32_regs.h26 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS) macro
/Zephyr-Core-3.6.0/drivers/clock_control/
Dclock_control_gd32.c126 psc = (cfg & RCU_CFG0_APB2PSC_MSK) >> RCU_CFG0_APB2PSC_POS; in clock_control_gd32_get_rate()