1 /*
2 * Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT renesas_ra_gpio
8
9 #include <errno.h>
10 #include <string.h>
11
12 #include <zephyr/kernel.h>
13 #include <zephyr/device.h>
14 #include <zephyr/init.h>
15 #include <zephyr/irq.h>
16 #include <zephyr/drivers/gpio.h>
17 #include <zephyr/drivers/gpio/gpio_utils.h>
18 #include <zephyr/drivers/interrupt_controller/intc_ra_icu.h>
19 #include <zephyr/drivers/pinctrl.h>
20
21 enum {
22 PCNTR1_OFFSET = 0x0,
23 PCNTR2_OFFSET = 0x4,
24 PCNTR3_OFFSET = 0x8,
25 PCNTR4_OFFSET = 0xc
26 };
27
28 enum {
29 PCNTR1_PDR0_OFFSET = 0,
30 PCNTR1_PODR0_OFFSET = 16,
31 };
32
33 enum {
34 PCNTR2_PIDR0_OFFSET = 0,
35 PCNTR2_EIDR0_OFFSET = 16,
36 };
37
38 enum {
39 PCNTR3_POSR0_OFFSET = 0,
40 PCNTR3_PORR0_OFFSET = 16,
41 };
42
43 enum {
44 PCNTR4_EOSR0_OFFSET = 0,
45 PCNTR4_EORR0_OFFSET = 16,
46 };
47
48 struct gpio_ra_irq_info {
49 const uint8_t *const pins;
50 size_t num;
51 int port_irq;
52 int irq;
53 uint32_t priority;
54 uint32_t flags;
55 ra_isr_handler isr;
56 };
57
58 struct gpio_ra_pin_irq_info {
59 const struct gpio_ra_irq_info *info;
60 uint8_t pin;
61 };
62
63 struct gpio_ra_config {
64 struct gpio_driver_config common;
65 mem_addr_t regs;
66 struct gpio_ra_irq_info *irq_info;
67 uint32_t irq_info_size;
68 uint16_t port;
69 };
70
71 struct gpio_ra_data {
72 struct gpio_driver_data common;
73 struct gpio_ra_pin_irq_info port_irq_info[16];
74 sys_slist_t callbacks;
75 };
76
gpio_ra_irq_info_event(const struct gpio_ra_irq_info * info)77 static inline uint32_t gpio_ra_irq_info_event(const struct gpio_ra_irq_info *info)
78 {
79 return ((info->flags & RA_ICU_FLAG_EVENT_MASK) >> RA_ICU_FLAG_EVENT_OFFSET);
80 }
81
gpio_ra_isr(const struct device * dev,uint32_t port_irq)82 static void gpio_ra_isr(const struct device *dev, uint32_t port_irq)
83 {
84 struct gpio_ra_data *data = dev->data;
85 const struct gpio_ra_pin_irq_info *pin_irq = &data->port_irq_info[port_irq];
86 const int irq = ra_icu_query_exists_irq(gpio_ra_irq_info_event(pin_irq->info));
87
88 if (irq >= 0) {
89 gpio_fire_callbacks(&data->callbacks, dev, BIT(pin_irq->pin));
90 ra_icu_clear_int_flag(irq);
91 }
92 }
93
query_irq_info(const struct device * dev,uint32_t pin)94 static const struct gpio_ra_irq_info *query_irq_info(const struct device *dev, uint32_t pin)
95 {
96 const struct gpio_ra_config *config = dev->config;
97
98 for (int i = 0; i < config->irq_info_size; i++) {
99 const struct gpio_ra_irq_info *info = &config->irq_info[i];
100
101 for (int j = 0; j < info->num; j++) {
102 if (info->pins[j] == pin) {
103 return info;
104 }
105 }
106 }
107
108 return NULL;
109 }
110
reg_read(const struct device * dev,size_t offset)111 static inline uint32_t reg_read(const struct device *dev, size_t offset)
112 {
113 const struct gpio_ra_config *config = dev->config;
114
115 return sys_read32(config->regs + offset);
116 }
117
reg_write(const struct device * dev,size_t offset,uint32_t value)118 static inline void reg_write(const struct device *dev, size_t offset, uint32_t value)
119 {
120 const struct gpio_ra_config *config = dev->config;
121
122 sys_write32(value, config->regs + offset);
123 }
124
port_read(const struct device * dev)125 static inline uint32_t port_read(const struct device *dev)
126 {
127 return reg_read(dev, PCNTR2_OFFSET) & UINT16_MAX;
128 }
129
port_write(const struct device * dev,uint16_t value,uint16_t mask)130 static int port_write(const struct device *dev, uint16_t value, uint16_t mask)
131 {
132 const uint16_t set = value & mask;
133 const uint16_t clr = (~value) & mask;
134
135 reg_write(dev, PCNTR3_OFFSET, (clr << PCNTR3_PORR0_OFFSET) | set << PCNTR3_POSR0_OFFSET);
136
137 return 0;
138 }
139
gpio_ra_pin_configure(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)140 static int gpio_ra_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
141 {
142 const enum gpio_int_mode mode =
143 flags & (GPIO_INT_EDGE | GPIO_INT_DISABLE | GPIO_INT_ENABLE);
144 const enum gpio_int_trig trig = flags & (GPIO_INT_LOW_0 | GPIO_INT_HIGH_1);
145 const struct gpio_ra_config *config = dev->config;
146 struct gpio_ra_data *data = dev->data;
147 struct pinctrl_ra_pin pincfg = {0};
148
149 if ((flags & GPIO_OUTPUT) && (flags & GPIO_INPUT)) {
150 /* Pin cannot be configured as input and output */
151 return -ENOTSUP;
152 } else if (!(flags & (GPIO_INPUT | GPIO_OUTPUT))) {
153 /* Pin has to be configured as input or output */
154 return -ENOTSUP;
155 }
156
157 if (flags & GPIO_OUTPUT) {
158 pincfg.config |= BIT(PmnPFS_PDR_POS);
159 }
160
161 if (flags & GPIO_PULL_UP) {
162 pincfg.config |= BIT(PmnPFS_PCR_POS);
163 }
164
165 if ((flags & GPIO_SINGLE_ENDED) && (flags & GPIO_LINE_OPEN_DRAIN)) {
166 pincfg.config |= BIT(PmnPFS_NCODR_POS);
167 }
168
169 if (flags & GPIO_INT_ENABLE) {
170 pincfg.config |= BIT(PmnPFS_ISEL_POS);
171 }
172
173 pincfg.config &= ~BIT(PmnPFS_PMR_POS);
174
175 pincfg.pin = pin;
176 pincfg.port = config->port;
177
178 if (flags & GPIO_INT_ENABLE) {
179 const struct gpio_ra_irq_info *irq_info;
180 uint32_t intcfg;
181 int irqn;
182
183 if (mode == GPIO_INT_MODE_LEVEL) {
184 if (trig != GPIO_INT_TRIG_LOW) {
185 return -ENOTSUP;
186 }
187
188 intcfg = ICU_LOW_LEVEL;
189 } else if (mode == GPIO_INT_MODE_EDGE) {
190 switch (trig) {
191 case GPIO_INT_TRIG_LOW:
192 intcfg = ICU_FALLING;
193 break;
194 case GPIO_INT_TRIG_HIGH:
195 intcfg = ICU_RISING;
196 break;
197 case GPIO_INT_TRIG_BOTH:
198 intcfg = ICU_BOTH_EDGE;
199 break;
200 default:
201 return -ENOTSUP;
202 }
203 } else {
204 return -ENOTSUP;
205 }
206
207 irq_info = query_irq_info(dev, pin);
208 if (irq_info == NULL) {
209 return -EINVAL;
210 }
211
212 irqn = ra_icu_irq_connect_dynamic(
213 irq_info->irq, irq_info->priority, irq_info->isr, dev,
214 (intcfg << RA_ICU_FLAG_INTCFG_OFFSET) | irq_info->flags);
215 if (irqn < 0) {
216 return irqn;
217 }
218
219 data->port_irq_info[irq_info->port_irq].pin = pin;
220 data->port_irq_info[irq_info->port_irq].info = irq_info;
221
222 irq_enable(irqn);
223 }
224
225 return pinctrl_configure_pins(&pincfg, 1, PINCTRL_REG_NONE);
226 }
227
228 #ifdef CONFIG_GPIO_GET_CONFIG
gpio_ra_pin_get_config(const struct device * dev,gpio_pin_t pin,gpio_flags_t * flags)229 static int gpio_ra_pin_get_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t *flags)
230 {
231 const struct gpio_ra_config *config = dev->config;
232 const struct gpio_ra_irq_info *irq_info;
233 struct pinctrl_ra_pin pincfg;
234 ra_isr_handler cb;
235 const void *cbarg;
236 uint32_t intcfg;
237 int irqn;
238 int err;
239
240 memset(flags, 0, sizeof(gpio_flags_t));
241
242 err = pinctrl_ra_query_config(config->port, pin, &pincfg);
243 if (err < 0) {
244 return err;
245 }
246
247 if (pincfg.config & BIT(PmnPFS_PDR_POS)) {
248 *flags |= GPIO_OUTPUT;
249 } else {
250 *flags |= GPIO_INPUT;
251 }
252
253 if (pincfg.config & BIT(PmnPFS_ISEL_POS)) {
254 *flags |= GPIO_INT_ENABLE;
255 }
256
257 if (pincfg.config & BIT(PmnPFS_PCR_POS)) {
258 *flags |= GPIO_PULL_UP;
259 }
260
261 irq_info = query_irq_info(dev, pin);
262 if (irq_info == NULL) {
263 return 0;
264 }
265
266 irqn = ra_icu_query_exists_irq(gpio_ra_irq_info_event(irq_info));
267 if (irqn < 0) {
268 return 0;
269 }
270
271 ra_icu_query_irq_config(irqn, &intcfg, &cb, &cbarg);
272
273 if (cbarg != dev) {
274 return 0;
275 }
276
277 if (intcfg == ICU_FALLING) {
278 *flags |= GPIO_INT_TRIG_LOW;
279 *flags |= GPIO_INT_MODE_EDGE;
280 } else if (intcfg == ICU_RISING) {
281 *flags |= GPIO_INT_TRIG_HIGH;
282 *flags |= GPIO_INT_MODE_EDGE;
283 } else if (intcfg == ICU_BOTH_EDGE) {
284 *flags |= GPIO_INT_TRIG_BOTH;
285 *flags |= GPIO_INT_MODE_EDGE;
286 } else if (intcfg == ICU_LOW_LEVEL) {
287 *flags |= GPIO_INT_TRIG_LOW;
288 *flags |= GPIO_INT_MODE_LEVEL;
289 }
290
291 return 0;
292 }
293 #endif
294
gpio_ra_port_get_raw(const struct device * dev,gpio_port_value_t * value)295 static int gpio_ra_port_get_raw(const struct device *dev, gpio_port_value_t *value)
296 {
297 *value = port_read(dev);
298
299 return 0;
300 }
301
gpio_ra_port_set_masked_raw(const struct device * dev,gpio_port_pins_t mask,gpio_port_value_t value)302 static int gpio_ra_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
303 gpio_port_value_t value)
304 {
305 uint16_t port_val;
306
307 port_val = port_read(dev);
308 port_val = (port_val & ~mask) | (value & mask);
309 return port_write(dev, port_val, UINT16_MAX);
310 }
311
gpio_ra_port_set_bits_raw(const struct device * dev,gpio_port_pins_t pins)312 static int gpio_ra_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
313 {
314 uint16_t port_val;
315
316 port_val = port_read(dev);
317 port_val |= pins;
318 return port_write(dev, port_val, UINT16_MAX);
319 }
320
gpio_ra_port_clear_bits_raw(const struct device * dev,gpio_port_pins_t pins)321 static int gpio_ra_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
322 {
323 uint16_t port_val;
324
325 port_val = port_read(dev);
326 port_val &= ~pins;
327 return port_write(dev, port_val, UINT16_MAX);
328 }
329
gpio_ra_port_toggle_bits(const struct device * dev,gpio_port_pins_t pins)330 static int gpio_ra_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
331 {
332 uint16_t port_val;
333
334 port_val = port_read(dev);
335 port_val ^= pins;
336 return port_write(dev, port_val, UINT16_MAX);
337 }
338
gpio_ra_manage_callback(const struct device * dev,struct gpio_callback * callback,bool set)339 static int gpio_ra_manage_callback(const struct device *dev, struct gpio_callback *callback,
340 bool set)
341 {
342 struct gpio_ra_data *data = dev->data;
343
344 return gpio_manage_callback(&data->callbacks, callback, set);
345 }
346
gpio_ra_pin_interrupt_configure(const struct device * dev,gpio_pin_t pin,enum gpio_int_mode mode,enum gpio_int_trig trig)347 static int gpio_ra_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
348 enum gpio_int_mode mode, enum gpio_int_trig trig)
349 {
350 gpio_flags_t pincfg;
351 int err;
352
353 err = gpio_ra_pin_get_config(dev, pin, &pincfg);
354 if (err < 0) {
355 return err;
356 }
357
358 return gpio_ra_pin_configure(dev, pin, pincfg | mode | trig);
359 }
360
361 static const struct gpio_driver_api gpio_ra_driver_api = {
362 .pin_configure = gpio_ra_pin_configure,
363 #ifdef CONFIG_GPIO_GET_CONFIG
364 .pin_get_config = gpio_ra_pin_get_config,
365 #endif
366 .port_get_raw = gpio_ra_port_get_raw,
367 .port_set_masked_raw = gpio_ra_port_set_masked_raw,
368 .port_set_bits_raw = gpio_ra_port_set_bits_raw,
369 .port_clear_bits_raw = gpio_ra_port_clear_bits_raw,
370 .port_toggle_bits = gpio_ra_port_toggle_bits,
371 .pin_interrupt_configure = gpio_ra_pin_interrupt_configure,
372 .manage_callback = gpio_ra_manage_callback,
373 };
374
375 #define RA_NUM_PORT_IRQ0 0
376 #define RA_NUM_PORT_IRQ1 1
377 #define RA_NUM_PORT_IRQ2 2
378 #define RA_NUM_PORT_IRQ3 3
379 #define RA_NUM_PORT_IRQ4 4
380 #define RA_NUM_PORT_IRQ5 5
381 #define RA_NUM_PORT_IRQ6 6
382 #define RA_NUM_PORT_IRQ7 7
383 #define RA_NUM_PORT_IRQ8 8
384 #define RA_NUM_PORT_IRQ9 9
385 #define RA_NUM_PORT_IRQ10 10
386 #define RA_NUM_PORT_IRQ11 11
387 #define RA_NUM_PORT_IRQ12 12
388 #define RA_NUM_PORT_IRQ13 13
389 #define RA_NUM_PORT_IRQ14 14
390 #define RA_NUM_PORT_IRQ15 15
391
392 #define GPIO_RA_DECL_PINS(n, p, i) \
393 const uint8_t _CONCAT(n, ___pins##i[]) = {DT_FOREACH_PROP_ELEM_SEP( \
394 n, _CONCAT(DT_STRING_TOKEN_BY_IDX(n, p, i), _pins), DT_PROP_BY_IDX, (,))};
395
396 #define GPIO_RA_IRQ_INFO(n, p, i) \
397 { \
398 .port_irq = _CONCAT(RA_NUM_, DT_STRING_UPPER_TOKEN_BY_IDX(n, p, i)), \
399 .irq = DT_IRQ_BY_IDX(n, i, irq), \
400 .flags = DT_IRQ_BY_IDX(n, i, flags), \
401 .priority = DT_IRQ_BY_IDX(n, i, priority), \
402 .pins = _CONCAT(n, ___pins##i), \
403 .num = ARRAY_SIZE(_CONCAT(n, ___pins##i)), \
404 .isr = _CONCAT(n, _CONCAT(gpio_ra_isr_, DT_STRING_TOKEN_BY_IDX(n, p, i))), \
405 },
406
407 #define GPIO_RA_ISR_DECL(n, p, i) \
408 static void _CONCAT(n, _CONCAT(gpio_ra_isr_, DT_STRING_TOKEN_BY_IDX(n, p, i)))( \
409 const void *arg) \
410 { \
411 gpio_ra_isr((const struct device *)arg, \
412 _CONCAT(RA_NUM_, DT_STRING_UPPER_TOKEN_BY_IDX(n, p, i))); \
413 }
414
415 #define GPIO_RA_INIT(idx) \
416 static struct gpio_ra_data gpio_ra_data_##idx = {}; \
417 DT_INST_FOREACH_PROP_ELEM(idx, interrupt_names, GPIO_RA_DECL_PINS); \
418 DT_INST_FOREACH_PROP_ELEM(idx, interrupt_names, GPIO_RA_ISR_DECL); \
419 struct gpio_ra_irq_info gpio_ra_irq_info_##idx[] = { \
420 DT_INST_FOREACH_PROP_ELEM(idx, interrupt_names, GPIO_RA_IRQ_INFO)}; \
421 static struct gpio_ra_config gpio_ra_config_##idx = { \
422 .common = { \
423 .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx), \
424 }, \
425 .regs = DT_INST_REG_ADDR(idx), \
426 .port = (DT_INST_REG_ADDR(idx) - DT_REG_ADDR(DT_NODELABEL(ioport0))) / \
427 DT_INST_REG_SIZE(idx), \
428 .irq_info = gpio_ra_irq_info_##idx, \
429 .irq_info_size = ARRAY_SIZE(gpio_ra_irq_info_##idx), \
430 }; \
431 \
432 DEVICE_DT_INST_DEFINE(idx, NULL, NULL, &gpio_ra_data_##idx, &gpio_ra_config_##idx, \
433 PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, &gpio_ra_driver_api);
434
435 DT_INST_FOREACH_STATUS_OKAY(GPIO_RA_INIT)
436
