1 /*
2 * Copyright (c) 2023 Synopsys
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT snps_emsdp_pinctrl
8
9 #include <zephyr/arch/cpu.h>
10 #include <zephyr/devicetree.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <zephyr/dt-bindings/pinctrl/emsdp-pinctrl.h>
13
14 /**
15 * Mux Control Register Index
16 */
17 #define PMOD_MUX_CTRL 0 /*!< 32-bits, offset 0x0 */
18 #define ARDUINO_MUX_CTRL 4 /*!< 32-bits, offset 0x4 */
19
20 #define EMSDP_CREG_BASE DT_INST_REG_ADDR(0)
21 #define EMSDP_CREG_PMOD_MUX_OFFSET (0x0030)
22
23 #define MUX_SEL0_OFFSET (0)
24 #define MUX_SEL1_OFFSET (4)
25 #define MUX_SEL2_OFFSET (8)
26 #define MUX_SEL3_OFFSET (12)
27 #define MUX_SEL4_OFFSET (16)
28 #define MUX_SEL5_OFFSET (20)
29 #define MUX_SEL6_OFFSET (24)
30 #define MUX_SEL7_OFFSET (28)
31
32 #define MUX_SEL0_MASK (0xf << MUX_SEL0_OFFSET)
33 #define MUX_SEL1_MASK (0xf << MUX_SEL1_OFFSET)
34 #define MUX_SEL2_MASK (0xf << MUX_SEL2_OFFSET)
35 #define MUX_SEL3_MASK (0xf << MUX_SEL3_OFFSET)
36 #define MUX_SEL4_MASK (0xf << MUX_SEL4_OFFSET)
37 #define MUX_SEL5_MASK (0xf << MUX_SEL5_OFFSET)
38 #define MUX_SEL6_MASK (0xf << MUX_SEL6_OFFSET)
39 #define MUX_SEL7_MASK (0xf << MUX_SEL7_OFFSET)
40
41 /**
42 * PMOD A Multiplexor
43 */
44 #define PM_A_CFG0_GPIO ((0) << MUX_SEL0_OFFSET)
45 #define PM_A_CFG0_I2C ((1) << MUX_SEL0_OFFSET) /* io_i2c_mst2 */
46 #define PM_A_CFG0_SPI ((2) << MUX_SEL0_OFFSET) /* io_spi_mst1, cs_0 */
47 #define PM_A_CFG0_UART1a ((3) << MUX_SEL0_OFFSET) /* io_uart1 */
48 #define PM_A_CFG0_UART1b ((4) << MUX_SEL0_OFFSET) /* io_uart1 */
49 #define PM_A_CFG0_PWM1 ((5) << MUX_SEL0_OFFSET)
50 #define PM_A_CFG0_PWM2 ((6) << MUX_SEL0_OFFSET)
51
52 #define PM_A_CFG1_GPIO ((0) << MUX_SEL1_OFFSET)
53
54 /**
55 * PMOD B Multiplexor
56 */
57 #define PM_B_CFG0_GPIO ((0) << MUX_SEL2_OFFSET)
58 #define PM_B_CFG0_I2C ((1) << MUX_SEL2_OFFSET) /* io_i2c_mst2 */
59 #define PM_B_CFG0_SPI ((2) << MUX_SEL2_OFFSET) /* io_spi_mst1, cs_1 */
60 #define PM_B_CFG0_UART2a ((3) << MUX_SEL2_OFFSET) /* io_uart2 */
61 #define PM_B_CFG0_UART2b ((4) << MUX_SEL2_OFFSET) /* io_uart2 */
62 #define PM_B_CFG0_PWM1 ((5) << MUX_SEL2_OFFSET)
63 #define PM_B_CFG0_PWM2 ((6) << MUX_SEL2_OFFSET)
64
65 #define PM_B_CFG1_GPIO ((0) << MUX_SEL3_OFFSET)
66
67 /**
68 * PMOD C Multiplexor
69 */
70 #define PM_C_CFG0_GPIO ((0) << MUX_SEL4_OFFSET)
71 #define PM_C_CFG0_I2C ((1) << MUX_SEL4_OFFSET) /* io_i2c_mst2 */
72 #define PM_C_CFG0_SPI ((2) << MUX_SEL4_OFFSET) /* io_spi_mst1, cs_2 */
73 #define PM_C_CFG0_UART3a ((3) << MUX_SEL4_OFFSET) /* io_uart3 */
74 #define PM_C_CFG0_UART3b ((4) << MUX_SEL4_OFFSET) /* io_uart3 */
75 #define PM_C_CFG0_PWM1 ((5) << MUX_SEL4_OFFSET)
76 #define PM_C_CFG0_PWM2 ((6) << MUX_SEL4_OFFSET)
77
78 #define PM_C_CFG1_GPIO ((0) << MUX_SEL5_OFFSET)
79
80 /**
81 * Arduino Multiplexor
82 */
83 #define ARDUINO_CFG0_GPIO ((0) << MUX_SEL0_OFFSET)
84 #define ARDUINO_CFG0_UART ((1) << MUX_SEL0_OFFSET) /* io_uart0 */
85
86 #define ARDUINO_CFG1_GPIO ((0) << MUX_SEL1_OFFSET)
87 #define ARDUINO_CFG1_PWM ((1) << MUX_SEL1_OFFSET)
88
89 #define ARDUINO_CFG2_GPIO ((0) << MUX_SEL2_OFFSET)
90 #define ARDUINO_CFG2_PWM ((1) << MUX_SEL2_OFFSET)
91
92 #define ARDUINO_CFG3_GPIO ((0) << MUX_SEL3_OFFSET)
93 #define ARDUINO_CFG3_PWM ((1) << MUX_SEL3_OFFSET)
94
95 #define ARDUINO_CFG4_GPIO ((0) << MUX_SEL4_OFFSET)
96 #define ARDUINO_CFG4_PWM ((1) << MUX_SEL4_OFFSET)
97
98 #define ARDUINO_CFG5_GPIO ((0) << MUX_SEL5_OFFSET)
99 #define ARDUINO_CFG5_SPI ((1) << MUX_SEL5_OFFSET) /* io_spi_mst0, cs_0 */
100 #define ARDUINO_CFG5_PWM1 ((2) << MUX_SEL5_OFFSET)
101 #define ARDUINO_CFG5_PWM2 ((3) << MUX_SEL5_OFFSET)
102 #define ARDUINO_CFG5_PWM3 ((4) << MUX_SEL5_OFFSET)
103
104 #define ARDUINO_CFG6_GPIO ((0) << MUX_SEL6_OFFSET)
105 #define ARDUINO_CFG6_I2C ((1) << MUX_SEL6_OFFSET) /* io_i2c_mst1 */
106
pinctrl_emsdp_set(uint32_t pin,uint32_t type)107 static int pinctrl_emsdp_set(uint32_t pin, uint32_t type)
108 {
109 const uint32_t mux_regs = (EMSDP_CREG_BASE + EMSDP_CREG_PMOD_MUX_OFFSET);
110 uint32_t reg;
111
112 if (pin == UNMUXED_PIN) {
113 return 0;
114 }
115
116 if (pin <= PMOD_C) {
117 reg = sys_read32(mux_regs + PMOD_MUX_CTRL);
118 } else {
119 reg = sys_read32(mux_regs + ARDUINO_MUX_CTRL);
120 }
121
122 switch (pin) {
123 case PMOD_A:
124 reg &= ~(MUX_SEL0_MASK);
125 switch (type) {
126 case PMOD_GPIO:
127 reg |= PM_A_CFG0_GPIO;
128 break;
129 case PMOD_UARTA:
130 reg |= PM_A_CFG0_UART1a;
131 break;
132 case PMOD_UARTB:
133 reg |= PM_A_CFG0_UART1b;
134 break;
135 case PMOD_SPI:
136 reg |= PM_A_CFG0_SPI;
137 break;
138 case PMOD_I2C:
139 reg |= PM_A_CFG0_I2C;
140 break;
141 case PMOD_PWM_MODE1:
142 reg |= PM_A_CFG0_PWM1;
143 break;
144 case PMOD_PWM_MODE2:
145 reg |= PM_A_CFG0_PWM2;
146 break;
147 default:
148 break;
149 }
150 break;
151 case PMOD_B:
152 reg &= ~(MUX_SEL2_MASK);
153 switch (type) {
154 case PMOD_GPIO:
155 reg |= PM_B_CFG0_GPIO;
156 break;
157 case PMOD_UARTA:
158 reg |= PM_B_CFG0_UART2a;
159 break;
160 case PMOD_UARTB:
161 reg |= PM_A_CFG0_UART1b;
162 break;
163 case PMOD_SPI:
164 reg |= PM_B_CFG0_SPI;
165 break;
166 case PMOD_I2C:
167 reg |= PM_B_CFG0_I2C;
168 break;
169 case PMOD_PWM_MODE1:
170 reg |= PM_B_CFG0_PWM1;
171 break;
172 case PMOD_PWM_MODE2:
173 reg |= PM_B_CFG0_PWM2;
174 break;
175 default:
176 break;
177 }
178 break;
179 case PMOD_C:
180 reg &= ~(MUX_SEL4_MASK);
181 switch (type) {
182 case PMOD_GPIO:
183 reg |= PM_C_CFG0_GPIO;
184 break;
185 case PMOD_UARTA:
186 reg |= PM_C_CFG0_UART3a;
187 break;
188 case PMOD_UARTB:
189 reg |= PM_C_CFG0_UART3b;
190 break;
191 case PMOD_SPI:
192 reg |= PM_C_CFG0_SPI;
193 break;
194 case PMOD_I2C:
195 reg |= PM_C_CFG0_I2C;
196 break;
197 case PMOD_PWM_MODE1:
198 reg |= PM_C_CFG0_PWM1;
199 break;
200 case PMOD_PWM_MODE2:
201 reg |= PM_C_CFG0_PWM2;
202 break;
203 default:
204 break;
205 }
206 break;
207 case ARDUINO_PIN_0:
208 case ARDUINO_PIN_1:
209 reg &= ~MUX_SEL0_MASK;
210 if (type == ARDUINO_GPIO) {
211 reg |= ARDUINO_CFG0_GPIO;
212 } else if (type == ARDUINO_UART) {
213 reg |= ARDUINO_CFG0_UART;
214 }
215 break;
216 case ARDUINO_PIN_2:
217 case ARDUINO_PIN_3:
218 reg &= ~MUX_SEL1_MASK;
219 if (type == ARDUINO_GPIO) {
220 reg |= ARDUINO_CFG1_GPIO;
221 } else if (type == ARDUINO_PWM) {
222 reg |= ARDUINO_CFG1_PWM;
223 }
224 break;
225 case ARDUINO_PIN_4:
226 case ARDUINO_PIN_5:
227 reg &= ~MUX_SEL2_MASK;
228 if (type == ARDUINO_GPIO) {
229 reg |= ARDUINO_CFG2_GPIO;
230 } else if (type == ARDUINO_PWM) {
231 reg |= ARDUINO_CFG2_PWM;
232 }
233 break;
234 case ARDUINO_PIN_6:
235 case ARDUINO_PIN_7:
236 reg &= ~MUX_SEL3_MASK;
237 if (type == ARDUINO_GPIO) {
238 reg |= ARDUINO_CFG3_GPIO;
239 } else if (type == ARDUINO_PWM) {
240 reg |= ARDUINO_CFG3_PWM;
241 }
242 break;
243 case ARDUINO_PIN_8:
244 case ARDUINO_PIN_9:
245 reg &= ~MUX_SEL4_MASK;
246 if (type == ARDUINO_GPIO) {
247 reg |= ARDUINO_CFG4_GPIO;
248 } else if (type == ARDUINO_PWM) {
249 reg |= ARDUINO_CFG4_PWM;
250 }
251 break;
252 case ARDUINO_PIN_10:
253 case ARDUINO_PIN_11:
254 case ARDUINO_PIN_12:
255 case ARDUINO_PIN_13:
256 reg &= ~MUX_SEL5_MASK;
257 if (type == ARDUINO_GPIO) {
258 reg |= ARDUINO_CFG5_GPIO;
259 } else if (type == ARDUINO_SPI) {
260 reg |= ARDUINO_CFG5_SPI;
261 } else if (type == ARDUINO_PWM) {
262 reg |= ARDUINO_CFG5_PWM1;
263 }
264 break;
265 case ARDUINO_PIN_AD4:
266 case ARDUINO_PIN_AD5:
267 reg &= ~MUX_SEL6_MASK;
268 if (type == ARDUINO_GPIO) {
269 reg |= ARDUINO_CFG6_GPIO;
270 } else if (type == ARDUINO_I2C) {
271 reg |= ARDUINO_CFG6_I2C;
272 }
273 break;
274 default:
275 break;
276 }
277
278 if (pin <= PMOD_C) {
279 sys_write32(reg, mux_regs + PMOD_MUX_CTRL);
280 } else {
281 sys_write32(reg, mux_regs + ARDUINO_MUX_CTRL);
282 }
283
284 return 0;
285 }
286
pinctrl_configure_pins(const pinctrl_soc_pin_t * pins,uint8_t pin_cnt,uintptr_t reg)287 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
288 {
289 ARG_UNUSED(reg);
290 int i;
291
292 for (i = 0; i < pin_cnt; i++) {
293 pinctrl_emsdp_set(pins[i].pin, pins[i].type);
294 }
295
296 return 0;
297 }
298
