1 /*
2 * Copyright (c) 2018 Synopsys
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/init.h>
8
9 #define PMODMUX_BASE_ADDR 0xF0000000
10
11 /*
12 * 32-bits, offset 0x0, This register controls mapping of the peripheral device
13 * signals on Pmod connectors
14 */
15 #define PMOD_MUX_CTRL 0
16 /* 32-bits, offset 0x4 */
17 #define I2C_MAP_CTRL 1
18
19 /*
20 * 32-bits, offset 0x8, SPI_MAP_CTRL[0] selects the mode of operation of the SPI
21 * Slave: Normal operation, SPI_MAP_CTRL[0]=0: SPI Slave is connected to Pmod1
22 * at connector J1. Loop-back mode, SPI_MAP_CTRL[0]=1: SPI Slave is connected to
23 * the SPI Master inside the FPGA using CS4.
24 */
25 #define SPI_MAP_CTRL 2
26 /*
27 * 32-bits, offset 0x8, This register controls the mapping of the UART signals
28 * on the Pmod1 connector.
29 */
30 #define UART_MAP_CTRL 3
31
32 #define BIT0 (0)
33 #define BIT1 (1)
34 #define BIT2 (2)
35 #define BIT3 (3)
36 #define PM1_OFFSET (0)
37 #define PM2_OFFSET (4)
38 #define PM3_OFFSET (8)
39 #define PM4_OFFSET (12)
40 #define PM5_OFFSET (16)
41 #define PM6_OFFSET (20)
42 #define PM7_OFFSET (24)
43
44 #define PM1_MASK (0xf << PM1_OFFSET)
45 #define PM2_MASK (0xf << PM2_OFFSET)
46 #define PM3_MASK (0xf << PM3_OFFSET)
47 #define PM4_MASK (0xf << PM4_OFFSET)
48 #define PM5_MASK (0xf << PM5_OFFSET)
49 #define PM6_MASK (0xf << PM6_OFFSET)
50 #define PM7_MASK (0xf << PM7_OFFSET)
51
52 #define SPI_MAP_NORMAL (0)
53 #define SPI_MAP_LOOPBACK (1)
54
55 #define UART_MAP_TYPE4 (0xE4)
56 #define UART_MAP_TYPE3 (0x6C)
57
58 /* all pins are configured as GPIO inputs */
59 #define PMOD_MUX_CTRL_DEFAULT (0)
60 /* normal SPI mode */
61 #define SPI_MAP_CTRL_DEFAULT (SPI_MAP_NORMAL)
62 /* TYPE4 PMOD compatible */
63 #define UART_MAP_CTRL_DEFAULT (UART_MAP_TYPE4)
64
65 /* Pmod1[4:1] are connected to DW GPIO Port C[11:8] */
66 #define PM1_UR_GPIO_C ((0 << BIT0) << PM1_OFFSET)
67 /* Pmod1[4:1] are connected to DW UART0 signals */
68 #define PM1_UR_UART_0 ((1 << BIT0) << PM1_OFFSET)
69
70 /* Pmod1[10:7] are connected to DW GPIO Port A[11:8] */
71 #define PM1_LR_GPIO_A ((0 << BIT2) << PM1_OFFSET)
72 /* Pmod1[10:7] are connected to DW SPI Slave signals */
73 #define PM1_LR_SPI_S ((1 << BIT2) << PM1_OFFSET)
74 /*
75 * Pmod2[4:1] are connected to DW GPIO Port C[15:12],
76 * Pmod2[10:7] are connected to DW GPIO Port A[15:12]
77 */
78 #define PM2_GPIO_AC ((0 << BIT0) << PM2_OFFSET)
79 /* connect I2C to Pmod2[4:1] and halt/run interface to Pmod2[10:7] */
80 #define PM2_I2C_HRI ((1 << BIT0) << PM2_OFFSET)
81 /*
82 * Pmod3[4:1] are connected to DW GPIO Port C[19:16],
83 * Pmod3[10:7] are connected to DW GPIO Port A[19:16]
84 */
85 #define PM3_GPIO_AC ((0 << BIT0) << PM3_OFFSET)
86 /*
87 * Pmod3[4:3] are connected to DW I2C signals,
88 * Pmod3[2:1] are connected to DW GPIO Port D[1:0],
89 * Pmod3[10:7] are connected to DW GPIO Port D[3:2]
90 */
91 #define PM3_I2C_GPIO_D ((1 << BIT0) << PM3_OFFSET)
92 /*
93 * Pmod4[4:1] are connected to DW GPIO Port C[23:20],
94 * Pmod4[10:7] are connected to DW GPIO Port A[23:20]
95 */
96 #define PM4_GPIO_AC ((0 << BIT0) << PM4_OFFSET)
97 /*
98 * Pmod4[4:3] are connected to DW I2C signals,
99 * Pmod4[2:1] are connected to DW GPIO Port D[5:4],
100 * Pmod4[10:7] are connected to DW GPIO Port D[7:6]
101 */
102 #define PM4_I2C_GPIO_D ((1 << BIT0) << PM4_OFFSET)
103
104 /* Pmod5[4:1] are connected to DW GPIO Port C[27:24] */
105 #define PM5_UR_GPIO_C ((0 << BIT0) << PM5_OFFSET)
106 /* Pmod5[4:1] are connected to DW SPI Master signals using CS1_N */
107 #define PM5_UR_SPI_M1 ((1 << BIT0) << PM5_OFFSET)
108 /* Pmod5[10:7] are connected to DW GPIO Port A[27:24] */
109 #define PM5_LR_GPIO_A ((0 << BIT2) << PM5_OFFSET)
110 /* Pmod5[10:7] are connected to DW SPI Master signals using CS2_N */
111 #define PM5_LR_SPI_M2 ((1 << BIT2) << PM5_OFFSET)
112
113 /* Pmod6[4:1] are connected to DW GPIO Port C[31:28] */
114 #define PM6_UR_GPIO_C ((0 << BIT0) << PM6_OFFSET)
115 /* Pmod6[4:1] are connected to DW SPI Master signals using CS0_N */
116 #define PM6_UR_SPI_M0 ((1 << BIT0) << PM6_OFFSET)
117 /* Pmod6[10:7] are connected to DW GPIO Port A[31:28] */
118 #define PM6_LR_GPIO_A ((0 << BIT2) << PM6_OFFSET)
119 /*
120 * Pmod6[8:7] are connected to the DW SPI Master chip select signals CS1_N and
121 * CS2_N, Pmod6[6:5] are connected to the ARC EM halt and sleep status signals
122 */
123 #define PM6_LR_CSS_STAT ((1 << BIT2) << PM6_OFFSET)
124
125
pmod_mux_init(void)126 static int pmod_mux_init(void)
127 {
128 volatile uint32_t *mux_regs = (uint32_t *)(PMODMUX_BASE_ADDR);
129
130 mux_regs[SPI_MAP_CTRL] = SPI_MAP_CTRL_DEFAULT;
131 mux_regs[UART_MAP_CTRL] = UART_MAP_CTRL_DEFAULT;
132
133 /**
134 * + Please refer to corresponding EMSK User Guide for detailed
135 * information -> Appendix: A Hardware Functional Description ->
136 * Pmods Configuration summary
137 * + Set up pin-multiplexer of all PMOD connections
138 * - PM1 J1: Upper row as UART 0, lower row as SPI Slave
139 * - PM2 J2: IIC 0 and run/halt signals
140 * - PM3 J3: GPIO Port A and Port C
141 * - PM4 J4: IIC 1 and Port D
142 * - PM5 J5: Upper row as SPI Master, lower row as Port A
143 * - PM6 J6: Upper row as SPI Master, lower row as Port A
144 */
145 mux_regs[PMOD_MUX_CTRL] = PM1_UR_UART_0 | PM1_LR_SPI_S
146 | PM2_I2C_HRI | PM3_GPIO_AC
147 | PM4_I2C_GPIO_D | PM5_UR_SPI_M1
148 | PM5_LR_GPIO_A | PM6_UR_SPI_M0
149 | PM6_LR_GPIO_A;
150 return 0;
151 }
152
153
154 SYS_INIT(pmod_mux_init, PRE_KERNEL_1,
155 CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
156
