1 /* 2 * Copyright (c) 2022 Intel Corporation 3 * 4 * Intel I/O Controller Hub (ICH) later renamed to Intel Platform Controller 5 * Hub (PCH) SMBus driver. 6 * 7 * PCH provides SMBus 2.0 - compliant Host Controller. 8 * 9 * SPDX-License-Identifier: Apache-2.0 10 */ 11 12 #ifndef ZEPHYR_DRIVERS_SMBUS_PCH_H_ 13 #define ZEPHYR_DRIVERS_SMBUS_PCH_H_ 14 15 /* PCI Configuration Space registers */ 16 17 /* Host Configuration (HCFG) - Offset 40h, 8 bits */ 18 #define PCH_SMBUS_HCFG 0x10 19 #define PCH_SMBUS_HCFG_HST_EN BIT(0) /* Enable SMBus controller */ 20 21 /* PCH SMBus I/O and Memory Mapped registers */ 22 23 /* Host Status Register Address (HSTS) */ 24 #define PCH_SMBUS_HSTS 0x00 25 #define PCH_SMBUS_HSTS_HOST_BUSY BIT(0) /* Host Busy */ 26 #define PCH_SMBUS_HSTS_INTERRUPT BIT(1) /* Interrupt */ 27 #define PCH_SMBUS_HSTS_DEV_ERROR BIT(2) /* Device Error */ 28 #define PCH_SMBUS_HSTS_BUS_ERROR BIT(3) /* Bus Error */ 29 #define PCH_SMBUS_HSTS_FAILED BIT(4) /* Failed */ 30 #define PCH_SMBUS_HSTS_SMB_ALERT BIT(5) /* SMB Alert */ 31 #define PCH_SMBUS_HSTS_INUSE BIT(6) /* In Use */ 32 #define PCH_SMBUS_HSTS_BYTE_DONE BIT(7) /* Byte Done */ 33 34 #define PCH_SMBUS_HSTS_ERROR (PCH_SMBUS_HSTS_DEV_ERROR | \ 35 PCH_SMBUS_HSTS_BUS_ERROR | \ 36 PCH_SMBUS_HSTS_FAILED) 37 38 /* Host Control Register (HCTL) */ 39 #define PCH_SMBUS_HCTL 0x02 /* Host Control */ 40 #define PCH_SMBUS_HCTL_INTR_EN BIT(0) /* INT Enable */ 41 #define PCH_SMBUS_HCTL_KILL BIT(1) /* Kill current trans */ 42 #define PCH_SMBUS_HCTL_CMD GENMASK(4, 2) /* Command */ 43 /* SMBUS Commands */ 44 #define PCH_SMBUS_HCTL_CMD_QUICK (0 << 2) /* Quick cmd*/ 45 #define PCH_SMBUS_HCTL_CMD_BYTE (1 << 2) /* Byte cmd */ 46 #define PCH_SMBUS_HCTL_CMD_BYTE_DATA (2 << 2) /* Byte Data cmd */ 47 #define PCH_SMBUS_HCTL_CMD_WORD_DATA (3 << 2) /* Word Data cmd */ 48 #define PCH_SMBUS_HCTL_CMD_PROC_CALL (4 << 2) /* Process Call cmd */ 49 #define PCH_SMBUS_HCTL_CMD_BLOCK (5 << 2) /* Block cmd */ 50 #define PCH_SMBUS_HCTL_CMD_I2C_READ (6 << 2) /* I2C Read cmd */ 51 #define PCH_SMBUS_HCTL_CMD_BLOCK_PROC (7 << 2) /* Block Process cmd */ 52 53 #define PCH_SMBUS_HCTL_CMD_SET(cmd) (cmd << 2) 54 55 #define PCH_SMBUS_HCTL_CMD_GET(val) (val & PCH_SMBUS_HCTL_CMD) 56 57 #define PCH_SMBUS_HCTL_LAST_BYTE BIT(5) /* Last byte block op */ 58 #define PCH_SMBUS_HCTL_START BIT(6) /* Start SMBUS cmd */ 59 #define PCH_SMBUS_HCTL_PEC_EN BIT(7) /* Enable PEC */ 60 61 /* Host Command Register (HCMD) */ 62 #define PCH_SMBUS_HCMD 0x03 63 64 /* Transmit Slave Address Register (TSA) */ 65 #define PCH_SMBUS_TSA 0x04 66 #define PCH_SMBUS_TSA_RW BIT(0) /* Direction */ 67 #define PCH_SMBUS_TSA_ADDR_MASK GENMASK(7, 1) /* Address mask */ 68 69 /* Set 7-bit address */ 70 #define PCH_SMBUS_TSA_ADDR_SET(addr) (((addr) & BIT_MASK(7)) << 1) 71 72 /* Get Peripheral address from register value */ 73 #define PCH_SMBUS_TSA_ADDR_GET(reg) ((reg >> 1) & BIT_MASK(7)) 74 75 /* Data 0 Register (HD0) */ 76 #define PCH_SMBUS_HD0 0x05 /* Data 0 / Count */ 77 78 /* Data 1 Register (HD1) */ 79 #define PCH_SMBUS_HD1 0x06 /* Data 1 */ 80 81 /* Host Block Data (HBD) */ 82 #define PCH_SMBUS_HBD 0x07 /* Host block data */ 83 84 /* Packet Error Check Data Register (PEC) */ 85 #define PCH_SMBUS_PEC 0x08 /* PEC data */ 86 87 /* Receive Slave Address Register (RSA) */ 88 #define PCH_SMBUS_RSA 0x09 /* Receive slave addr */ 89 90 /* Slave Data Register (SD) (16 bits) */ 91 #define PCH_SMBUS_SD 0x0a /* Slave data */ 92 93 /* Auxiliary Status (AUXS) */ 94 #define PCH_SMBUS_AUXS 0x0c /* Auxiliary Status */ 95 #define PCH_SMBUS_AUXS_CRC_ERROR BIT(0) /* CRC error */ 96 97 /* Auxiliary Control (AUXC) */ 98 #define PCH_SMBUS_AUXC 0x0d /* Auxiliary Control */ 99 #define PCH_SMBUS_AUXC_AAC BIT(0) /* Auto append CRC */ 100 #define PCH_SMBUS_AUXC_EN_32BUF BIT(1) /* Enable 32-byte buf */ 101 102 /* SMLink Pin Control Register (SMLC) */ 103 #define PCH_SMBUS_SMLC 0x0e /* SMLink pin control */ 104 105 /* SMBus Pin control Register (SMBC) */ 106 #define PCH_SMBUS_SMBC 0x0f /* SMBus pin control */ 107 #define PCH_SMBUS_SMBC_CLK_CUR_STS BIT(0) /* SMBCLK pin status */ 108 #define PCH_SMBUS_SMBC_DATA_CUR_STS BIT(1) /* SMBDATA pin status */ 109 #define PCH_SMBUS_SMBC_CLK_CTL BIT(2) /* SMBCLK pin CTL */ 110 111 /* Slave Status Register (SSTS) */ 112 #define PCH_SMBUS_SSTS 0x10 /* Slave Status */ 113 #define PCH_SMBUS_SSTS_HNS BIT(0) /* Host Notify Status */ 114 115 /* Slave Command Register (SCMD) */ 116 #define PCH_SMBUS_SCMD 0x11 /* Slave Command */ 117 #define PCH_SMBUS_SCMD_HNI_EN BIT(0) /* Host Notify INT En */ 118 #define PCH_SMBUS_SCMD_HNW_EN BIT(1) /* Host Notify Wake */ 119 #define PCH_SMBUS_SCMD_SMBALERT_DIS BIT(2) /* Disable Smbalert */ 120 121 /* Notify Device Address Register (NDA) */ 122 #define PCH_SMBUS_NDA 0x14 /* Notify Device addr */ 123 124 /* Notify Data Low Byte Register (NDLB) */ 125 #define PCH_SMBUS_NDLB 0x16 /* Notify Data low */ 126 127 /* Notify Data High Byte Register (NDHB) */ 128 #define PCH_SMBUS_NDHB 0x17 /* Notify Data high */ 129 130 /* Debug helpers */ 131 132 #if CONFIG_SMBUS_LOG_LEVEL >= LOG_LEVEL_DBG 133 /* Dump HSTS register using define to show calling function */ 134 #define pch_dump_register_hsts(reg) \ 135 LOG_DBG("HSTS: 0x%02x: %s%s%s%s%s%s%s%s", reg, \ 136 reg & PCH_SMBUS_HSTS_HOST_BUSY ? "[Host Busy] " : "", \ 137 reg & PCH_SMBUS_HSTS_INTERRUPT ? "[Interrupt] " : "", \ 138 reg & PCH_SMBUS_HSTS_DEV_ERROR ? "[Device Error] " : "",\ 139 reg & PCH_SMBUS_HSTS_BUS_ERROR ? "[Bus Error] " : "", \ 140 reg & PCH_SMBUS_HSTS_FAILED ? "[Failed] " : "", \ 141 reg & PCH_SMBUS_HSTS_SMB_ALERT ? "[SMBALERT] " : "", \ 142 reg & PCH_SMBUS_HSTS_BYTE_DONE ? "[Byte Done] " : "", \ 143 reg & PCH_SMBUS_HSTS_INUSE ? "[In USE] " : ""); 144 #else 145 #define pch_dump_register_hsts(reg) 146 #endif 147 148 #endif /* ZEPHYR_DRIVERS_SMBUS_PCH_H_ */ 149
