1 /*
2 * Copyright (c) 2018-2019 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT intel_gpio
8
9 /**
10 * @file
11 * @brief Intel GPIO Controller Driver
12 *
13 * The GPIO controller on Intel SoC serves
14 * both GPIOs and Pinmuxing function. This driver provides
15 * the GPIO function.
16 *
17 * Due to GPIO callback only allowing 32 pins (as a 32-bit mask) at once,
18 * each set is further sub-divided into multiple devices, so
19 * we export GPIO_INTEL_NR_SUBDEVS devices to the kernel.
20 */
21
22 #include <errno.h>
23 #include <zephyr/drivers/gpio.h>
24 #include <soc.h>
25 #include <zephyr/sys/sys_io.h>
26 #include <zephyr/sys/__assert.h>
27 #include <zephyr/sys/slist.h>
28 #include <zephyr/sys/speculation.h>
29 #include <zephyr/irq.h>
30
31 #include <zephyr/drivers/gpio/gpio_utils.h>
32
33 BUILD_ASSERT(DT_INST_IRQN(0) == 14);
34
35 #define REG_MISCCFG 0x0010
36 #define MISCCFG_IRQ_ROUTE_POS 3
37
38 #define PAD_OWN_MASK 0x03
39 #define PAD_OWN_HOST 0
40 #define PAD_OWN_CSME 1
41 #define PAD_OWN_ISH 2
42 #define PAD_OWN_IE 3
43
44 #define PAD_HOST_SW_OWN_GPIO 1
45 #define PAD_HOST_SW_OWN_ACPI 0
46
47
48 #define PAD_CFG0_RXPADSTSEL BIT(29)
49 #define PAD_CFG0_RXRAW1 BIT(28)
50
51
52 #define PAD_CFG0_RXEVCFG_POS 25
53 #define PAD_CFG0_RXEVCFG_MASK (0x03 << PAD_CFG0_RXEVCFG_POS)
54 #define PAD_CFG0_RXEVCFG_LEVEL (0 << PAD_CFG0_RXEVCFG_POS)
55 #define PAD_CFG0_RXEVCFG_EDGE (1 << PAD_CFG0_RXEVCFG_POS)
56 #define PAD_CFG0_RXEVCFG_DRIVE0 (2 << PAD_CFG0_RXEVCFG_POS)
57
58 #define PAD_CFG0_PREGFRXSEL BIT(24)
59 #define PAD_CFG0_RXINV BIT(23)
60
61 #define PAD_CFG0_RXDIS BIT(9)
62 #define PAD_CFG0_TXDIS BIT(8)
63 #define PAD_CFG0_RXSTATE BIT(1)
64 #define PAD_CFG0_RXSTATE_POS 1
65 #define PAD_CFG0_TXSTATE BIT(0)
66 #define PAD_CFG0_TXSTATE_POS 0
67
68 #define PAD_CFG1_IOSTERM_POS 8
69 #define PAD_CFG1_IOSTERM_MASK (0x03 << PAD_CFG1_IOSTERM_POS)
70 #define PAD_CFG1_IOSTERM_FUNC (0 << PAD_CFG1_IOSTERM_POS)
71 #define PAD_CFG1_IOSTERM_DISPUD (1 << PAD_CFG1_IOSTERM_POS)
72 #define PAD_CFG1_IOSTERM_PU (2 << PAD_CFG1_IOSTERM_POS)
73 #define PAD_CFG1_IOSTERM_PD (3 << PAD_CFG1_IOSTERM_POS)
74
75 #define PAD_CFG1_TERM_POS 10
76 #define PAD_CFG1_TERM_MASK (0x0F << PAD_CFG1_TERM_POS)
77 #define PAD_CFG1_TERM_NONE (0x00 << PAD_CFG1_TERM_POS)
78 #define PAD_CFG1_TERM_PD_5K (0x02 << PAD_CFG1_TERM_POS)
79 #define PAD_CFG1_TERM_PD_20K (0x04 << PAD_CFG1_TERM_POS)
80 #define PAD_CFG1_TERM_NONE2 (0x08 << PAD_CFG1_TERM_POS)
81 #define PAD_CFG1_TERM_PU_1K (0x09 << PAD_CFG1_TERM_POS)
82 #define PAD_CFG1_TERM_PU_5K (0x0A << PAD_CFG1_TERM_POS)
83 #define PAD_CFG1_TERM_PU_2K (0x0B << PAD_CFG1_TERM_POS)
84 #define PAD_CFG1_TERM_PU_20K (0x0C << PAD_CFG1_TERM_POS)
85 #define PAD_CFG1_TERM_PU_1K_2K (0x0D << PAD_CFG1_TERM_POS)
86
87 #define PAD_CFG1_IOSSTATE_POS 14
88 #define PAD_CFG1_IOSSTATE_MASK (0x0F << PAD_CFG1_IOSSTATE_POS)
89 #define PAD_CFG1_IOSSTATE_IGNORE (0x0F << PAD_CFG1_IOSSTATE_POS)
90
91 /* Required by DEVICE_MMIO_NAMED_* macros */
92 #define DEV_CFG(_dev) \
93 ((const struct gpio_intel_config *)(_dev)->config)
94 #define DEV_DATA(_dev) ((struct gpio_intel_data *)(_dev)->data)
95
96 struct gpio_intel_config {
97 /* gpio_driver_config needs to be first */
98 struct gpio_driver_config common;
99
100 DEVICE_MMIO_NAMED_ROM(reg_base);
101
102 uint8_t pin_offset;
103 uint8_t group_index;
104 uint8_t num_pins;
105 };
106
107 struct gpio_intel_data {
108 /* gpio_driver_data needs to be first */
109 struct gpio_driver_data common;
110
111 DEVICE_MMIO_NAMED_RAM(reg_base);
112
113 /* Pad base address */
114 uint32_t pad_base;
115
116 sys_slist_t cb;
117 };
118
regs(const struct device * dev)119 static inline mm_reg_t regs(const struct device *dev)
120 {
121 return GPIO_REG_BASE(DEVICE_MMIO_NAMED_GET(dev, reg_base));
122 }
123
pad_base(const struct device * dev)124 static inline mm_reg_t pad_base(const struct device *dev)
125 {
126 return GPIO_PAD_BASE(DEVICE_MMIO_NAMED_GET(dev, reg_base));
127 }
128
129 #ifdef CONFIG_GPIO_INTEL_CHECK_PERMS
130 /**
131 * @brief Check if host has permission to alter this GPIO pin.
132 *
133 * @param "struct device *dev" Device struct
134 * @param "uint32_t raw_pin" Raw GPIO pin
135 *
136 * @return true if host owns the GPIO pin, false otherwise
137 */
check_perm(const struct device * dev,uint32_t raw_pin)138 static bool check_perm(const struct device *dev, uint32_t raw_pin)
139 {
140 struct gpio_intel_data *data = dev->data;
141 const struct gpio_intel_config *cfg = dev->config;
142 uint32_t offset, val, pin_offset;
143
144 pin_offset = cfg->pin_offset;
145 /* First is to establish that host software owns the pin */
146
147 /* read the Pad Ownership register related to the pin */
148 offset = GPIO_PAD_OWNERSHIP(raw_pin, pin_offset);
149 val = sys_read32(regs(dev) + offset);
150
151 /* get the bits about ownership */
152 offset = GPIO_OWNERSHIP_BIT(raw_pin);
153 val = (val >> offset) & PAD_OWN_MASK;
154 if (val) {
155 /* PAD_OWN_HOST == 0, so !0 => false*/
156 return false;
157 }
158
159 /* Also need to make sure the function of pad is GPIO */
160 offset = data->pad_base + (raw_pin << 4);
161 val = sys_read32(regs(dev) + offset);
162 if (val & PAD_CFG0_PMODE_MASK) {
163 /* mode is not zero => not functioning as GPIO */
164 return false;
165 }
166
167 return true;
168 }
169 #else
170 #define check_perm(...) (1)
171 #endif
172
173 /*
174 * as the kernel initializes the subdevices, we add them
175 * to the list of devices to check at ISR time.
176 */
177
178 static int nr_isr_devs;
179
180 static const struct device *isr_devs[GPIO_INTEL_NR_SUBDEVS];
181
gpio_intel_isr(const struct device * dev)182 static void gpio_intel_isr(const struct device *dev)
183 {
184 const struct gpio_intel_config *cfg;
185 struct gpio_intel_data *data;
186 struct gpio_callback *cb, *tmp;
187 uint32_t reg, int_sts, cur_mask, acc_mask;
188 int isr_dev;
189
190 for (isr_dev = 0; isr_dev < nr_isr_devs; ++isr_dev) {
191 dev = isr_devs[isr_dev];
192 cfg = dev->config;
193 data = dev->data;
194
195 reg = regs(dev) + REG_GPI_INT_STS_BASE
196 + GPIO_INTERRUPT_BASE(cfg);
197 int_sts = sys_read32(reg);
198 acc_mask = 0U;
199
200 SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&data->cb, cb, tmp, node) {
201 cur_mask = int_sts & cb->pin_mask;
202 acc_mask |= cur_mask;
203 if (cur_mask) {
204 __ASSERT(cb->handler, "No callback handler!");
205 cb->handler(dev, cb, cur_mask);
206 }
207 }
208
209 /* clear handled interrupt bits */
210 sys_write32(acc_mask, reg);
211 }
212 }
213
gpio_intel_config(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)214 static int gpio_intel_config(const struct device *dev,
215 gpio_pin_t pin, gpio_flags_t flags)
216 {
217 const struct gpio_intel_config *cfg = dev->config;
218 struct gpio_intel_data *data = dev->data;
219 uint32_t raw_pin, reg, cfg0, cfg1;
220
221 /* Only support push-pull mode */
222 if ((flags & GPIO_SINGLE_ENDED) != 0U) {
223 return -ENOTSUP;
224 }
225
226 pin = k_array_index_sanitize(pin, cfg->num_pins + 1);
227
228 raw_pin = GPIO_RAW_PIN(pin, cfg->pin_offset);
229
230 if (!check_perm(dev, raw_pin)) {
231 return -EINVAL;
232 }
233
234 /* read in pad configuration register */
235 reg = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET);
236 cfg0 = sys_read32(reg);
237 cfg1 = sys_read32(reg + 4);
238
239 /* don't override RX to 1 */
240 cfg0 &= ~(PAD_CFG0_RXRAW1);
241
242 /* set input/output */
243 if ((flags & GPIO_INPUT) != 0U) {
244 /* clear RX disable bit */
245 cfg0 &= ~PAD_CFG0_RXDIS;
246 } else {
247 /* set RX disable bit */
248 cfg0 |= PAD_CFG0_RXDIS;
249 }
250
251 if ((flags & GPIO_OUTPUT) != 0U) {
252 /* pin to output */
253
254 /* set pin output if desired */
255 if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
256 cfg0 |= PAD_CFG0_TXSTATE;
257 } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
258 cfg0 &= ~PAD_CFG0_TXSTATE;
259 }
260
261 /* clear TX disable bit */
262 cfg0 &= ~PAD_CFG0_TXDIS;
263 } else {
264 /* set TX disable bit */
265 cfg0 |= PAD_CFG0_TXDIS;
266 }
267
268 /* pull-up or pull-down */
269 cfg1 &= ~(PAD_CFG1_TERM_MASK | PAD_CFG1_IOSTERM_MASK);
270 if ((flags & GPIO_PULL_UP) != 0U) {
271 cfg1 |= (PAD_CFG1_TERM_PU_20K | PAD_CFG1_IOSTERM_PU);
272 } else if ((flags & GPIO_PULL_DOWN) != 0U) {
273 cfg1 |= (PAD_CFG1_TERM_PD_20K | PAD_CFG1_IOSTERM_PD);
274 } else {
275 cfg1 |= (PAD_CFG1_TERM_NONE | PAD_CFG1_IOSTERM_FUNC);
276 }
277
278 /* IO Standby state to TX,RX enabled */
279 cfg1 &= ~PAD_CFG1_IOSSTATE_MASK;
280
281 /* write back pad configuration register after all changes */
282 sys_write32(cfg0, reg);
283 sys_write32(cfg1, reg + 4);
284
285 return 0;
286 }
287
gpio_intel_pin_interrupt_configure(const struct device * dev,gpio_pin_t pin,enum gpio_int_mode mode,enum gpio_int_trig trig)288 static int gpio_intel_pin_interrupt_configure(const struct device *dev,
289 gpio_pin_t pin,
290 enum gpio_int_mode mode,
291 enum gpio_int_trig trig)
292 {
293 const struct gpio_intel_config *cfg = dev->config;
294 struct gpio_intel_data *data = dev->data;
295 uint32_t raw_pin, cfg0, cfg1;
296 uint32_t reg, reg_en, reg_sts;
297
298 /* no double-edge triggering according to data sheet */
299 if (trig == GPIO_INT_TRIG_BOTH) {
300 return -ENOTSUP;
301 }
302
303 pin = k_array_index_sanitize(pin, cfg->num_pins + 1);
304
305 raw_pin = GPIO_RAW_PIN(pin, cfg->pin_offset);
306
307 if (!check_perm(dev, raw_pin)) {
308 return -EINVAL;
309 }
310
311 /* set owner to GPIO driver mode for legacy interrupt mode */
312 reg = regs(dev) + REG_PAD_HOST_SW_OWNER + GPIO_BASE(cfg);
313 sys_bitfield_set_bit(reg, raw_pin);
314
315 /* read in pad configuration register */
316 reg = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET);
317 cfg0 = sys_read32(reg);
318 cfg1 = sys_read32(reg + 4);
319
320 reg_en = regs(dev) + REG_GPI_INT_EN_BASE + GPIO_BASE(cfg);
321
322 /* disable interrupt bit first before setup */
323 sys_bitfield_clear_bit(reg_en, raw_pin);
324
325 /* clear (by setting) interrupt status bit */
326 reg_sts = regs(dev) + REG_GPI_INT_STS_BASE + GPIO_BASE(cfg);
327 sys_bitfield_set_bit(reg_sts, raw_pin);
328
329 /* clear level/edge configuration bits */
330 cfg0 &= ~PAD_CFG0_RXEVCFG_MASK;
331
332 if (mode == GPIO_INT_MODE_DISABLED) {
333 /* set RX conf to drive 0 */
334 cfg0 |= PAD_CFG0_RXEVCFG_DRIVE0;
335 } else {
336 /* cannot enable interrupt without pin as input */
337 if ((cfg0 & PAD_CFG0_RXDIS) != 0U) {
338 return -ENOTSUP;
339 }
340
341 /*
342 * Do not enable interrupt with pin as output.
343 * Hardware does not seem to support triggering
344 * interrupt by setting line as both input/output
345 * and then setting output to desired level.
346 * So just say not supported.
347 */
348 if ((cfg0 & PAD_CFG0_TXDIS) == 0U) {
349 return -ENOTSUP;
350 }
351
352 if (mode == GPIO_INT_MODE_LEVEL) {
353 /* level trigger */
354 cfg0 |= PAD_CFG0_RXEVCFG_LEVEL;
355 } else {
356 /* edge trigger */
357 cfg0 |= PAD_CFG0_RXEVCFG_EDGE;
358 }
359
360 /* invert pin for active low triggering */
361 if (trig == GPIO_INT_TRIG_LOW) {
362 cfg0 |= PAD_CFG0_RXINV;
363 } else {
364 cfg0 &= ~PAD_CFG0_RXINV;
365 }
366 }
367
368 /* write back pad configuration register after all changes */
369 sys_write32(cfg0, reg);
370 sys_write32(cfg1, reg + 4);
371
372 if (mode != GPIO_INT_MODE_DISABLED) {
373 /* enable interrupt bit */
374 sys_bitfield_set_bit(reg_en, raw_pin);
375 }
376
377 return 0;
378 }
379
gpio_intel_manage_callback(const struct device * dev,struct gpio_callback * callback,bool set)380 static int gpio_intel_manage_callback(const struct device *dev,
381 struct gpio_callback *callback,
382 bool set)
383 {
384 struct gpio_intel_data *data = dev->data;
385
386 return gpio_manage_callback(&data->cb, callback, set);
387 }
388
port_get_raw(const struct device * dev,uint32_t mask,uint32_t * value,bool read_tx)389 static int port_get_raw(const struct device *dev, uint32_t mask,
390 uint32_t *value,
391 bool read_tx)
392 {
393 const struct gpio_intel_config *cfg = dev->config;
394 struct gpio_intel_data *data = dev->data;
395 uint32_t pin, raw_pin, reg_addr, reg_val, cmp;
396
397 if (read_tx) {
398 cmp = PAD_CFG0_TXSTATE;
399 } else {
400 cmp = PAD_CFG0_RXSTATE;
401 }
402
403 *value = 0;
404 while (mask != 0U) {
405 pin = find_lsb_set(mask) - 1;
406
407 if (pin >= cfg->num_pins) {
408 break;
409 }
410
411 mask &= ~BIT(pin);
412
413 raw_pin = GPIO_RAW_PIN(pin, cfg->pin_offset);
414
415 if (!check_perm(dev, raw_pin)) {
416 continue;
417 }
418
419 reg_addr = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET);
420 reg_val = sys_read32(reg_addr);
421
422 if ((reg_val & cmp) != 0U) {
423 *value |= BIT(pin);
424 }
425 }
426
427 return 0;
428 }
429
port_set_raw(const struct device * dev,uint32_t mask,uint32_t value)430 static int port_set_raw(const struct device *dev, uint32_t mask,
431 uint32_t value)
432 {
433 const struct gpio_intel_config *cfg = dev->config;
434 struct gpio_intel_data *data = dev->data;
435 uint32_t pin, raw_pin, reg_addr, reg_val;
436
437 while (mask != 0) {
438 pin = find_lsb_set(mask) - 1;
439
440 if (pin >= cfg->num_pins) {
441 break;
442 }
443
444 mask &= ~BIT(pin);
445
446 raw_pin = GPIO_RAW_PIN(pin, cfg->pin_offset);
447
448 if (!check_perm(dev, raw_pin)) {
449 continue;
450 }
451
452 reg_addr = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET);
453 reg_val = sys_read32(reg_addr);
454
455 if ((value & BIT(pin)) != 0) {
456 reg_val |= PAD_CFG0_TXSTATE;
457 } else {
458 reg_val &= ~PAD_CFG0_TXSTATE;
459 }
460
461 sys_write32(reg_val, reg_addr);
462 }
463
464 return 0;
465 }
466
gpio_intel_port_set_masked_raw(const struct device * dev,uint32_t mask,uint32_t value)467 static int gpio_intel_port_set_masked_raw(const struct device *dev,
468 uint32_t mask,
469 uint32_t value)
470 {
471 uint32_t port_val;
472
473 port_get_raw(dev, mask, &port_val, true);
474
475 port_val = (port_val & ~mask) | (mask & value);
476
477 port_set_raw(dev, mask, port_val);
478
479 return 0;
480 }
481
gpio_intel_port_set_bits_raw(const struct device * dev,uint32_t mask)482 static int gpio_intel_port_set_bits_raw(const struct device *dev,
483 uint32_t mask)
484 {
485 return gpio_intel_port_set_masked_raw(dev, mask, mask);
486 }
487
gpio_intel_port_clear_bits_raw(const struct device * dev,uint32_t mask)488 static int gpio_intel_port_clear_bits_raw(const struct device *dev,
489 uint32_t mask)
490 {
491 return gpio_intel_port_set_masked_raw(dev, mask, 0);
492 }
493
gpio_intel_port_toggle_bits(const struct device * dev,uint32_t mask)494 static int gpio_intel_port_toggle_bits(const struct device *dev,
495 uint32_t mask)
496 {
497 uint32_t port_val;
498
499 port_get_raw(dev, mask, &port_val, true);
500
501 port_val ^= mask;
502
503 port_set_raw(dev, mask, port_val);
504
505 return 0;
506 }
507
gpio_intel_port_get_raw(const struct device * dev,uint32_t * value)508 static int gpio_intel_port_get_raw(const struct device *dev,
509 uint32_t *value)
510 {
511 return port_get_raw(dev, 0xFFFFFFFF, value, false);
512 }
513
514 static const struct gpio_driver_api gpio_intel_api = {
515 .pin_configure = gpio_intel_config,
516 .manage_callback = gpio_intel_manage_callback,
517 .port_get_raw = gpio_intel_port_get_raw,
518 .port_set_masked_raw = gpio_intel_port_set_masked_raw,
519 .port_set_bits_raw = gpio_intel_port_set_bits_raw,
520 .port_clear_bits_raw = gpio_intel_port_clear_bits_raw,
521 .port_toggle_bits = gpio_intel_port_toggle_bits,
522 .pin_interrupt_configure = gpio_intel_pin_interrupt_configure,
523 };
524
gpio_intel_init(const struct device * dev)525 int gpio_intel_init(const struct device *dev)
526 {
527 struct gpio_intel_data *data = dev->data;
528
529 #ifdef CONFIG_SOC_APOLLO_LAKE
530 /*
531 * On Apollo Lake, each GPIO controller has more than 32 pins.
532 * But Zephyr API can only manipulate 32 pins per controller.
533 * So the workaround is to divide each hardware GPIO controller
534 * into 32-pin blocks so each block has a GPIO driver instance.
535 * Compounding to the issue is that there cannot be two device
536 * tree nodes with same register address. So another workaround
537 * is to increment the register addresses by 1 for each block.
538 * So when mapping the address, the lowest 8-bit needs to be
539 * masked to get the actual hardware address. Hence the weird
540 * code below.
541 */
542
543 const struct gpio_intel_config *cfg = dev->config;
544
545 device_map(&data->reg_base,
546 cfg->reg_base.phys_addr & ~0xFFU,
547 cfg->reg_base.size,
548 K_MEM_CACHE_NONE);
549 #else
550 DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE);
551 #endif
552 data->pad_base = pad_base(dev);
553
554 __ASSERT(nr_isr_devs < GPIO_INTEL_NR_SUBDEVS, "too many subdevs");
555
556 if (nr_isr_devs == 0) {
557 /* Note that all controllers are using the same IRQ line.
558 * So we can just use the values from the first instance.
559 */
560 IRQ_CONNECT(DT_INST_IRQN(0),
561 DT_INST_IRQ(0, priority),
562 gpio_intel_isr, NULL,
563 DT_INST_IRQ(0, sense));
564
565 irq_enable(DT_INST_IRQN(0));
566 }
567
568 isr_devs[nr_isr_devs++] = dev;
569
570 if (IS_ENABLED(CONFIG_SOC_APOLLO_LAKE)) {
571 /* route to IRQ 14 */
572 sys_bitfield_clear_bit(regs(dev) + REG_MISCCFG,
573 MISCCFG_IRQ_ROUTE_POS);
574 }
575 return 0;
576 }
577
578 #define GPIO_INTEL_DEV_CFG_DATA(n) \
579 static const struct gpio_intel_config \
580 gpio_intel_cfg_##n = { \
581 .common = { \
582 .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
583 }, \
584 DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)), \
585 .pin_offset = DT_INST_PROP(n, pin_offset), \
586 .group_index = DT_INST_PROP_OR(n, group_index, 0), \
587 .num_pins = DT_INST_PROP(n, ngpios), \
588 }; \
589 \
590 static struct gpio_intel_data gpio_intel_data_##n; \
591 \
592 DEVICE_DT_INST_DEFINE(n, \
593 gpio_intel_init, \
594 NULL, \
595 &gpio_intel_data_##n, \
596 &gpio_intel_cfg_##n, \
597 POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY, \
598 &gpio_intel_api);
599
600 /* "sub" devices. no more than GPIO_INTEL_NR_SUBDEVS of these! */
601 DT_INST_FOREACH_STATUS_OKAY(GPIO_INTEL_DEV_CFG_DATA)
602
