1 /*
2 * Copyright (c) 2020 Nuvoton Technology Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #ifndef _NUVOTON_NPCX_REG_DEF_H
8 #define _NUVOTON_NPCX_REG_DEF_H
9
10 #include <stdint.h>
11
12 #include <zephyr/devicetree.h>
13 #include <zephyr/sys/__assert.h>
14 #include <zephyr/sys/util_macro.h>
15 #include <zephyr/toolchain.h>
16
17 /*
18 * NPCX register structure size/offset checking macro function to mitigate
19 * the risk of unexpected compiling results. All addresses of NPCX registers
20 * must meet the alignment requirement of cortex-m4.
21 * DO NOT use 'packed' attribute if module contains different length ie.
22 * 8/16/32 bits registers.
23 */
24 #define NPCX_REG_SIZE_CHECK(reg_def, size) \
25 BUILD_ASSERT(sizeof(struct reg_def) == size, \
26 "Failed in size check of register structure!")
27 #define NPCX_REG_OFFSET_CHECK(reg_def, member, offset) \
28 BUILD_ASSERT(offsetof(struct reg_def, member) == offset, \
29 "Failed in offset check of register structure member!")
30
31 /*
32 * NPCX register access checking via structure macro function to mitigate the
33 * risk of unexpected compiling results if module contains different length
34 * registers. For example, a word register access might break into two byte
35 * register accesses by adding 'packed' attribute.
36 *
37 * For example, add this macro for word register 'PRSC' of PWM module in its
38 * device init function for checking violation. Once it occurred, core will be
39 * stalled forever and easy to find out what happens.
40 */
41 #define NPCX_REG_WORD_ACCESS_CHECK(reg, val) { \
42 uint16_t placeholder = reg; \
43 reg = val; \
44 __ASSERT(reg == val, "16-bit reg access failed!"); \
45 reg = placeholder; \
46 }
47 #define NPCX_REG_DWORD_ACCESS_CHECK(reg, val) { \
48 uint32_t placeholder = reg; \
49 reg = val; \
50 __ASSERT(reg == val, "32-bit reg access failed!"); \
51 reg = placeholder; \
52 }
53 /*
54 * Core Domain Clock Generator (CDCG) device registers
55 */
56 struct cdcg_reg {
57 /* High Frequency Clock Generator (HFCG) registers */
58 /* 0x000: HFCG Control */
59 volatile uint8_t HFCGCTRL;
60 volatile uint8_t reserved1;
61 /* 0x002: HFCG M Low Byte Value */
62 volatile uint8_t HFCGML;
63 volatile uint8_t reserved2;
64 /* 0x004: HFCG M High Byte Value */
65 volatile uint8_t HFCGMH;
66 volatile uint8_t reserved3;
67 /* 0x006: HFCG N Value */
68 volatile uint8_t HFCGN;
69 volatile uint8_t reserved4;
70 /* 0x008: HFCG Prescaler */
71 volatile uint8_t HFCGP;
72 volatile uint8_t reserved5[7];
73 /* 0x010: HFCG Bus Clock Dividers */
74 volatile uint8_t HFCBCD;
75 volatile uint8_t reserved6;
76 /* 0x012: HFCG Bus Clock Dividers */
77 volatile uint8_t HFCBCD1;
78 volatile uint8_t reserved7;
79 /* 0x014: HFCG Bus Clock Dividers */
80 volatile uint8_t HFCBCD2;
81 volatile uint8_t reserved8[235];
82
83 /* Low Frequency Clock Generator (LFCG) registers */
84 /* 0x100: LFCG Control */
85 volatile uint8_t LFCGCTL;
86 volatile uint8_t reserved9;
87 /* 0x102: High-Frequency Reference Divisor I */
88 volatile uint16_t HFRDI;
89 /* 0x104: High-Frequency Reference Divisor F */
90 volatile uint16_t HFRDF;
91 /* 0x106: FRCLK Clock Divisor */
92 volatile uint16_t FRCDIV;
93 /* 0x108: Divisor Correction Value 1 */
94 volatile uint16_t DIVCOR1;
95 /* 0x10A: Divisor Correction Value 2 */
96 volatile uint16_t DIVCOR2;
97 volatile uint8_t reserved10[8];
98 /* 0x114: LFCG Control 2 */
99 volatile uint8_t LFCGCTL2;
100 volatile uint8_t reserved11;
101 };
102
103 /* CDCG register fields */
104 #define NPCX_HFCGCTRL_LOAD 0
105 #define NPCX_HFCGCTRL_LOCK 2
106 #define NPCX_HFCGCTRL_CLK_CHNG 7
107
108 #define NPCX_LFCGCTL2_XT_OSC_SL_EN 6
109
110 /*
111 * Power Management Controller (PMC) device registers
112 */
113 struct pmc_reg {
114 /* 0x000: Power Management Controller */
115 volatile uint8_t PMCSR;
116 volatile uint8_t reserved1[2];
117 /* 0x003: Enable in Sleep Control */
118 volatile uint8_t ENIDL_CTL;
119 /* 0x004: Disable in Idle Control */
120 volatile uint8_t DISIDL_CTL;
121 /* 0x005: Disable in Idle Control 1 */
122 volatile uint8_t DISIDL_CTL1;
123 volatile uint8_t reserved2[2];
124 /* 0x008 - 0D: Power-Down Control 1 - 6 */
125 volatile uint8_t PWDWN_CTL1[6];
126 volatile uint8_t reserved3[18];
127 /* 0x020 - 21: Power-Down Control 1 - 2 */
128 volatile uint8_t RAM_PD[2];
129 volatile uint8_t reserved4[2];
130 /* 0x024: Power-Down Control 7 */
131 volatile uint8_t PWDWN_CTL7[1];
132 };
133
134 /* PMC internal inline functions for multi-registers */
npcx_pwdwn_ctl_offset(uint32_t ctl_no)135 static inline uint32_t npcx_pwdwn_ctl_offset(uint32_t ctl_no)
136 {
137 if (ctl_no < 6) {
138 return 0x008 + ctl_no;
139 } else {
140 return 0x024 + ctl_no - 6;
141 }
142 }
143
144 /* Macro functions for PMC multi-registers */
145 #define NPCX_PWDWN_CTL(base, n) (*(volatile uint8_t *)(base + \
146 npcx_pwdwn_ctl_offset(n)))
147
148 /* PMC register fields */
149 #define NPCX_PMCSR_DI_INSTW 0
150 #define NPCX_PMCSR_DHF 1
151 #define NPCX_PMCSR_IDLE 2
152 #define NPCX_PMCSR_NWBI 3
153 #define NPCX_PMCSR_OHFC 6
154 #define NPCX_PMCSR_OLFC 7
155 #define NPCX_DISIDL_CTL_RAM_DID 5
156 #define NPCX_ENIDL_CTL_ADC_LFSL 7
157 #define NPCX_ENIDL_CTL_LP_WK_CTL 6
158 #define NPCX_ENIDL_CTL_PECI_ENI 2
159 #define NPCX_ENIDL_CTL_ADC_ACC_DIS 1
160
161 /* Macro functions for Development and Debugger Interface (DDI) registers */
162 #define NPCX_DBGCTRL(base) (*(volatile uint8_t *)(base + 0x004))
163 #define NPCX_DBGFRZEN1(base) (*(volatile uint8_t *)(base + 0x006))
164 #define NPCX_DBGFRZEN2(base) (*(volatile uint8_t *)(base + 0x007))
165 #define NPCX_DBGFRZEN3(base) (*(volatile uint8_t *)(base + 0x008))
166 #define NPCX_DBGFRZEN4(base) (*(volatile uint8_t *)(base + 0x009))
167
168 /* DDI register fields */
169 #define NPCX_DBGCTRL_CCDEV_SEL FIELD(6, 2)
170 #define NPCX_DBGCTRL_CCDEV_DIR 5
171 #define NPCX_DBGCTRL_SEQ_WK_EN 4
172 #define NPCX_DBGCTRL_FRCLK_SEL_DIS 3
173 #define NPCX_DBGFRZEN1_SPIFEN 7
174 #define NPCX_DBGFRZEN1_HIFEN 6
175 #define NPCX_DBGFRZEN1_ESPISEN 5
176 #define NPCX_DBGFRZEN1_UART1FEN 4
177 #define NPCX_DBGFRZEN1_SMB3FEN 3
178 #define NPCX_DBGFRZEN1_SMB2FEN 2
179 #define NPCX_DBGFRZEN1_MFT2FEN 1
180 #define NPCX_DBGFRZEN1_MFT1FEN 0
181 #define NPCX_DBGFRZEN2_ITIM6FEN 7
182 #define NPCX_DBGFRZEN2_ITIM5FEN 6
183 #define NPCX_DBGFRZEN2_ITIM4FEN 5
184 #define NPCX_DBGFRZEN2_ITIM64FEN 3
185 #define NPCX_DBGFRZEN2_SMB1FEN 2
186 #define NPCX_DBGFRZEN2_SMB0FEN 1
187 #define NPCX_DBGFRZEN2_MFT3FEN 0
188 #define NPCX_DBGFRZEN3_GLBL_FRZ_DIS 7
189 #define NPCX_DBGFRZEN3_ITIM3FEN 6
190 #define NPCX_DBGFRZEN3_ITIM2FEN 5
191 #define NPCX_DBGFRZEN3_ITIM1FEN 4
192 #define NPCX_DBGFRZEN3_I3CFEN 2
193 #define NPCX_DBGFRZEN3_SMB4FEN 1
194 #define NPCX_DBGFRZEN3_SHMFEN 0
195 #define NPCX_DBGFRZEN4_UART2FEN 6
196 #define NPCX_DBGFRZEN4_UART3FEN 5
197 #define NPCX_DBGFRZEN4_UART4FEN 4
198 #define NPCX_DBGFRZEN4_LCTFEN 3
199 #define NPCX_DBGFRZEN4_SMB7FEN 2
200 #define NPCX_DBGFRZEN4_SMB6FEN 1
201 #define NPCX_DBGFRZEN4_SMB5FEN 0
202
203 /*
204 * System Configuration (SCFG) device registers
205 */
206 struct scfg_reg {
207 /* 0x000: Device Control */
208 volatile uint8_t DEVCNT;
209 /* 0x001: Straps Status */
210 volatile uint8_t STRPST;
211 /* 0x002: Reset Control and Status */
212 volatile uint8_t RSTCTL;
213 volatile uint8_t reserved1[3];
214 /* 0x006: Device Control 4 */
215 volatile uint8_t DEV_CTL4;
216 volatile uint8_t reserved2[9];
217 /* 0x010 - 1F: Device Alternate Function 0 - F */
218 volatile uint8_t DEVALT0[16];
219 volatile uint8_t reserved3[6];
220 /* 0x026: Low-Voltage GPIO Pins Control 5 */
221 volatile uint8_t LV_GPIO_CTL5[1];
222 volatile uint8_t reserved4;
223 /* 0x028: Pull-Up/Pull-Down Enable 0 */
224 volatile uint8_t PUPD_EN0;
225 /* 0x029: Pull-Up/Pull-Down Enable 1 */
226 volatile uint8_t PUPD_EN1;
227 /* 0x02A - 2E: Low-Voltage GPIO Pins Control 0 - 4 */
228 volatile uint8_t LV_GPIO_CTL0[5];
229 };
230
231 /* Macro functions for SCFG multi-registers */
232 #define NPCX_DEV_CTL(base, n) \
233 (*(volatile uint8_t *)(base + n))
234 #define NPCX_DEVALT(base, n) \
235 (*(volatile uint8_t *)(base + NPCX_DEVALT_OFFSET(n)))
236 #define NPCX_DEVALT_LK(base, n) \
237 (*(volatile uint8_t *)(base + NPCX_DEVALT_LK_OFFSET(n)))
238 #define NPCX_PUPD_EN(base, n) \
239 (*(volatile uint8_t *)(base + NPCX_PUPD_EN_OFFSET(n)))
240 #define NPCX_LV_GPIO_CTL(base, n) \
241 (*(volatile uint8_t *)(base + NPCX_LV_GPIO_CTL_OFFSET(n)))
242
243 /* SCFG register fields */
244 #define NPCX_DEVCNT_F_SPI_TRIS 6
245 #define NPCX_DEVCNT_HIF_TYP_SEL_FIELD FIELD(2, 2)
246 #define NPCX_DEVCNT_JEN1_HEN 5
247 #define NPCX_DEVCNT_JEN0_HEN 4
248 #define NPCX_STRPST_TRIST 1
249 #define NPCX_STRPST_TEST 2
250 #define NPCX_STRPST_JEN1 4
251 #define NPCX_STRPST_JEN0 5
252 #define NPCX_STRPST_SPI_COMP 7
253 #define NPCX_RSTCTL_VCC1_RST_STS 0
254 #define NPCX_RSTCTL_DBGRST_STS 1
255 #define NPCX_RSTCTL_VCC1_RST_SCRATCH 3
256 #define NPCX_RSTCTL_LRESET_PLTRST_MODE 5
257 #define NPCX_RSTCTL_HIPRST_MODE 6
258 #define NPCX_DEV_CTL4_F_SPI_SLLK 2
259 #define NPCX_DEV_CTL4_SPI_SP_SEL 4
260 #define NPCX_DEV_CTL4_WP_IF 5
261 #define NPCX_DEV_CTL4_VCC1_RST_LK 6
262 #define NPCX_DEVPU0_I2C0_0_PUE 0
263 #define NPCX_DEVPU0_I2C0_1_PUE 1
264 #define NPCX_DEVPU0_I2C1_0_PUE 2
265 #define NPCX_DEVPU0_I2C2_0_PUE 4
266 #define NPCX_DEVPU0_I2C3_0_PUE 6
267 #define NPCX_DEVPU1_F_SPI_PUD_EN 7
268
269 /* Supported host interface type for HIF_TYP_SEL FILED in DEVCNT register. */
270 enum npcx_hif_type {
271 NPCX_HIF_TYPE_NONE,
272 NPCX_HIF_TYPE_LPC,
273 NPCX_HIF_TYPE_ESPI_SHI,
274 };
275
276 /*
277 * System Glue (GLUE) device registers
278 */
279 struct glue_reg {
280 volatile uint8_t reserved1[2];
281 /* 0x002: SMBus Start Bit Detection */
282 volatile uint8_t SMB_SBD;
283 /* 0x003: SMBus Event Enable */
284 volatile uint8_t SMB_EEN;
285 volatile uint8_t reserved2[12];
286 /* 0x010: Simple Debug Port Data 0 */
287 volatile uint8_t SDPD0;
288 volatile uint8_t reserved3;
289 /* 0x012: Simple Debug Port Data 1 */
290 volatile uint8_t SDPD1;
291 volatile uint8_t reserved4;
292 /* 0x014: Simple Debug Port Control and Status */
293 volatile uint8_t SDP_CTS;
294 volatile uint8_t reserved5[12];
295 /* 0x021: SMBus Bus Select */
296 volatile uint8_t SMB_SEL;
297 volatile uint8_t reserved6[5];
298 /* 0x027: PSL Control and Status */
299 volatile uint8_t PSL_CTS;
300 };
301
302 /* GLUE register fields */
303 /* PSL input detection mode is configured by bits 7:4 of PSL_CTS */
304 #define NPCX_PSL_CTS_MODE_BIT(bit) BIT(bit + 4)
305 /* PSL input assertion events are reported by bits 3:0 of PSL_CTS */
306 #define NPCX_PSL_CTS_EVENT_BIT(bit) BIT(bit)
307
308 /*
309 * Universal Asynchronous Receiver-Transmitter (UART) device registers
310 */
311 struct uart_reg {
312 /* 0x000: Transmit Data Buffer */
313 volatile uint8_t UTBUF;
314 volatile uint8_t reserved1;
315 /* 0x002: Receive Data Buffer */
316 volatile uint8_t URBUF;
317 volatile uint8_t reserved2;
318 /* 0x004: Interrupt Control */
319 volatile uint8_t UICTRL;
320 volatile uint8_t reserved3;
321 /* 0x006: Status */
322 volatile uint8_t USTAT;
323 volatile uint8_t reserved4;
324 /* 0x008: Frame Select */
325 volatile uint8_t UFRS;
326 volatile uint8_t reserved5;
327 /* 0x00A: Mode Select */
328 volatile uint8_t UMDSL;
329 volatile uint8_t reserved6;
330 /* 0x00C: Baud Rate Divisor */
331 volatile uint8_t UBAUD;
332 volatile uint8_t reserved7;
333 /* 0x00E: Baud Rate Prescaler */
334 volatile uint8_t UPSR;
335 volatile uint8_t reserved8[17];
336 /* 0x020: FIFO Mode Transmit Status */
337 volatile uint8_t UFTSTS;
338 volatile uint8_t reserved9;
339 /* 0x022: FIFO Mode Receive Status */
340 volatile uint8_t UFRSTS;
341 volatile uint8_t reserved10;
342 /* 0x024: FIFO Mode Transmit Control */
343 volatile uint8_t UFTCTL;
344 volatile uint8_t reserved11;
345 /* 0x026: FIFO Mode Receive Control */
346 volatile uint8_t UFRCTL;
347 };
348
349 /* UART register fields */
350 #define NPCX_UICTRL_TBE 0
351 #define NPCX_UICTRL_RBF 1
352 #define NPCX_UICTRL_ETI 5
353 #define NPCX_UICTRL_ERI 6
354 #define NPCX_UICTRL_EEI 7
355 #define NPCX_USTAT_PE 0
356 #define NPCX_USTAT_FE 1
357 #define NPCX_USTAT_DOE 2
358 #define NPCX_USTAT_ERR 3
359 #define NPCX_USTAT_BKD 4
360 #define NPCX_USTAT_RB9 5
361 #define NPCX_USTAT_XMIP 6
362 #define NPCX_UFRS_CHAR_FIELD FIELD(0, 2)
363 #define NPCX_UFRS_STP 2
364 #define NPCX_UFRS_XB9 3
365 #define NPCX_UFRS_PSEL_FIELD FIELD(4, 2)
366 #define NPCX_UFRS_PEN 6
367 #define NPCX_UMDSL_FIFO_MD 0
368 #define NPCX_UFTSTS_TEMPTY_LVL FIELD(0, 5)
369 #define NPCX_UFTSTS_TEMPTY_LVL_STS 5
370 #define NPCX_UFTSTS_TFIFO_EMPTY_STS 6
371 #define NPCX_UFTSTS_NXMIP 7
372 #define NPCX_UFRSTS_RFULL_LVL_STS 5
373 #define NPCX_UFRSTS_RFIFO_NEMPTY_STS 6
374 #define NPCX_UFRSTS_ERR 7
375 #define NPCX_UFTCTL_TEMPTY_LVL_SEL FIELD(0, 5)
376 #define NPCX_UFTCTL_TEMPTY_LVL_EN 5
377 #define NPCX_UFTCTL_TEMPTY_EN 6
378 #define NPCX_UFTCTL_NXMIP_EN 7
379 #define NPCX_UFRCTL_RFULL_LVL_SEL FIELD(0, 5)
380 #define NPCX_UFRCTL_RFULL_LVL_EN 5
381 #define NPCX_UFRCTL_RNEMPTY_EN 6
382 #define NPCX_UFRCTL_ERR_EN 7
383
384 /* Macro functions for MIWU multi-registers */
385 #define NPCX_WKEDG(base, group) \
386 (*(volatile uint8_t *)(base + NPCX_WKEDG_OFFSET(group)))
387 #define NPCX_WKAEDG(base, group) \
388 (*(volatile uint8_t *)(base + NPCX_WKAEDG_OFFSET(group)))
389 #define NPCX_WKPND(base, group) \
390 (*(volatile uint8_t *)(base + NPCX_WKPND_OFFSET(group)))
391 #define NPCX_WKPCL(base, group) \
392 (*(volatile uint8_t *)(base + NPCX_WKPCL_OFFSET(group)))
393 #define NPCX_WKEN(base, group) \
394 (*(volatile uint8_t *)(base + NPCX_WKEN_OFFSET(group)))
395 #define NPCX_WKINEN(base, group) \
396 (*(volatile uint8_t *)(base + NPCX_WKINEN_OFFSET(group)))
397 #define NPCX_WKMOD(base, group) \
398 (*(volatile uint8_t *)(base + NPCX_WKMOD_OFFSET(group)))
399
400 /*
401 * General-Purpose I/O (GPIO) device registers
402 */
403 struct gpio_reg {
404 /* 0x000: Port GPIOx Data Out */
405 volatile uint8_t PDOUT;
406 /* 0x001: Port GPIOx Data In */
407 volatile uint8_t PDIN;
408 /* 0x002: Port GPIOx Direction */
409 volatile uint8_t PDIR;
410 /* 0x003: Port GPIOx Pull-Up or Pull-Down Enable */
411 volatile uint8_t PPULL;
412 /* 0x004: Port GPIOx Pull-Up/Down Selection */
413 volatile uint8_t PPUD;
414 /* 0x005: Port GPIOx Drive Enable by VDD Present */
415 volatile uint8_t PENVDD;
416 /* 0x006: Port GPIOx Output Type */
417 volatile uint8_t PTYPE;
418 /* 0x007: Port GPIOx Lock Control */
419 volatile uint8_t PLOCK_CTL;
420 };
421
422 /*
423 * Pulse Width Modulator (PWM) device registers
424 */
425 struct pwm_reg {
426 /* 0x000: Clock Prescaler */
427 volatile uint16_t PRSC;
428 /* 0x002: Cycle Time */
429 volatile uint16_t CTR;
430 /* 0x004: PWM Control */
431 volatile uint8_t PWMCTL;
432 volatile uint8_t reserved1;
433 /* 0x006: Duty Cycle */
434 volatile uint16_t DCR;
435 volatile uint8_t reserved2[4];
436 /* 0x00C: PWM Control Extended */
437 volatile uint8_t PWMCTLEX;
438 volatile uint8_t reserved3;
439 };
440
441 /* PWM register fields */
442 #define NPCX_PWMCTL_INVP 0
443 #define NPCX_PWMCTL_CKSEL 1
444 #define NPCX_PWMCTL_HB_DC_CTL_FIELD FIELD(2, 2)
445 #define NPCX_PWMCTL_PWR 7
446 #define NPCX_PWMCTLEX_FCK_SEL_FIELD FIELD(4, 2)
447 #define NPCX_PWMCTLEX_OD_OUT 7
448
449 /*
450 * Analog-To-Digital Converter (ADC) device registers
451 */
452 struct adc_reg {
453 /* 0x000: ADC Status */
454 volatile uint16_t ADCSTS;
455 /* 0x002: ADC Configuration */
456 volatile uint16_t ADCCNF;
457 /* 0x004: ADC Timing Control */
458 volatile uint16_t ATCTL;
459 /* 0x006: ADC Single Channel Address */
460 volatile uint16_t ASCADD;
461 /* 0x008: ADC Scan Channels Select */
462 volatile uint16_t ADCCS;
463 /* 0x00A: ADC Scan Channels Select 2 */
464 volatile uint16_t ADCCS2;
465 volatile uint8_t reserved1[14];
466 /* 0x01A: Threshold Status */
467 volatile uint16_t THRCTS;
468 volatile uint8_t reserved2[4];
469 /* 0x020: Internal register 1 for ADC Speed */
470 volatile uint16_t ADCCNF2;
471 /* 0x022: Internal register 2 for ADC Speed */
472 volatile uint16_t GENDLY;
473 volatile uint8_t reserved3[2];
474 /* 0x026: Internal register 3 for ADC Speed */
475 volatile uint16_t MEAST;
476 };
477
478 /* ADC internal inline functions for multi-registers */
479 #define CHNDAT(base, ch) \
480 (*(volatile uint16_t *)((base) + NPCX_CHNDAT_OFFSET(ch)))
481 #define THRCTL(base, ctrl) \
482 (*(volatile uint16_t *)(base + NPCX_THRCTL_OFFSET(ctrl)))
483
484 /* ADC register fields */
485 #define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6)
486 #define NPCX_ATCTL_DLY_FIELD FIELD(8, 3)
487 #define NPCX_ASCADD_SADDR_FIELD FIELD(0, 5)
488 #define NPCX_ADCSTS_EOCEV 0
489 #define NPCX_ADCSTS_EOCCEV 1
490 #define NPCX_ADCCNF_ADCEN 0
491 #define NPCX_ADCCNF_ADCMD_FIELD FIELD(1, 2)
492 #define NPCX_ADCCNF_ADCRPTC 3
493 #define NPCX_ADCCNF_START 4
494 #define NPCX_ADCCNF_ADCTTE 5
495 #define NPCX_ADCCNF_INTECEN 6
496 #define NPCX_ADCCNF_INTECCEN 7
497 #define NPCX_ADCCNF_INTETCEN 8
498 #define NPCX_ADCCNF_INTOVFEN 9
499 #define NPCX_ADCCNF_STOP 11
500 #define NPCX_CHNDAT_CHDAT_FIELD FIELD(0, 10)
501 #define NPCX_CHNDAT_NEW 15
502 #define NPCX_THRCTS_ADC_WKEN 15
503 #define NPCX_THRCTS_THR3_IEN 10
504 #define NPCX_THRCTS_THR2_IEN 9
505 #define NPCX_THRCTS_THR1_IEN 8
506 #define NPCX_THRCTS_ADC_EVENT 7
507 #define NPCX_THRCTS_THR3_STS 2
508 #define NPCX_THRCTS_THR2_STS 1
509 #define NPCX_THRCTS_THR1_STS 0
510 #define NPCX_THR_DCTL_THRD_EN 15
511 #define NPCX_THR_DCTL_THR_DVAL FIELD(0, 10)
512
513 /*
514 * Timer Watchdog (TWD) device registers
515 */
516 struct twd_reg {
517 /* 0x000: Timer and Watchdog Configuration */
518 volatile uint8_t TWCFG;
519 volatile uint8_t reserved1;
520 /* 0x002: Timer and Watchdog Clock Prescaler */
521 volatile uint8_t TWCP;
522 volatile uint8_t reserved2;
523 /* 0x004: TWD Timer 0 */
524 volatile uint16_t TWDT0;
525 /* 0x006: TWDT0 Control and Status */
526 volatile uint8_t T0CSR;
527 volatile uint8_t reserved3;
528 /* 0x008: Watchdog Count */
529 volatile uint8_t WDCNT;
530 volatile uint8_t reserved4;
531 /* 0x00A: Watchdog Service Data Match */
532 volatile uint8_t WDSDM;
533 volatile uint8_t reserved5;
534 /* 0x00C: TWD Timer 0 Counter */
535 volatile uint16_t TWMT0;
536 /* 0x00E: Watchdog Counter */
537 volatile uint8_t TWMWD;
538 volatile uint8_t reserved6;
539 /* 0x010: Watchdog Clock Prescaler */
540 volatile uint8_t WDCP;
541 volatile uint8_t reserved7;
542 };
543
544 /* TWD register fields */
545 #define NPCX_TWCFG_LTWCFG 0
546 #define NPCX_TWCFG_LTWCP 1
547 #define NPCX_TWCFG_LTWDT0 2
548 #define NPCX_TWCFG_LWDCNT 3
549 #define NPCX_TWCFG_WDCT0I 4
550 #define NPCX_TWCFG_WDSDME 5
551 #define NPCX_T0CSR_RST 0
552 #define NPCX_T0CSR_TC 1
553 #define NPCX_T0CSR_WDLTD 3
554 #define NPCX_T0CSR_WDRST_STS 4
555 #define NPCX_T0CSR_WD_RUN 5
556 #define NPCX_T0CSR_TESDIS 7
557
558 /*
559 * Enhanced Serial Peripheral Interface (eSPI) device registers
560 */
561 struct espi_reg {
562 /* 0x000: eSPI Identification */
563 volatile uint32_t ESPIID;
564 /* 0x004: eSPI Configuration */
565 volatile uint32_t ESPICFG;
566 /* 0x008: eSPI Status */
567 volatile uint32_t ESPISTS;
568 /* 0x00C: eSPI Interrupt Enable */
569 volatile uint32_t ESPIIE;
570 /* 0x010: eSPI Wake-Up Enable */
571 volatile uint32_t ESPIWE;
572 /* 0x014: Virtual Wire Register Index */
573 volatile uint32_t VWREGIDX;
574 /* 0x018: Virtual Wire Register Data */
575 volatile uint32_t VWREGDATA;
576 /* 0x01C: OOB Receive Buffer Read Head */
577 volatile uint32_t OOBRXRDHEAD;
578 /* 0x020: OOB Transmit Buffer Write Head */
579 volatile uint32_t OOBTXWRHEAD;
580 /* 0x024: OOB Channel Control */
581 volatile uint32_t OOBCTL;
582 /* 0x028: Flash Receive Buffer Read Head */
583 volatile uint32_t FLASHRXRDHEAD;
584 /* 0x02C: Flash Transmit Buffer Write Head */
585 volatile uint32_t FLASHTXWRHEAD;
586 volatile uint32_t reserved1;
587 /* 0x034: Flash Channel Configuration */
588 volatile uint32_t FLASHCFG;
589 /* 0x038: Flash Channel Control */
590 volatile uint32_t FLASHCTL;
591 /* 0x03C: eSPI Error Status */
592 volatile uint32_t ESPIERR;
593 /* 0x040: Peripheral Bus Master Receive Buffer Read Head */
594 volatile uint32_t PBMRXRDHEAD;
595 /* 0x044: Peripheral Bus Master Transmit Buffer Write Head */
596 volatile uint32_t PBMTXWRHEAD;
597 /* 0x048: Peripheral Channel Configuration */
598 volatile uint32_t PERCFG;
599 /* 0x04C: Peripheral Channel Control */
600 volatile uint32_t PERCTL;
601 /* 0x050: Status Image Register */
602 volatile uint16_t STATUS_IMG;
603 volatile uint16_t reserved2[79];
604 /* 0x0F0: NPCX specific eSPI Register1 */
605 volatile uint8_t NPCX_ONLY_ESPI_REG1;
606 /* 0x0F1: NPCX specific eSPI Register2 */
607 volatile uint8_t NPCX_ONLY_ESPI_REG2;
608 volatile uint16_t reserved3[7];
609 /* 0x100 - 127: Virtual Wire Event Slave-to-Master 0 - 9 */
610 volatile uint32_t VWEVSM[10];
611 volatile uint32_t reserved4[6];
612 /* 0x140 - 16F: Virtual Wire Event Master-to-Slave 0 - 11 */
613 volatile uint32_t VWEVMS[12];
614 volatile uint32_t reserved5[4];
615 /* 0x180 - 1BF: Virtual Wire GPIO Event Master-to-Slave 0 - 15 */
616 volatile uint32_t VWGPSM[16];
617 volatile uint32_t reserved6[79];
618 /* 0x2FC: Virtual Wire Channel Control */
619 volatile uint32_t VWCTL;
620 /* 0x300 - 34F: OOB Receive Buffer 0 - 19 */
621 volatile uint32_t OOBRXBUF[20];
622 volatile uint32_t reserved7[12];
623 /* 0x380 - 3CF: OOB Transmit Buffer 0-19 */
624 volatile uint32_t OOBTXBUF[20];
625 volatile uint32_t reserved8[11];
626 /* 0x3FC: OOB Channel Control used in 'direct' mode */
627 volatile uint32_t OOBCTL_DIRECT;
628 /* 0x400 - 443: Flash Receive Buffer 0-17 */
629 volatile uint32_t FLASHRXBUF[18];
630 volatile uint32_t reserved9[14];
631 /* 0x480 - 497: Flash Transmit Buffer 0-16 */
632 volatile uint32_t FLASHTXBUF[17];
633 volatile uint32_t reserved10[14];
634 /* 0x4FC: Flash Channel Control used in 'direct' mode */
635 volatile uint32_t FLASHCTL_DIRECT;
636 volatile uint32_t reserved12[64];
637 /* 0x600 - 63F */
638 volatile uint32_t FLASH_PRTR_BADDR[16];
639 /* 0x640 - 67F */
640 volatile uint32_t FLASH_PRTR_HADDR[16];
641 /* 0x680 - 6BF */
642 volatile uint32_t FLASH_RGN_TAG_OVR[16];
643 volatile uint32_t reserved13[80];
644 /* 0x800 */
645 volatile uint32_t FLASH_RPMC_CFG_1;
646 /* 0x804 */
647 volatile uint32_t FLASH_RPMC_CFG_2;
648 /* 0x808 */
649 volatile uint32_t RMAP_FLASH_OFFS;
650 /* 0x80C */
651 volatile uint32_t RMAP_DST_BASE;
652 /* 0x810 */
653 volatile uint32_t RMAP_WIN_SIZE;
654 /* 0x814 */
655 volatile uint32_t FLASHBASE;
656 volatile uint32_t reserved14[58];
657 };
658
659 /* eSPI register fields */
660 #define NPCX_ESPICFG_PCHANEN 0
661 #define NPCX_ESPICFG_VWCHANEN 1
662 #define NPCX_ESPICFG_OOBCHANEN 2
663 #define NPCX_ESPICFG_FLASHCHANEN 3
664 #define NPCX_ESPICFG_HPCHANEN 4
665 #define NPCX_ESPICFG_HVWCHANEN 5
666 #define NPCX_ESPICFG_HOOBCHANEN 6
667 #define NPCX_ESPICFG_HFLASHCHANEN 7
668 #define NPCX_ESPICFG_CHANS_FIELD FIELD(0, 4)
669 #define NPCX_ESPICFG_HCHANS_FIELD FIELD(4, 4)
670 #define NPCX_ESPICFG_IOMODE_FIELD FIELD(8, 2)
671 #define NPCX_ESPICFG_MAXFREQ_FIELD FIELD(10, 3)
672 #define NPCX_ESPICFG_FLCHANMODE 16
673 #define NPCX_ESPICFG_PCCHN_SUPP 24
674 #define NPCX_ESPICFG_VWCHN_SUPP 25
675 #define NPCX_ESPICFG_OOBCHN_SUPP 26
676 #define NPCX_ESPICFG_FLASHCHN_SUPP 27
677 #define NPCX_ESPIIE_IBRSTIE 0
678 #define NPCX_ESPIIE_CFGUPDIE 1
679 #define NPCX_ESPIIE_BERRIE 2
680 #define NPCX_ESPIIE_OOBRXIE 3
681 #define NPCX_ESPIIE_FLASHRXIE 4
682 #define NPCX_ESPIIE_FLNACSIE 5
683 #define NPCX_ESPIIE_PERACCIE 6
684 #define NPCX_ESPIIE_DFRDIE 7
685 #define NPCX_ESPIIE_VWUPDIE 8
686 #define NPCX_ESPIIE_ESPIRSTIE 9
687 #define NPCX_ESPIIE_PLTRSTIE 10
688 #define NPCX_ESPIIE_AMERRIE 15
689 #define NPCX_ESPIIE_AMDONEIE 16
690 #define NPCX_ESPIIE_BMTXDONEIE 19
691 #define NPCX_ESPIIE_PBMRXIE 20
692 #define NPCX_ESPIIE_PMSGRXIE 21
693 #define NPCX_ESPIIE_BMBURSTERRIE 22
694 #define NPCX_ESPIIE_BMBURSTDONEIE 23
695 #define NPCX_ESPIWE_IBRSTWE 0
696 #define NPCX_ESPIWE_CFGUPDWE 1
697 #define NPCX_ESPIWE_BERRWE 2
698 #define NPCX_ESPIWE_OOBRXWE 3
699 #define NPCX_ESPIWE_FLASHRXWE 4
700 #define NPCX_ESPIWE_FLNACSWE 5
701 #define NPCX_ESPIWE_PERACCWE 6
702 #define NPCX_ESPIWE_DFRDWE 7
703 #define NPCX_ESPIWE_VWUPDWE 8
704 #define NPCX_ESPIWE_ESPIRSTWE 9
705 #define NPCX_ESPIWE_PBMRXWE 20
706 #define NPCX_ESPIWE_PMSGRXWE 21
707 #define NPCX_ESPISTS_IBRST 0
708 #define NPCX_ESPISTS_CFGUPD 1
709 #define NPCX_ESPISTS_BERR 2
710 #define NPCX_ESPISTS_OOBRX 3
711 #define NPCX_ESPISTS_FLASHRX 4
712 #define NPCX_ESPISTS_FLNACS 5
713 #define NPCX_ESPISTS_PERACC 6
714 #define NPCX_ESPISTS_DFRD 7
715 #define NPCX_ESPISTS_VWUPD 8
716 #define NPCX_ESPISTS_ESPIRST 9
717 #define NPCX_ESPISTS_PLTRST 10
718 #define NPCX_ESPISTS_AMERR 15
719 #define NPCX_ESPISTS_AMDONE 16
720 #define NPCX_ESPISTS_VWUPDW 17
721 #define NPCX_ESPISTS_BMTXDONE 19
722 #define NPCX_ESPISTS_PBMRX 20
723 #define NPCX_ESPISTS_PMSGRX 21
724 #define NPCX_ESPISTS_BMBURSTERR 22
725 #define NPCX_ESPISTS_BMBURSTDONE 23
726 #define NPCX_ESPISTS_ESPIRST_LVL 24
727 #define NPCX_VWSWIRQ_IRQ_NUM FIELD(0, 7)
728 #define NPCX_VWSWIRQ_IRQ_LVL 7
729 #define NPCX_VWSWIRQ_INDEX FIELD(8, 7)
730 #define NPCX_VWSWIRQ_INDEX_EN 15
731 #define NPCX_VWSWIRQ_DIRTY 16
732 #define NPCX_VWSWIRQ_ENPLTRST 17
733 #define NPCX_VWSWIRQ_ENCDRST 19
734 #define NPCX_VWSWIRQ_EDGE_IRQ 28
735 #define NPCX_VWEVMS_WIRE FIELD(0, 4)
736 #define NPCX_VWEVMS_VALID FIELD(4, 4)
737 #define NPCX_VWEVMS_IE 18
738 #define NPCX_VWEVMS_WE 20
739 #define NPCX_VWEVSM_WIRE FIELD(0, 4)
740 #define NPCX_VWEVSM_VALID FIELD(4, 4)
741 #define NPCX_VWEVSM_BIT_VALID(n) (4+n)
742 #define NPCX_VWEVSM_HW_WIRE FIELD(24, 4)
743 #define NPCX_VWGPSM_INDEX_EN 15
744 #define NPCX_OOBCTL_OOB_FREE 0
745 #define NPCX_OOBCTL_OOB_AVAIL 1
746 #define NPCX_OOBCTL_RSTBUFHEADS 2
747 #define NPCX_OOBCTL_OOBPLSIZE FIELD(10, 3)
748 #define NPCX_FLASHCFG_FLASHBLERSSIZE FIELD(7, 3)
749 #define NPCX_FLASHCFG_FLASHPLSIZE FIELD(10, 3)
750 #define NPCX_FLASHCFG_FLASHREQSIZE FIELD(13, 3)
751 #define NPCX_FLASHCFG_FLCAPA FIELD(24, 2)
752 #define NPCX_FLASHCFG_TRGFLEBLKSIZE FIELD(16, 8)
753 #define NPCX_FLASHCFG_FLREQSUP FIELD(0, 3)
754 #define NPCX_FLASHCTL_FLASH_NP_FREE 0
755 #define NPCX_FLASHCTL_FLASH_TX_AVAIL 1
756 #define NPCX_FLASHCTL_STRPHDR 2
757 #define NPCX_FLASHCTL_DMATHRESH FIELD(3, 2)
758 #define NPCX_FLASHCTL_AMTSIZE FIELD(5, 8)
759 #define NPCX_FLASHCTL_RSTBUFHEADS 13
760 #define NPCX_FLASHCTL_CRCEN 14
761 #define NPCX_FLASHCTL_CHKSUMSEL 15
762 #define NPCX_FLASHCTL_AMTEN 16
763 #define NPCX_FLASHCTL_SAF_AUTO_READ 18
764 #define NPCX_FLASHCTL_AUTO_RD_DIS_CTL 19
765 #define NPCX_FLASHCTL_BLK_FLASH_NP_FREE 20
766 #define NPCX_FLASHBASE_FLBASE_ADDR FIELD(12, 15)
767 #define NPCX_FLASH_PRTR_BADDR FIELD(12, 15)
768 #define NPCX_FRGN_WPR 29
769 #define SAF_PROT_LCK 31
770 #define NPCX_FRGN_RPR 30
771 #define NPCX_FLASH_PRTR_HADDR FIELD(12, 15)
772 #define NPCX_FLASH_TAG_OVR_RPR FIELD(16, 16)
773 #define NPCX_FLASH_TAG_OVR_WPR FIELD(0, 16)
774 #define NPCX_ONLY_ESPI_REG1_UNLOCK_REG2 0x55
775 #define NPCX_ONLY_ESPI_REG1_LOCK_REG2 0
776 #define NPCX_ONLY_ESPI_REG2_TRANS_END_CONFIG 4
777
778 /*
779 * Mobile System Wake-Up Control (MSWC) device registers
780 */
781 struct mswc_reg {
782 /* 0x000: MSWC Control Status 1 */
783 volatile uint8_t MSWCTL1;
784 volatile uint8_t reserved1;
785 /* 0x002: MSWC Control Status 2 */
786 volatile uint8_t MSWCTL2;
787 volatile uint8_t reserved2[5];
788 /* 0x008: Host Configuration Base Address Low */
789 volatile uint8_t HCBAL;
790 volatile uint8_t reserved3;
791 /* 0x00A: Host Configuration Base Address High */
792 volatile uint8_t HCBAH;
793 volatile uint8_t reserved4;
794 /* 0X00C: MSWC INTERRUPT ENABLE 2 */
795 volatile uint8_t MSIEN2;
796 volatile uint8_t reserved5;
797 /* 0x00E: MSWC Host Event Status 0 */
798 volatile uint8_t MSHES0;
799 volatile uint8_t reserved6;
800 /* 0x010: MSWC Host Event Interrupt Enable */
801 volatile uint8_t MSHEIE0;
802 volatile uint8_t reserved7;
803 /* 0x012: Host Control */
804 volatile uint8_t HOST_CTL;
805 volatile uint8_t reserved8;
806 /* 0x014: SMI Pulse Length */
807 volatile uint8_t SMIP_LEN;
808 volatile uint8_t reserved9;
809 /* 0x016: SCI Pulse Length */
810 volatile uint8_t SCIP_LEN;
811 volatile uint8_t reserved10[5];
812 /* 0x01C: SRID Core Access */
813 volatile uint8_t SRID_CR;
814 volatile uint8_t reserved11[3];
815 /* 0x020: SID Core Access */
816 volatile uint8_t SID_CR;
817 volatile uint8_t reserved12;
818 /* 0x022: DEVICE_ID Core Access */
819 volatile uint8_t DEVICE_ID_CR;
820 volatile uint8_t reserved13[5];
821 /* 0x028: Chip Revision Core Access */
822 volatile uint8_t CHPREV_CR;
823 volatile uint8_t reserved14[5];
824 /* 0x02E: Virtual Wire Sleep States */
825 volatile uint8_t VW_SLPST1;
826 volatile uint8_t reserved15;
827 };
828
829 /* MSWC register fields */
830 #define NPCX_MSWCTL1_HRSTOB 0
831 #define NPCS_MSWCTL1_HWPRON 1
832 #define NPCX_MSWCTL1_PLTRST_ACT 2
833 #define NPCX_MSWCTL1_VHCFGA 3
834 #define NPCX_MSWCTL1_HCFGLK 4
835 #define NPCX_MSWCTL1_PWROFFB 6
836 #define NPCX_MSWCTL1_A20MB 7
837
838 /*
839 * Shared Memory (SHM) device registers
840 */
841 struct shm_reg {
842 /* 0x000: Shared Memory Core Status */
843 volatile uint8_t SMC_STS;
844 /* 0x001: Shared Memory Core Control */
845 volatile uint8_t SMC_CTL;
846 /* 0x002: Shared Memory Host Control */
847 volatile uint8_t SHM_CTL;
848 volatile uint8_t reserved1[2];
849 /* 0x005: Indirect Memory Access Window Size */
850 volatile uint8_t IMA_WIN_SIZE;
851 volatile uint8_t reserved2;
852 /* 0x007: Shared Access Windows Size */
853 volatile uint8_t WIN_SIZE;
854 /* 0x008: Shared Access Window 1, Semaphore */
855 volatile uint8_t SHAW1_SEM;
856 /* 0x009: Shared Access Window 2, Semaphore */
857 volatile uint8_t SHAW2_SEM;
858 volatile uint8_t reserved3;
859 /* 0x00B: Indirect Memory Access, Semaphore */
860 volatile uint8_t IMA_SEM;
861 volatile uint8_t reserved4[2];
862 /* 0x00E: Shared Memory Configuration */
863 volatile uint16_t SHCFG;
864 /* 0x010: Shared Access Window 1 Write Protect */
865 volatile uint8_t WIN1_WR_PROT;
866 /* 0x011: Shared Access Window 1 Read Protect */
867 volatile uint8_t WIN1_RD_PROT;
868 /* 0x012: Shared Access Window 2 Write Protect */
869 volatile uint8_t WIN2_WR_PROT;
870 /* 0x013: Shared Access Window 2 Read Protect */
871 volatile uint8_t WIN2_RD_PROT;
872 volatile uint8_t reserved5[2];
873 /* 0x016: Indirect Memory Access Write Protect */
874 volatile uint8_t IMA_WR_PROT;
875 /* 0x017: Indirect Memory Access Read Protect */
876 volatile uint8_t IMA_RD_PROT;
877 volatile uint8_t reserved6[8];
878 /* 0x020: Shared Access Window 1 Base */
879 volatile uint32_t WIN_BASE1;
880 /* 0x024: Shared Access Window 2 Base */
881 volatile uint32_t WIN_BASE2;
882 volatile uint32_t reserved7;
883 /* 0x02C: Indirect Memory Access Base */
884 volatile uint32_t IMA_BASE;
885 volatile uint8_t reserved8[10];
886 /* 0x03A: Reset Configuration */
887 volatile uint8_t RST_CFG;
888 volatile uint8_t reserved9[5];
889 /* 0x040: Debug Port 80 Buffered Data */
890 volatile uint16_t DP80BUF;
891 /* 0x042: Debug Port 80 Status */
892 volatile uint8_t DP80STS;
893 volatile uint8_t reserved10;
894 /* 0x044: Debug Port 80 Control */
895 volatile uint8_t DP80CTL;
896 volatile uint8_t reserved11[3];
897 /* 0x048: Host_Offset in Windows 1, 2 Status */
898 volatile uint8_t HOFS_STS;
899 /* 0x049: Host_Offset in Windows 1, 2 Control */
900 volatile uint8_t HOFS_CTL;
901 /* 0x04A: Core_Offset in Window 2 Address */
902 volatile uint16_t COFS2;
903 /* 0x04C: Core_Offset in Window 1 Address */
904 volatile uint16_t COFS1;
905 volatile uint16_t reserved12;
906 };
907
908 /* SHM register fields */
909 #define NPCX_SMC_STS_HRERR 0
910 #define NPCX_SMC_STS_HWERR 1
911 #define NPCX_SMC_STS_HSEM1W 4
912 #define NPCX_SMC_STS_HSEM2W 5
913 #define NPCX_SMC_STS_SHM_ACC 6
914 #define NPCX_SMC_CTL_HERR_IE 2
915 #define NPCX_SMC_CTL_HSEM1_IE 3
916 #define NPCX_SMC_CTL_HSEM2_IE 4
917 #define NPCX_SMC_CTL_ACC_IE 5
918 #define NPCX_SMC_CTL_PREF_EN 6
919 #define NPCX_SMC_CTL_HOSTWAIT 7
920 #define NPCX_FLASH_SIZE_STALL_HOST 6
921 #define NPCX_FLASH_SIZE_RD_BURST 7
922 #define NPCX_WIN_SIZE_RWIN1_SIZE_FIELD FIELD(0, 4)
923 #define NPCX_WIN_SIZE_RWIN2_SIZE_FIELD FIELD(4, 4)
924 #define NPCX_WIN_PROT_RW1L_RP 0
925 #define NPCX_WIN_PROT_RW1L_WP 1
926 #define NPCX_WIN_PROT_RW1H_RP 2
927 #define NPCX_WIN_PROT_RW1H_WP 3
928 #define NPCX_WIN_PROT_RW2L_RP 4
929 #define NPCX_WIN_PROT_RW2L_WP 5
930 #define NPCX_WIN_PROT_RW2H_RP 6
931 #define NPCX_WIN_PROT_RW2H_WP 7
932 #define NPCX_PWIN_SIZEI_RPROT 13
933 #define NPCX_PWIN_SIZEI_WPROT 14
934 #define NPCX_CSEM2 6
935 #define NPCX_CSEM3 7
936 #define NPCX_DP80STS_FWR 5
937 #define NPCX_DP80STS_FNE 6
938 #define NPCX_DP80STS_FOR 7
939 #define NPCX_DP80CTL_DP80EN 0
940 #define NPCX_DP80CTL_SYNCEN 1
941 #define NPCX_DP80CTL_ADV 2
942 #define NPCX_DP80CTL_RAA 3
943 #define NPCX_DP80CTL_RFIFO 4
944 #define NPCX_DP80CTL_CIEN 5
945 #define NPCX_DP80CTL_DP80_HF_CFG 7
946 #define NPCX_DP80BUF_OFFS_FIELD FIELD(8, 3)
947
948 /*
949 * Keyboard and Mouse Controller (KBC) device registers
950 */
951 struct kbc_reg {
952 /* 0x000h: Host Interface Control */
953 volatile uint8_t HICTRL;
954 volatile uint8_t reserved1;
955 /* 0x002h: Host Interface IRQ Control */
956 volatile uint8_t HIIRQC;
957 volatile uint8_t reserved2;
958 /* 0x004h: Host Interface Keyboard/Mouse Status */
959 volatile uint8_t HIKMST;
960 volatile uint8_t reserved3;
961 /* 0x006h: Host Interface Keyboard Data Out Buffer */
962 volatile uint8_t HIKDO;
963 volatile uint8_t reserved4;
964 /* 0x008h: Host Interface Mouse Data Out Buffer */
965 volatile uint8_t HIMDO;
966 volatile uint8_t reserved5;
967 /* 0x00Ah: Host Interface Keyboard/Mouse Data In Buffer */
968 volatile uint8_t HIKMDI;
969 /* 0x00Bh: Host Interface Keyboard/Mouse Shadow Data In Buffer */
970 volatile uint8_t SHIKMDI;
971 };
972
973 /* KBC register field */
974 #define NPCX_HICTRL_OBFKIE 0
975 #define NPCX_HICTRL_OBFMIE 1
976 #define NPCX_HICTRL_OBECIE 2
977 #define NPCX_HICTRL_IBFCIE 3
978 #define NPCX_HICTRL_PMIHIE 4
979 #define NPCX_HICTRL_PMIOCIE 5
980 #define NPCX_HICTRL_PMICIE 6
981 #define NPCX_HICTRL_FW_OBF 7
982 #define NPCX_HIKMST_OBF 0
983 #define NPCX_HIKMST_IBF 1
984 #define NPCX_HIKMST_F0 2
985 #define NPCX_HIKMST_A2 3
986 #define NPCX_HIKMST_ST0 4
987 #define NPCX_HIKMST_ST1 5
988 #define NPCX_HIKMST_ST2 6
989 #define NPCX_HIKMST_ST3 7
990
991 /*
992 * Power Management Channel (PMCH) device registers
993 */
994
995 struct pmch_reg {
996 /* 0x000: Host Interface PM Status */
997 volatile uint8_t HIPMST;
998 volatile uint8_t reserved1;
999 /* 0x002: Host Interface PM Data Out Buffer */
1000 volatile uint8_t HIPMDO;
1001 volatile uint8_t reserved2;
1002 /* 0x004: Host Interface PM Data In Buffer */
1003 volatile uint8_t HIPMDI;
1004 /* 0x005: Host Interface PM Shadow Data In Buffer */
1005 volatile uint8_t SHIPMDI;
1006 /* 0x006: Host Interface PM Data Out Buffer with SCI */
1007 volatile uint8_t HIPMDOC;
1008 volatile uint8_t reserved3;
1009 /* 0x008: Host Interface PM Data Out Buffer with SMI */
1010 volatile uint8_t HIPMDOM;
1011 volatile uint8_t reserved4;
1012 /* 0x00A: Host Interface PM Data In Buffer with SCI */
1013 volatile uint8_t HIPMDIC;
1014 volatile uint8_t reserved5;
1015 /* 0x00C: Host Interface PM Control */
1016 volatile uint8_t HIPMCTL;
1017 /* 0x00D: Host Interface PM Control 2 */
1018 volatile uint8_t HIPMCTL2;
1019 /* 0x00E: Host Interface PM Interrupt Control */
1020 volatile uint8_t HIPMIC;
1021 volatile uint8_t reserved6;
1022 /* 0x010: Host Interface PM Interrupt Enable */
1023 volatile uint8_t HIPMIE;
1024 volatile uint8_t reserved7;
1025 };
1026
1027 /* PMCH register field */
1028 #define NPCX_HIPMIE_SCIE 1
1029 #define NPCX_HIPMIE_SMIE 2
1030 #define NPCX_HIPMCTL_IBFIE 0
1031 #define NPCX_HIPMCTL_OBEIE 1
1032 #define NPCX_HIPMCTL_SCIPOL 6
1033 #define NPCX_HIPMST_OBF 0
1034 #define NPCX_HIPMST_IBF 1
1035 #define NPCX_HIPMST_F0 2
1036 #define NPCX_HIPMST_CMD 3
1037 #define NPCX_HIPMST_ST0 4
1038 #define NPCX_HIPMST_ST1 5
1039 #define NPCX_HIPMST_ST2 6
1040 #define NPCX_HIPMIC_SMIB 1
1041 #define NPCX_HIPMIC_SCIB 2
1042 #define NPCX_HIPMIC_SMIPOL 6
1043
1044 /*
1045 * Core Access to Host (C2H) device registers
1046 */
1047 struct c2h_reg {
1048 /* 0x000: Indirect Host I/O Address */
1049 volatile uint16_t IHIOA;
1050 /* 0x002: Indirect Host Data */
1051 volatile uint8_t IHD;
1052 volatile uint8_t reserved1;
1053 /* 0x004: Lock Host Access */
1054 volatile uint16_t LKSIOHA;
1055 /* 0x006: Access Lock Violation */
1056 volatile uint16_t SIOLV;
1057 /* 0x008: Core-to-Host Modules Access Enable */
1058 volatile uint16_t CRSMAE;
1059 /* 0x00A: Module Control */
1060 volatile uint8_t SIBCTRL;
1061 volatile uint8_t reserved3;
1062 };
1063
1064 /* C2H register fields */
1065 #define NPCX_LKSIOHA_LKCFG 0
1066 #define NPCX_LKSIOHA_LKSPHA 2
1067 #define NPCX_LKSIOHA_LKHIKBD 11
1068 #define NPCX_CRSMAE_CFGAE 0
1069 #define NPCX_CRSMAE_HIKBDAE 11
1070 #define NPCX_SIOLV_SPLV 2
1071 #define NPCX_SIBCTRL_CSAE 0
1072 #define NPCX_SIBCTRL_CSRD 1
1073 #define NPCX_SIBCTRL_CSWR 2
1074
1075 /*
1076 * SMBUS (SMB) device registers
1077 */
1078 struct smb_reg {
1079 /* 0x000: SMB Serial Data */
1080 volatile uint8_t SMBSDA;
1081 volatile uint8_t reserved1;
1082 /* 0x002: SMB Status */
1083 volatile uint8_t SMBST;
1084 volatile uint8_t reserved2;
1085 /* 0x004: SMB Control Status */
1086 volatile uint8_t SMBCST;
1087 volatile uint8_t reserved3;
1088 /* 0x006: SMB Control 1 */
1089 volatile uint8_t SMBCTL1;
1090 volatile uint8_t reserved4;
1091 /* 0x008: SMB Own Address */
1092 volatile uint8_t SMBADDR1;
1093 volatile uint8_t reserved5;
1094 /* 0x00A: SMB Control 2 */
1095 volatile uint8_t SMBCTL2;
1096 volatile uint8_t reserved6;
1097 /* 0x00C: SMB Own Address */
1098 volatile uint8_t SMBADDR2;
1099 volatile uint8_t reserved7;
1100 /* 0x00E: SMB Control 3 */
1101 volatile uint8_t SMBCTL3;
1102 /* 0x00F: SMB Bus Timeout */
1103 volatile uint8_t SMBT_OUT;
1104 union {
1105 /* Bank 0 */
1106 struct {
1107 /* 0x010: SMB Own Address 3 */
1108 volatile uint8_t SMBADDR3;
1109 /* 0x011: SMB Own Address 7 */
1110 volatile uint8_t SMBADDR7;
1111 /* 0x012: SMB Own Address 4 */
1112 volatile uint8_t SMBADDR4;
1113 /* 0x013: SMB Own Address 8 */
1114 volatile uint8_t SMBADDR8;
1115 /* 0x014: SMB Own Address 5 */
1116 volatile uint8_t SMBADDR5;
1117 volatile uint8_t reserved8;
1118 /* 0x016: SMB Own Address 6 */
1119 volatile uint8_t SMBADDR6;
1120 volatile uint8_t reserved9;
1121 /* 0x018: SMB Control Status 2 */
1122 volatile uint8_t SMBCST2;
1123 /* 0x019: SMB Control Status 3 */
1124 volatile uint8_t SMBCST3;
1125 /* 0x01A: SMB Control 4 */
1126 volatile uint8_t SMBCTL4;
1127 volatile uint8_t reserved10;
1128 /* 0x01C: SMB SCL Low Time */
1129 volatile uint8_t SMBSCLLT;
1130 /* 0x01D: SMB FIFO Control */
1131 volatile uint8_t SMBFIF_CTL;
1132 /* 0x01E: SMB SCL High Time */
1133 volatile uint8_t SMBSCLHT;
1134 volatile uint8_t reserved11;
1135 };
1136 /* Bank 1 */
1137 struct {
1138 /* 0x010: SMB FIFO Control */
1139 volatile uint8_t SMBFIF_CTS;
1140 volatile uint8_t reserved12;
1141 /* 0x012: SMB Tx-FIFO Control */
1142 volatile uint8_t SMBTXF_CTL;
1143 volatile uint8_t reserved13;
1144 /* 0x014: SMB Bus Timeout */
1145 volatile uint8_t SMB_T_OUT;
1146 volatile uint8_t reserved14[3];
1147 /* 0x018: SMB Control Status 2 (FIFO) */
1148 volatile uint8_t SMBCST2_FIFO;
1149 /* 0x019: SMB Control Status 3 (FIFO) */
1150 volatile uint8_t SMBCST3_FIFO;
1151 /* 0x01A: SMB Tx-FIFO Status */
1152 volatile uint8_t SMBTXF_STS;
1153 volatile uint8_t reserved15;
1154 /* 0x01C: SMB Rx-FIFO Status */
1155 volatile uint8_t SMBRXF_STS;
1156 volatile uint8_t reserved16;
1157 /* 0x01E: SMB Rx-FIFO Control */
1158 volatile uint8_t SMBRXF_CTL;
1159 volatile uint8_t reserved17[1];
1160 };
1161 };
1162 };
1163
1164 /* SMB register fields */
1165 #define NPCX_SMBST_XMIT 0
1166 #define NPCX_SMBST_MASTER 1
1167 #define NPCX_SMBST_NMATCH 2
1168 #define NPCX_SMBST_STASTR 3
1169 #define NPCX_SMBST_NEGACK 4
1170 #define NPCX_SMBST_BER 5
1171 #define NPCX_SMBST_SDAST 6
1172 #define NPCX_SMBST_SLVSTP 7
1173 #define NPCX_SMBCST_BUSY 0
1174 #define NPCX_SMBCST_BB 1
1175 #define NPCX_SMBCST_MATCH 2
1176 #define NPCX_SMBCST_GCMATCH 3
1177 #define NPCX_SMBCST_TSDA 4
1178 #define NPCX_SMBCST_TGSCL 5
1179 #define NPCX_SMBCST_MATCHAF 6
1180 #define NPCX_SMBCST_ARPMATCH 7
1181 #define NPCX_SMBCST2_MATCHA1F 0
1182 #define NPCX_SMBCST2_MATCHA2F 1
1183 #define NPCX_SMBCST2_MATCHA3F 2
1184 #define NPCX_SMBCST2_MATCHA4F 3
1185 #define NPCX_SMBCST2_MATCHA5F 4
1186 #define NPCX_SMBCST2_MATCHA6F 5
1187 #define NPCX_SMBCST2_MATCHA7F 6
1188 #define NPCX_SMBCST2_INTSTS 7
1189 #define NPCX_SMBCST3_MATCHA8F 0
1190 #define NPCX_SMBCST3_MATCHA9F 1
1191 #define NPCX_SMBCST3_MATCHA10F 2
1192 #define NPCX_SMBCTL1_START 0
1193 #define NPCX_SMBCTL1_STOP 1
1194 #define NPCX_SMBCTL1_INTEN 2
1195 #define NPCX_SMBCTL1_ACK 4
1196 #define NPCX_SMBCTL1_GCMEN 5
1197 #define NPCX_SMBCTL1_NMINTE 6
1198 #define NPCX_SMBCTL1_STASTRE 7
1199 #define NPCX_SMBCTL2_ENABLE 0
1200 #define NPCX_SMBCTL2_SCLFRQ0_6_FIELD FIELD(1, 7)
1201 #define NPCX_SMBCTL3_ARPMEN 2
1202 #define NPCX_SMBCTL3_SCLFRQ7_8_FIELD FIELD(0, 2)
1203 #define NPCX_SMBCTL3_IDL_START 3
1204 #define NPCX_SMBCTL3_400K 4
1205 #define NPCX_SMBCTL3_BNK_SEL 5
1206 #define NPCX_SMBCTL3_SDA_LVL 6
1207 #define NPCX_SMBCTL3_SCL_LVL 7
1208 #define NPCX_SMBCTL4_HLDT_FIELD FIELD(0, 6)
1209 #define NPCX_SMBCTL4_LVL_WE 7
1210 #define NPCX_SMBADDR1_SAEN 7
1211 #define NPCX_SMBADDR2_SAEN 7
1212 #define NPCX_SMBADDR3_SAEN 7
1213 #define NPCX_SMBADDR4_SAEN 7
1214 #define NPCX_SMBADDR5_SAEN 7
1215 #define NPCX_SMBADDR6_SAEN 7
1216 #define NPCX_SMBADDR7_SAEN 7
1217 #define NPCX_SMBADDR8_SAEN 7
1218 #define NPCX_SMBSEL_SMB4SEL 4
1219 #define NPCX_SMBSEL_SMB5SEL 5
1220 #define NPCX_SMBSEL_SMB6SEL 6
1221 #define NPCX_SMBFIF_CTS_RXF_TXE 1
1222 #define NPCX_SMBFIF_CTS_CLR_FIFO 6
1223 #define NPCX_SMBFIF_CTL_FIFO_EN 4
1224 #define NPCX_SMBRXF_STS_RX_THST 6
1225
1226 /* RX FIFO threshold */
1227 #define NPCX_SMBRXF_CTL_RX_THR FIELD(0, 6)
1228 #define NPCX_SMBRXF_CTL_LAST 7
1229
1230 /*
1231 * Internal 32-bit Timer (ITIM32) device registers
1232 */
1233 struct itim32_reg {
1234 volatile uint8_t reserved1;
1235 /* 0x001: Internal 32-bit Timer Prescaler */
1236 volatile uint8_t ITPRE32;
1237 volatile uint8_t reserved2[2];
1238 /* 0x004: Internal 32-bit Timer Control and Status */
1239 volatile uint8_t ITCTS32;
1240 volatile uint8_t reserved3[3];
1241 /* 0x008: Internal 32-Bit Timer Counter */
1242 volatile uint32_t ITCNT32;
1243 };
1244
1245 /*
1246 * Internal 64-bit Timer (ITIM54) device registers
1247 */
1248 struct itim64_reg {
1249 volatile uint8_t reserved1;
1250 /* 0x001: Internal 64-bit Timer Prescaler */
1251 volatile uint8_t ITPRE64;
1252 volatile uint8_t reserved2[2];
1253 /* 0x004: Internal 64-bit Timer Control and Status */
1254 volatile uint8_t ITCTS64;
1255 volatile uint8_t reserved3[3];
1256 /* 0x008: Internal 32-Bit Timer Counter */
1257 volatile uint32_t ITCNT64L;
1258 /* 0x00C: Internal 32-Bit Timer Counter */
1259 volatile uint32_t ITCNT64H;
1260 };
1261
1262 /* ITIM register fields */
1263 #define NPCX_ITCTSXX_TO_STS 0
1264 #define NPCX_ITCTSXX_TO_IE 2
1265 #define NPCX_ITCTSXX_TO_WUE 3
1266 #define NPCX_ITCTSXX_CKSEL 4
1267 #define NPCX_ITCTSXX_ITEN 7
1268
1269 /*
1270 * Tachometer (TACH) Sensor device registers
1271 */
1272 struct tach_reg {
1273 /* 0x000: Timer/Counter 1 */
1274 volatile uint16_t TCNT1;
1275 /* 0x002: Reload/Capture A */
1276 volatile uint16_t TCRA;
1277 /* 0x004: Reload/Capture B */
1278 volatile uint16_t TCRB;
1279 /* 0x006: Timer/Counter 2 */
1280 volatile uint16_t TCNT2;
1281 /* 0x008: Clock Prescaler */
1282 volatile uint8_t TPRSC;
1283 volatile uint8_t reserved1;
1284 /* 0x00A: Clock Unit Control */
1285 volatile uint8_t TCKC;
1286 volatile uint8_t reserved2;
1287 /* 0x00C: Timer Mode Control */
1288 volatile uint8_t TMCTRL;
1289 volatile uint8_t reserved3;
1290 /* 0x00E: Timer Event Control */
1291 volatile uint8_t TECTRL;
1292 volatile uint8_t reserved4;
1293 /* 0x010: Timer Event Clear */
1294 volatile uint8_t TECLR;
1295 volatile uint8_t reserved5;
1296 /* 0x012: Timer Interrupt Enable */
1297 volatile uint8_t TIEN;
1298 volatile uint8_t reserved6;
1299 /* 0x014: Compare A */
1300 volatile uint16_t TCPA;
1301 /* 0x016: Compare B */
1302 volatile uint16_t TCPB;
1303 /* 0x018: Compare Configuration */
1304 volatile uint8_t TCPCFG;
1305 volatile uint8_t reserved7;
1306 /* 0x01A: Timer Wake-Up Enable */
1307 volatile uint8_t TWUEN;
1308 volatile uint8_t reserved8;
1309 /* 0x01C: Timer Configuration */
1310 volatile uint8_t TCFG;
1311 volatile uint8_t reserved9;
1312 };
1313
1314 /* TACH register fields */
1315 #define NPCX_TCKC_LOW_PWR 7
1316 #define NPCX_TCKC_PLS_ACC_CLK 6
1317 #define NPCX_TCKC_C1CSEL_FIELD FIELD(0, 3)
1318 #define NPCX_TCKC_C2CSEL_FIELD FIELD(3, 3)
1319 #define NPCX_TMCTRL_MDSEL_FIELD FIELD(0, 3)
1320 #define NPCX_TMCTRL_TAEN 5
1321 #define NPCX_TMCTRL_TBEN 6
1322 #define NPCX_TMCTRL_TAEDG 3
1323 #define NPCX_TMCTRL_TBEDG 4
1324 #define NPCX_TCFG_TADBEN 6
1325 #define NPCX_TCFG_TBDBEN 7
1326 #define NPCX_TECTRL_TAPND 0
1327 #define NPCX_TECTRL_TBPND 1
1328 #define NPCX_TECTRL_TCPND 2
1329 #define NPCX_TECTRL_TDPND 3
1330 #define NPCX_TECLR_TACLR 0
1331 #define NPCX_TECLR_TBCLR 1
1332 #define NPCX_TECLR_TCCLR 2
1333 #define NPCX_TECLR_TDCLR 3
1334 #define NPCX_TIEN_TAIEN 0
1335 #define NPCX_TIEN_TBIEN 1
1336 #define NPCX_TIEN_TCIEN 2
1337 #define NPCX_TIEN_TDIEN 3
1338 #define NPCX_TWUEN_TAWEN 0
1339 #define NPCX_TWUEN_TBWEN 1
1340 #define NPCX_TWUEN_TCWEN 2
1341 #define NPCX_TWUEN_TDWEN 3
1342
1343 /* Debug Interface registers */
1344 struct dbg_reg {
1345 /* 0x000: Debug Control */
1346 volatile uint8_t DBGCTRL;
1347 volatile uint8_t reserved1;
1348 /* 0x002: Debug Freeze Enable 1 */
1349 volatile uint8_t DBGFRZEN1;
1350 /* 0x003: Debug Freeze Enable 2 */
1351 volatile uint8_t DBGFRZEN2;
1352 /* 0x004: Debug Freeze Enable 3 */
1353 volatile uint8_t DBGFRZEN3;
1354 /* 0x005: Debug Freeze Enable 4 */
1355 volatile uint8_t DBGFRZEN4;
1356 };
1357 /* Debug Interface registers fields */
1358 #define NPCX_DBGFRZEN3_GLBL_FRZ_DIS 7
1359
1360 /* PS/2 Interface registers */
1361 struct ps2_reg {
1362 /* 0x000: PS/2 Data */
1363 volatile uint8_t PSDAT;
1364 volatile uint8_t reserved1;
1365 /* 0x002: PS/2 Status */
1366 volatile uint8_t PSTAT;
1367 volatile uint8_t reserved2;
1368 /* 0x004: PS/2 Control */
1369 volatile uint8_t PSCON;
1370 volatile uint8_t reserved3;
1371 /* 0x006: PS/2 Output Signal */
1372 volatile uint8_t PSOSIG;
1373 volatile uint8_t reserved4;
1374 /* 0x008: PS/2 Input Signal */
1375 volatile uint8_t PSISIG;
1376 volatile uint8_t reserved5;
1377 /* 0x00A: PS/2 Interrupt Enable */
1378 volatile uint8_t PSIEN;
1379 volatile uint8_t reserved6;
1380 };
1381
1382 /* PS/2 Interface registers fields */
1383 #define NPCX_PSTAT_SOT 0
1384 #define NPCX_PSTAT_EOT 1
1385 #define NPCX_PSTAT_PERR 2
1386 #define NPCX_PSTAT_ACH FIELD(3, 3)
1387 #define NPCX_PSTAT_RFERR 6
1388
1389 #define NPCX_PSCON_EN 0
1390 #define NPCX_PSCON_XMT 1
1391 #define NPCX_PSCON_HDRV FIELD(2, 2)
1392 #define NPCX_PSCON_IDB FIELD(4, 3)
1393 #define NPCX_PSCON_WPUED 7
1394
1395 #define NPCX_PSOSIG_WDAT0 0
1396 #define NPCX_PSOSIG_WDAT1 1
1397 #define NPCX_PSOSIG_WDAT2 2
1398 #define NPCX_PSOSIG_CLK0 3
1399 #define NPCX_PSOSIG_CLK1 4
1400 #define NPCX_PSOSIG_CLK2 5
1401 #define NPCX_PSOSIG_WDAT3 6
1402 #define NPCX_PSOSIG_CLK3 7
1403 #define NPCX_PSOSIG_CLK(n) (((n) < 3) ? ((n) + 3) : 7)
1404 #define NPCX_PSOSIG_WDAT(n) (((n) < 3) ? ((n) + 0) : 6)
1405 #define NPCX_PSOSIG_CLK_MASK_ALL \
1406 (BIT(NPCX_PSOSIG_CLK0) | \
1407 BIT(NPCX_PSOSIG_CLK1) | \
1408 BIT(NPCX_PSOSIG_CLK2) | \
1409 BIT(NPCX_PSOSIG_CLK3))
1410
1411 #define NPCX_PSIEN_SOTIE 0
1412 #define NPCX_PSIEN_EOTIE 1
1413 #define NPCX_PSIEN_PS2_WUE 4
1414 #define NPCX_PSIEN_PS2_CLK_SEL 7
1415
1416 /* Flash Interface Unit (FIU) device registers */
1417 struct fiu_reg {
1418 volatile uint8_t reserved1;
1419 /* 0x001: Burst Configuration */
1420 volatile uint8_t BURST_CFG;
1421 /* 0x002: FIU Response Configuration */
1422 volatile uint8_t RESP_CFG;
1423 volatile uint8_t reserved2[17];
1424 /* 0x014: SPI Flash Configuration */
1425 volatile uint8_t SPI_FL_CFG;
1426 volatile uint8_t reserved3;
1427 /* 0x016: UMA Code Byte */
1428 volatile uint8_t UMA_CODE;
1429 /* 0x017: UMA Address Byte 0 */
1430 volatile uint8_t UMA_AB0;
1431 /* 0x018: UMA Address Byte 1 */
1432 volatile uint8_t UMA_AB1;
1433 /* 0x019: UMA Address Byte 2 */
1434 volatile uint8_t UMA_AB2;
1435 /* 0x01A: UMA Data Byte 0 */
1436 volatile uint8_t UMA_DB0;
1437 /* 0x01B: UMA Data Byte 1 */
1438 volatile uint8_t UMA_DB1;
1439 /* 0x01C: UMA Data Byte 2 */
1440 volatile uint8_t UMA_DB2;
1441 /* 0x01D: UMA Data Byte 3 */
1442 volatile uint8_t UMA_DB3;
1443 /* 0x01E: UMA Control and Status */
1444 volatile uint8_t UMA_CTS;
1445 /* 0x01F: UMA Extended Control and Status */
1446 volatile uint8_t UMA_ECTS;
1447 /* 0x020: UMA Data Bytes 0-3 */
1448 volatile uint32_t UMA_DB0_3;
1449 volatile uint8_t reserved4[2];
1450 /* 0x026: CRC Control Register */
1451 volatile uint8_t CRCCON;
1452 /* 0x027: CRC Entry Register */
1453 volatile uint8_t CRCENT;
1454 /* 0x028: CRC Initialization and Result Register */
1455 volatile uint32_t CRCRSLT;
1456 volatile uint8_t reserved5[4];
1457 /* 0x030: FIU Read Command */
1458 volatile uint8_t FIU_RD_CMD;
1459 volatile uint8_t reserved6;
1460 /* 0x032: FIU Dummy Cycles */
1461 volatile uint8_t FIU_DMM_CYC;
1462 /* 0x033: FIU Extended Configuration */
1463 volatile uint8_t FIU_EXT_CFG;
1464 #if defined(CONFIG_SOC_SERIES_NPCX9)
1465 /* 0x034: UMA address byte 0-3 */
1466 volatile uint32_t UMA_AB0_3;
1467 /* 0x038-0x3C */
1468 volatile uint8_t reserved8[5];
1469 /* 0x03D: SPI Device */
1470 volatile uint8_t SPI1_DEV;
1471 /* 0x03E-0x3F */
1472 volatile uint8_t reserved9[2];
1473 #elif defined(CONFIG_SOC_SERIES_NPCX4)
1474 /* 0x034: UMA address byte 0-3 */
1475 volatile uint32_t UMA_AB0_3;
1476 /* 0x038-0x3B */
1477 volatile uint8_t reserved8[4];
1478 /* 0x03C: SPI Device */
1479 volatile uint8_t SPI_DEV;
1480 /* 0x03D */
1481 volatile uint8_t reserved9;
1482 /* 0x03E */
1483 volatile uint8_t SPI_DEV_SIZE;
1484 /* 0x03F */
1485 volatile uint8_t reserved10;
1486 #endif
1487 };
1488
1489 /* FIU register fields */
1490 #define NPCX_BURST_CFG_SPI_DEV_SEL FIELD(4, 2)
1491 #define NPCX_RESP_CFG_IAD_EN 0
1492 #define NPCX_RESP_CFG_DEV_SIZE_EX 2
1493 #define NPCX_RESP_CFG_QUAD_EN 3
1494 #define NPCX_SPI_FL_CFG_RD_MODE FIELD(6, 2)
1495 #define NPCX_UMA_CTS_A_SIZE 3
1496 #define NPCX_UMA_CTS_C_SIZE 4
1497 #define NPCX_UMA_CTS_RD_WR 5
1498 #define NPCX_UMA_CTS_DEV_NUM 6
1499 #define NPCX_UMA_CTS_EXEC_DONE 7
1500 #define NPCX_UMA_ECTS_SW_CS0 0
1501 #define NPCX_UMA_ECTS_SW_CS1 1
1502 #define NPCX_UMA_ECTS_SEC_CS 2
1503 #define NPCX_UMA_ECTS_UMA_LOCK 3
1504 #define NPCX_UMA_ECTS_UMA_ADDR_SIZE FIELD(4, 3)
1505 #define NPCX_SPI1_DEV_FOUR_BADDR_CS10 6
1506 #define NPCX_SPI1_DEV_FOUR_BADDR_CS11 7
1507 #define NPCX_SPI1_DEV_SPI1_LO_DEV_SIZE FIELD(0, 4)
1508 #define NPCX_FIU_EXT_CFG_SET_DMM_EN 2
1509 #define NPCX_FIU_EXT_CFG_SET_CMD_EN 1
1510 #define NPCX_SPI_DEV_NADDRB FIELD(5, 3)
1511
1512 #define NPCX_MSR_IE_CFG_UMA_BLOCK 3
1513
1514 /* UMA fields selections */
1515 #define UMA_FLD_ADDR BIT(NPCX_UMA_CTS_A_SIZE) /* 3-bytes ADR field */
1516 #define UMA_FLD_NO_CMD BIT(NPCX_UMA_CTS_C_SIZE) /* No 1-Byte CMD field */
1517 #define UMA_FLD_WRITE BIT(NPCX_UMA_CTS_RD_WR) /* Write transaction */
1518 #define UMA_FLD_SHD_SL BIT(NPCX_UMA_CTS_DEV_NUM) /* Shared flash selected */
1519 #define UMA_FLD_EXEC BIT(NPCX_UMA_CTS_EXEC_DONE)
1520
1521 #define UMA_FIELD_DATA_1 0x01
1522 #define UMA_FIELD_DATA_2 0x02
1523 #define UMA_FIELD_DATA_3 0x03
1524 #define UMA_FIELD_DATA_4 0x04
1525
1526 /* UMA code for transaction */
1527 #define UMA_CODE_CMD_ONLY (UMA_FLD_EXEC | UMA_FLD_SHD_SL)
1528 #define UMA_CODE_CMD_ADR (UMA_FLD_EXEC | UMA_FLD_ADDR | \
1529 UMA_FLD_SHD_SL)
1530 #define UMA_CODE_CMD_RD_BYTE(n) (UMA_FLD_EXEC | UMA_FIELD_DATA_##n | \
1531 UMA_FLD_SHD_SL)
1532 #define UMA_CODE_RD_BYTE(n) (UMA_FLD_EXEC | UMA_FLD_NO_CMD | \
1533 UMA_FIELD_DATA_##n | UMA_FLD_SHD_SL)
1534 #define UMA_CODE_CMD_WR_ONLY (UMA_FLD_EXEC | UMA_FLD_WRITE | \
1535 UMA_FLD_SHD_SL)
1536 #define UMA_CODE_CMD_WR_BYTE(n) (UMA_FLD_EXEC | UMA_FLD_WRITE | \
1537 UMA_FIELD_DATA_##n | UMA_FLD_SHD_SL)
1538 #define UMA_CODE_CMD_WR_ADR (UMA_FLD_EXEC | UMA_FLD_WRITE | UMA_FLD_ADDR | \
1539 UMA_FLD_SHD_SL)
1540
1541 #define UMA_CODE_CMD_ADR_WR_BYTE(n) (UMA_FLD_EXEC | UMA_FLD_WRITE | \
1542 UMA_FLD_ADDR | UMA_FIELD_DATA_##n | \
1543 UMA_FLD_SHD_SL)
1544
1545 /* Platform Environment Control Interface (PECI) device registers */
1546 struct peci_reg {
1547 /* 0x000: PECI Control Status */
1548 volatile uint8_t PECI_CTL_STS;
1549 /* 0x001: PECI Read Length */
1550 volatile uint8_t PECI_RD_LENGTH;
1551 /* 0x002: PECI Address */
1552 volatile uint8_t PECI_ADDR;
1553 /* 0x003: PECI Command */
1554 volatile uint8_t PECI_CMD;
1555 /* 0x004: PECI Control 2 */
1556 volatile uint8_t PECI_CTL2;
1557 /* 0x005: PECI Index */
1558 volatile uint8_t PECI_INDEX;
1559 /* 0x006: PECI Index Data */
1560 volatile uint8_t PECI_IDATA;
1561 /* 0x007: PECI Write Length */
1562 volatile uint8_t PECI_WR_LENGTH;
1563 volatile uint8_t reserved1[3];
1564 /* 0x00B: PECI Write FCS */
1565 volatile uint8_t PECI_WR_FCS;
1566 /* 0x00C: PECI Read FCS */
1567 volatile uint8_t PECI_RD_FCS;
1568 /* 0x00D: PECI Assured Write FCS */
1569 volatile uint8_t PECI_AW_FCS;
1570 volatile uint8_t reserved2;
1571 /* 0x00F: PECI Transfer Rate */
1572 volatile uint8_t PECI_RATE;
1573 /* 0x010 - 0x04F: PECI Data In/Out */
1574 union {
1575 volatile uint8_t PECI_DATA_IN[64];
1576 volatile uint8_t PECI_DATA_OUT[64];
1577 };
1578 };
1579
1580 /* PECI register fields */
1581 #define NPCX_PECI_CTL_STS_START_BUSY 0
1582 #define NPCX_PECI_CTL_STS_DONE 1
1583 #define NPCX_PECI_CTL_STS_CRC_ERR 3
1584 #define NPCX_PECI_CTL_STS_ABRT_ERR 4
1585 #define NPCX_PECI_CTL_STS_AWFCS_EB 5
1586 #define NPCX_PECI_CTL_STS_DONE_EN 6
1587 #define NPCX_PECI_RATE_MAX_BIT_RATE FIELD(0, 5)
1588 #define NPCX_PECI_RATE_MAX_BIT_RATE_MASK 0x1F
1589 /* The minimal valid value of NPCX_PECI_RATE_MAX_BIT_RATE field */
1590 #define PECI_MAX_BIT_RATE_VALID_MIN 0x05
1591 #define PECI_HIGH_SPEED_MIN_VAL 0x07
1592
1593 #define NPCX_PECI_RATE_EHSP 6
1594
1595 /* KBS (Keyboard Scan) device registers */
1596 struct kbs_reg {
1597 volatile uint8_t reserved1[4];
1598 /* 0x004: Keyboard Scan In */
1599 volatile uint8_t KBSIN;
1600 /* 0x005: Keyboard Scan In Pull-Up Enable */
1601 volatile uint8_t KBSINPU;
1602 /* 0x006: Keyboard Scan Out 0 */
1603 volatile uint16_t KBSOUT0;
1604 /* 0x008: Keyboard Scan Out 1 */
1605 volatile uint16_t KBSOUT1;
1606 /* 0x00A: Keyboard Scan Buffer Index */
1607 volatile uint8_t KBS_BUF_INDX;
1608 /* 0x00B: Keyboard Scan Buffer Data */
1609 volatile uint8_t KBS_BUF_DATA;
1610 /* 0x00C: Keyboard Scan Event */
1611 volatile uint8_t KBSEVT;
1612 /* 0x00D: Keyboard Scan Control */
1613 volatile uint8_t KBSCTL;
1614 /* 0x00E: Keyboard Scan Configuration Index */
1615 volatile uint8_t KBS_CFG_INDX;
1616 /* 0x00F: Keyboard Scan Configuration Data */
1617 volatile uint8_t KBS_CFG_DATA;
1618 };
1619
1620 /* KBS register fields */
1621 #define NPCX_KBSBUFINDX 0
1622 #define NPCX_KBSEVT_KBSDONE 0
1623 #define NPCX_KBSEVT_KBSERR 1
1624 #define NPCX_KBSCTL_START 0
1625 #define NPCX_KBSCTL_KBSMODE 1
1626 #define NPCX_KBSCTL_KBSIEN 2
1627 #define NPCX_KBSCTL_KBSINC 3
1628 #define NPCX_KBSCTL_KBHDRV_FIELD FIELD(6, 2)
1629 #define NPCX_KBSCFGINDX 0
1630 /* Index of 'Automatic Scan' configuration register */
1631 #define KBS_CFG_INDX_DLY1 0 /* Keyboard Scan Delay T1 Byte */
1632 #define KBS_CFG_INDX_DLY2 1 /* Keyboard Scan Delay T2 Byte */
1633 #define KBS_CFG_INDX_RTYTO 2 /* Keyboard Scan Retry Timeout */
1634 #define KBS_CFG_INDX_CNUM 3 /* Keyboard Scan Columns Number */
1635 #define KBS_CFG_INDX_CDIV 4 /* Keyboard Scan Clock Divisor */
1636
1637 /* SHI (Serial Host Interface) registers */
1638 struct shi_reg {
1639 volatile uint8_t reserved1;
1640 /* 0x001: SHI Configuration 1 */
1641 volatile uint8_t SHICFG1;
1642 /* 0x002: SHI Configuration 2 */
1643 volatile uint8_t SHICFG2;
1644 volatile uint8_t reserved2[2];
1645 /* 0x005: Event Enable */
1646 volatile uint8_t EVENABLE;
1647 /* 0x006: Event Status */
1648 volatile uint8_t EVSTAT;
1649 /* 0x007: SHI Capabilities */
1650 volatile uint8_t CAPABILITY;
1651 /* 0x008: Status */
1652 volatile uint8_t STATUS;
1653 volatile uint8_t reserved3;
1654 /* 0x00A: Input Buffer Status */
1655 volatile uint8_t IBUFSTAT;
1656 /* 0x00B: Output Buffer Status */
1657 volatile uint8_t OBUFSTAT;
1658 /* 0x00C: SHI Configuration 3 */
1659 volatile uint8_t SHICFG3;
1660 /* 0x00D: SHI Configuration 4 */
1661 volatile uint8_t SHICFG4;
1662 /* 0x00E: SHI Configuration 5 */
1663 volatile uint8_t SHICFG5;
1664 /* 0x00F: Event Status 2 */
1665 volatile uint8_t EVSTAT2;
1666 /* 0x010: Event Enable 2 */
1667 volatile uint8_t EVENABLE2;
1668 /* 0x011: SHI Configuration 6 - only in chips which support enhanced buffer mode */
1669 volatile uint8_t SHICFG6;
1670 /* 0x012: Single Byte Output Buffer - only in chips which support enhanced buffer mode */
1671 volatile uint8_t SBOBUF;
1672 volatile uint8_t reserved4[13];
1673 /* 0x20~0x9F: Output Buffer */
1674 volatile uint8_t OBUF[128];
1675 /* 0xA0~0x11F: Input Buffer */
1676 volatile uint8_t IBUF[128];
1677 };
1678
1679 /* SHI register fields */
1680 #define NPCX_SHICFG1_EN 0
1681 #define NPCX_SHICFG1_MODE 1
1682 #define NPCX_SHICFG1_WEN 2
1683 #define NPCX_SHICFG1_AUTIBF 3
1684 #define NPCX_SHICFG1_AUTOBE 4
1685 #define NPCX_SHICFG1_DAS 5
1686 #define NPCX_SHICFG1_CPOL 6
1687 #define NPCX_SHICFG1_IWRAP 7
1688 #define NPCX_SHICFG2_SIMUL 0
1689 #define NPCX_SHICFG2_BUSY 1
1690 #define NPCX_SHICFG2_ONESHOT 2
1691 #define NPCX_SHICFG2_SLWU 3
1692 #define NPCX_SHICFG2_REEN 4
1693 #define NPCX_SHICFG2_RESTART 5
1694 #define NPCX_SHICFG2_REEVEN 6
1695 #define NPCX_EVENABLE_OBEEN 0
1696 #define NPCX_EVENABLE_OBHEEN 1
1697 #define NPCX_EVENABLE_IBFEN 2
1698 #define NPCX_EVENABLE_IBHFEN 3
1699 #define NPCX_EVENABLE_EOREN 4
1700 #define NPCX_EVENABLE_EOWEN 5
1701 #define NPCX_EVENABLE_STSREN 6
1702 #define NPCX_EVENABLE_IBOREN 7
1703 #define NPCX_EVSTAT_OBE 0
1704 #define NPCX_EVSTAT_OBHE 1
1705 #define NPCX_EVSTAT_IBF 2
1706 #define NPCX_EVSTAT_IBHF 3
1707 #define NPCX_EVSTAT_EOR 4
1708 #define NPCX_EVSTAT_EOW 5
1709 #define NPCX_EVSTAT_STSR 6
1710 #define NPCX_EVSTAT_IBOR 7
1711 #define NPCX_STATUS_OBES 6
1712 #define NPCX_STATUS_IBFS 7
1713 #define NPCX_SHICFG3_OBUFLVLDIS 7
1714 #define NPCX_SHICFG4_IBUFLVLDIS 7
1715 #define NPCX_SHICFG5_IBUFLVL2 FIELD(0, 6)
1716 #define NPCX_SHICFG5_IBUFLVL2DIS 7
1717 #define NPCX_EVSTAT2_IBHF2 0
1718 #define NPCX_EVSTAT2_CSNRE 1
1719 #define NPCX_EVSTAT2_CSNFE 2
1720 #define NPCX_EVENABLE2_IBHF2EN 0
1721 #define NPCX_EVENABLE2_CSNREEN 1
1722 #define NPCX_EVENABLE2_CSNFEEN 2
1723 #define NPCX_SHICFG6_EBUFMD 0
1724 #define NPCX_SHICFG6_OBUF_SL 1
1725
1726 #define IBF_IBHF_EN_MASK (BIT(NPCX_EVENABLE_IBFEN) | BIT(NPCX_EVENABLE_IBHFEN))
1727
1728 /* SPIP (SPI Peripheral Interface) registers */
1729 struct spip_reg {
1730 /* 0x000: SPIP Data In/Out */
1731 volatile uint16_t SPIP_DATA;
1732 /* 0x002: SPIP Control 1 */
1733 volatile uint16_t SPIP_CTL1;
1734 /* 0x004: SPIP Status */
1735 volatile uint8_t SPIP_STAT;
1736 volatile uint8_t reserved1;
1737 };
1738
1739 #define NPCX_SPIP_CTL1_SPIEN 0
1740 #define NPCX_SPIP_CTL1_MOD 2
1741 #define NPCX_SPIP_CTL1_EIR 5
1742 #define NPCX_SPIP_CTL1_EIW 6
1743 #define NPCX_SPIP_CTL1_SCM 7
1744 #define NPCX_SPIP_CTL1_SCIDL 8
1745 #define NPCX_SPIP_CTL1_SCDV FIELD(9, 7)
1746 #define NPCX_SPIP_STAT_BSY 0
1747 #define NPCX_SPIP_STAT_RBF 1
1748
1749 #endif /* _NUVOTON_NPCX_REG_DEF_H */
1750
