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Searched refs:MCUX_IMX_SLEW_RATE_SHIFT (Results 1 – 9 of 9) sorted by relevance

/Zephyr-Core-3.6.0/soc/arm/nxp_imx/mimx8mm6_m4/
Dpinctrl_soc.h22 #define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT macro
34 (DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \
/Zephyr-Core-3.6.0/soc/arm/nxp_imx/mimx8ml8_m7/
Dpinctrl_soc.h22 #define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT macro
34 (DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \
/Zephyr-Core-3.6.0/soc/arm/nxp_imx/mimx8mq6_m4/
Dpinctrl_soc.h22 #define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT macro
33 (DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \
/Zephyr-Core-3.6.0/soc/xtensa/nxp_adsp/imx8m/include/
Dpinctrl_soc.h22 #define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT macro
34 (DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \
/Zephyr-Core-3.6.0/soc/arm64/nxp_imx/mimx8m/
Dpinctrl_soc.h22 #define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT macro
34 (DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \
/Zephyr-Core-3.6.0/soc/arm64/nxp_imx/mimx9/
Dpinctrl_soc.h22 #define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC1_SW_PAD_CTL_PAD_FSEL1_SHIFT macro
32 (DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \
/Zephyr-Core-3.6.0/soc/arm/nxp_imx/mcimx6x_m4/
Dpinctrl_soc.h29 #define MCUX_IMX_SLEW_RATE_SHIFT 0 macro
45 (DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \
/Zephyr-Core-3.6.0/soc/arm/nxp_imx/mcimx7_m4/
Dpinctrl_soc.h24 #define MCUX_IMX_SLEW_RATE_SHIFT 2 macro
36 (DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \
/Zephyr-Core-3.6.0/soc/arm/nxp_imx/rt/
Dpinctrl_rt10xx.h26 #define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT macro
42 (DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \