1 /* 2 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MEC_TIMERS_H 8 #define _MEC_TIMERS_H 9 10 #include <stdint.h> 11 #include <stddef.h> 12 13 /* Basic timers */ 14 15 /* Offset between instances of the Basic Timer blocks */ 16 #define MCHP_BTMR_INSTANCE_POS 5ul 17 #define MCHP_BTMR_INSTANCE_OFS 0x20u 18 19 /* Base frequency of all basic timers is AHB clock */ 20 #define MCHP_BTMR_BASE_FREQ 48000000u 21 #define MCHP_BTMR_MIN_FREQ (MCHP_BTMR_BASE_FREQ / 0x10000u) 22 23 /* 24 * Basic Timer Count Register (Offset +00h) 25 * 32-bit R/W 26 * 16-bit Basic timers: bits[15:0]=R/W, bits[31:15]=RO=0 27 */ 28 #define MCHP_BTMR_CNT_OFS 0x00u 29 30 /* 31 * Basic Timer Preload Register (Offset +04h) 32 * 32-bit R/W 33 * 16-bit Basic timers: bits[15:0]=R/W, bits[31:15]=RO=0 34 */ 35 #define MCHP_BTMR_PRELOAD_OFS 0x04u 36 37 /* Basic Timer Status Register (Offset +08h) R/W1C */ 38 #define MCHP_BTMR_STS_OFS 0x08u 39 #define MCHP_BTMR_STS_MASK 0x01u 40 #define MCHP_BTMR_STS_ACTIVE_POS 0 41 #define MCHP_BTMR_STS_ACTIVE 0x01u 42 43 /* Basic Timer Interrupt Enable Register (Offset +0Ch) */ 44 #define MCHP_BTMR_INTEN_OFS 0x0cu 45 #define MCHP_BTMR_INTEN_MASK 0x01u 46 #define MCHP_BTMR_INTEN_POS 0 47 #define MCHP_BTMR_INTEN 0x01u 48 #define MCHP_BTMR_INTDIS 0u 49 50 /* Basic Timer Control Register (Offset +10h) */ 51 #define MCHP_BTMR_CTRL_OFS 0x10u 52 #define MCHP_BTMR_CTRL_MASK 0xffff00fdu 53 54 #define MCHP_BTMR_CTRL_PRESCALE_POS 16u 55 #define MCHP_BTMR_CTRL_PRESCALE_MASK0 0xffffu 56 #define MCHP_BTMR_CTRL_PRESCALE_MASK 0xffff0000u 57 58 #define MCHP_BTMR_CTRL_HALT 0x80u 59 #define MCHP_BTMR_CTRL_RELOAD 0x40u 60 #define MCHP_BTMR_CTRL_START 0x20u 61 #define MCHP_BTMR_CTRL_SOFT_RESET 0x10u 62 #define MCHP_BTMR_CTRL_AUTO_RESTART 0x08u 63 #define MCHP_BTMR_CTRL_COUNT_UP 0x04u 64 #define MCHP_BTMR_CTRL_ENABLE 0x01u 65 /* */ 66 #define MCHP_BTMR_CTRL_HALT_POS 7u 67 #define MCHP_BTMR_CTRL_RELOAD_POS 6u 68 #define MCHP_BTMR_CTRL_START_POS 5u 69 #define MCHP_BTMR_CTRL_SRESET_POS 4u 70 #define MCHP_BTMR_CTRL_AUTO_RESTART_POS 3u 71 #define MCHP_BTMR_CTRL_COUNT_DIR_POS 2u 72 #define MCHP_BTMR_CTRL_ENABLE_POS 0u 73 74 /** @brief Basic Timer(32 and 16 bit) registers. Total size = 20(0x14) bytes */ 75 struct btmr_regs { 76 volatile uint32_t CNT; 77 volatile uint32_t PRLD; 78 volatile uint8_t STS; 79 uint8_t RSVDC[3]; 80 volatile uint8_t IEN; 81 uint8_t RSVDD[3]; 82 volatile uint32_t CTRL; 83 }; 84 85 /* 86 * Hibernation Timer 87 * Set count resolution in bit[0] 88 * 0 = 30.5 us (32786 Hz) 89 * 1 = 125 ms (8 Hz) 90 */ 91 #define MCHP_HTMR_CTRL_REG_MASK 0x01u 92 #define MCHP_HTMR_CTRL_RESOL_POS 0u 93 #define MCHP_HTMR_CTRL_RESOL_MASK BIT(MCHP_HTMR_CTRL_EN_POS) 94 #define MCHP_HTMR_CTRL_RESOL_30US 0u 95 #define MCHP_HTMR_CTRL_RESOL_125MS BIT(MCHP_HTMR_CTRL_EN_POS) 96 97 /* 98 * Hibernation timer is started and stopped by writing a value 99 * to the CNT (count) register. 100 * Writing a non-zero value resets and start the counter counting down. 101 * Writing 0 stops the timer. 102 */ 103 #define MCHP_HTMR_CNT_STOP_VALUE 0 104 105 /** @brief Hibernation Timer (HTMR) */ 106 struct htmr_regs { 107 volatile uint16_t PRLD; 108 uint16_t RSVD1[1]; 109 volatile uint16_t CTRL; 110 uint16_t RSVD2[1]; 111 volatile uint16_t CNT; 112 uint16_t RSVD3[1]; 113 }; 114 115 /* Capture/Compare Timer */ 116 117 /* Control register at offset 0x00. Must use 32-bit access */ 118 #define MCHP_CCT_CTRL_ACTIVATE BIT(0) 119 #define MCHP_CCT_CTRL_FRUN_EN BIT(1) 120 #define MCHP_CCT_CTRL_FRUN_RESET BIT(2) /* self clearing bit */ 121 #define MCHP_CCT_CTRL_TCLK_MASK0 0x07u 122 #define MCHP_CCT_CTRL_TCLK_MASK SHLU32(MCHP_CCT_CTRL_TCLK_MASK0, 4) 123 #define MCHP_CCT_CTRL_TCLK_DIV_1 0u 124 #define MCHP_CCT_CTRL_TCLK_DIV_2 SHLU32(1, 4) 125 #define MCHP_CCT_CTRL_TCLK_DIV_4 SHLU32(2, 4) 126 #define MCHP_CCT_CTRL_TCLK_DIV_8 SHLU32(3, 4) 127 #define MCHP_CCT_CTRL_TCLK_DIV_16 SHLU32(4, 4) 128 #define MCHP_CCT_CTRL_TCLK_DIV_32 SHLU32(5, 4) 129 #define MCHP_CCT_CTRL_TCLK_DIV_64 SHLU32(6, 4) 130 #define MCHP_CCT_CTRL_TCLK_DIV_128 SHLU32(7, 4) 131 #define MCHP_CCT_CTRL_COMP0_EN BIT(8) 132 #define MCHP_CCT_CTRL_COMP1_EN BIT(9) 133 #define MCHP_CCT_CTRL_COMP1_SET BIT(16) /* R/WS */ 134 #define MCHP_CCT_CTRL_COMP0_SET BIT(17) /* R/WS */ 135 #define MCHP_CCT_CTRL_COMP1_CLR BIT(24) /* R/W1C */ 136 #define MCHP_CCT_CTRL_COMP0_CLR BIT(25) /* R/W1C */ 137 138 /** @brief Capture/Compare Timer */ 139 struct cct_regs { 140 volatile uint32_t CTRL; 141 volatile uint32_t CAP0_CTRL; 142 volatile uint32_t CAP1_CTRL; 143 volatile uint32_t FREE_RUN; 144 volatile uint32_t CAP0; 145 volatile uint32_t CAP1; 146 volatile uint32_t CAP2; 147 volatile uint32_t CAP3; 148 volatile uint32_t CAP4; 149 volatile uint32_t CAP5; 150 volatile uint32_t COMP0; 151 volatile uint32_t COMP1; 152 }; 153 154 /* RTOS Timer */ 155 #define MCHP_RTMR_FREQ_HZ 32768u 156 157 #define MCHP_RTMR_CTRL_MASK 0x1fu 158 #define MCHP_RTMR_CTRL_BLK_EN_POS 0 159 #define MCHP_RTMR_CTRL_BLK_EN_MASK BIT(MCHP_RTMR_CTRL_BLK_EN_POS) 160 #define MCHP_RTMR_CTRL_BLK_EN BIT(MCHP_RTMR_CTRL_BLK_EN_POS) 161 162 #define MCHP_RTMR_CTRL_AUTO_RELOAD_POS 1u 163 #define MCHP_RTMR_CTRL_AUTO_RELOAD_MASK BIT(MCHP_RTMR_CTRL_AUTO_RELOAD_POS) 164 #define MCHP_RTMR_CTRL_AUTO_RELOAD BIT(MCHP_RTMR_CTRL_AUTO_RELOAD_POS) 165 166 #define MCHP_RTMR_CTRL_START_POS 2u 167 #define MCHP_RTMR_CTRL_START_MASK BIT(MCHP_RTMR_CTRL_START_POS) 168 #define MCHP_RTMR_CTRL_START BIT(MCHP_RTMR_CTRL_START_POS) 169 170 #define MCHP_RTMR_CTRL_HW_HALT_EN_POS 3u 171 #define MCHP_RTMR_CTRL_HW_HALT_EN_MASK BIT(MCHP_RTMR_CTRL_HW_HALT_EN_POS) 172 #define MCHP_RTMR_CTRL_HW_HALT_EN BIT(MCHP_RTMR_CTRL_HW_HALT_EN_POS) 173 174 #define MCHP_RTMR_CTRL_FW_HALT_EN_POS 4u 175 #define MCHP_RTMR_CTRL_FW_HALT_EN_MASK BIT(MCHP_RTMR_CTRL_FW_HALT_EN_POS) 176 #define MCHP_RTMR_CTRL_FW_HALT_EN BIT(MCHP_RTMR_CTRL_FW_HALT_EN_POS) 177 178 /** @brief RTOS Timer (RTMR) */ 179 struct rtmr_regs { 180 volatile uint32_t CNT; 181 volatile uint32_t PRLD; 182 volatile uint32_t CTRL; 183 volatile uint32_t SOFTIRQ; 184 }; 185 186 /* Week Timer */ 187 #define MCHP_WKTMR_CTRL_MASK 0x41u 188 #define MCHP_WKTMR_CTRL_WT_EN_POS 0 189 #define MCHP_WKTMR_CTRL_WT_EN_MASK BIT(MCHP_WKTMR_CTRL_WT_EN_POS) 190 #define MCHP_WKTMR_CTRL_WT_EN BIT(MCHP_WKTMR_CTRL_WT_EN_POS) 191 #define MCHP_WKTMR_CTRL_PWRUP_EV_EN_POS 6u 192 #define MCHP_WKTMR_CTRL_PWRUP_EV_EN_MASK BIT(MCHP_WKTMR_CTRL_PWRUP_EV_EN_POS) 193 #define MCHP_WKTMR_CTRL_PWRUP_EV_EN BIT(MCHP_WKTMR_CTRL_PWRUP_EV_EN_POS) 194 195 #define MCHP_WKTMR_ALARM_CNT_MASK 0x0fffffffu 196 #define MCHP_WKTMR_TMR_CMP_MASK 0x0fffffffu 197 #define MCHP_WKTMR_CLK_DIV_MASK 0x7fffu 198 199 /* Sub-second interrupt select at +0x10 */ 200 #define MCHP_WKTMR_SS_MASK 0x0fu 201 #define MCHP_WKTMR_SS_RATE_DIS 0x00u 202 #define MCHP_WKTMR_SS_RATE_2HZ 0x01u 203 #define MCHP_WKTMR_SS_RATE_4HZ 0x02u 204 #define MCHP_WKTMR_SS_RATE_8HZ 0x03u 205 #define MCHP_WKTMR_SS_RATE_16HZ 0x04u 206 #define MCHP_WKTMR_SS_RATE_32HZ 0x05u 207 #define MCHP_WKTMR_SS_RATE_64HZ 0x06u 208 #define MCHP_WKTMR_SS_RATE_128HZ 0x07u 209 #define MCHP_WKTMR_SS_RATE_256HZ 0x08u 210 #define MCHP_WKTMR_SS_RATE_512HZ 0x09u 211 #define MCHP_WKTMR_SS_RATE_1024HZ 0x0au 212 #define MCHP_WKTMR_SS_RATE_2048HZ 0x0bu 213 #define MCHP_WKTMR_SS_RATE_4096HZ 0x0cu 214 #define MCHP_WKTMR_SS_RATE_8192HZ 0x0du 215 #define MCHP_WKTMR_SS_RATE_16384HZ 0x0eu 216 #define MCHP_WKTMR_SS_RATE_32768HZ 0x0fu 217 218 /* Sub-week control at +0x14 */ 219 #define MCHP_WKTMR_SWKC_MASK 0x3f3u 220 #define MCHP_WKTMR_SWKC_PWRUP_EV_STS_POS 0ul 221 #define MCHP_WKTMR_SWKC_PWRUP_EV_STS_MASK \ 222 BIT(MCHP_WKTMR_SWKC_PWRUP_EV_STS_POS) 223 #define MCHP_WKTMR_SWKC_PWRUP_EV_STS \ 224 BIT(MCHP_WKTMR_SWKC_PWRUP_EV_STS_POS) 225 #define MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_POS 4 226 #define MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_MASK \ 227 BIT(MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_POS) 228 #define MCHP_WKTMR_SWKC_SYSPWR_PRES_STS \ 229 BIT(MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_POS) 230 #define MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_POS 5 231 #define MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_MASK \ 232 BIT(MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_POS) 233 #define MCHP_WKTMR_SWKC_SYSPWR_PRES_EN \ 234 BIT(MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_POS) 235 #define MCHP_WKTMR_SWKC_AUTO_RELOAD_POS 6 236 #define MCHP_WKTMR_SWKC_AUTO_RELOAD_MASK \ 237 BIT(MCHP_WKTMR_SWKC_AUTO_RELOAD_POS) 238 #define MCHP_WKTMR_SWKC_AUTO_RELOAD \ 239 BIT(MCHP_WKTMR_SWKC_AUTO_RELOAD_POS) 240 241 /* Sub-week alarm counter at +0x18 */ 242 #define MCHP_WKTMR_SWAC_MASK 0x1ff01ffu 243 #define MCHP_WKTMR_SWAC_LOAD_POS 0 244 #define MCHP_WKTMR_SWAC_CNT_RO_POS 16 245 #define MCHP_WKTMR_SWAC_LOAD_MASK GENMASK(8, 0) 246 #define MCHP_WKTMR_SWAC_CNT_RO_MASK GENMASK(24, 16) 247 248 /* Week timer BGPO Data at +0x1c */ 249 #define MCHP_WKTMR_BGPO_DATA_MASK GENMASK(5, 0) 250 251 /* Week timer BGPO Power at +0x20 */ 252 #define MCHP_WKTMR_BGPO_PWR_MASK GENMASK(5, 0) 253 #define MCHP_WKTMR_BGPO_0_PWR_RO BIT(0) 254 255 /* Week timer BGPO Reset at +0x24 */ 256 #define MCHP_WKTMR_BGPO_RST_MASK GENMASK(5, 0) 257 #define MCHP_WKTMR_BGPO_RST_VBAT(n) BIT(n) 258 259 /** @brief Week Timer (WKTMR) */ 260 struct wktmr_regs { 261 volatile uint32_t CTRL; 262 volatile uint32_t ALARM_CNT; 263 volatile uint32_t TMR_CMP; 264 volatile uint32_t CLKDIV; 265 volatile uint32_t SUBSEC_ISEL; 266 volatile uint32_t SUBWK_CTRL; 267 volatile uint32_t SUBWK_ALARM_CNT; 268 volatile uint32_t BGPO_DATA; 269 volatile uint32_t BGPO_PWR; 270 volatile uint32_t BGPO_RST; 271 }; 272 273 #endif /* #ifndef _MEC_TIMERS_H */ 274
