1 /* 2 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MEC172X_VBAT_H 8 #define _MEC172X_VBAT_H 9 10 #include <stdint.h> 11 #include <stddef.h> 12 13 /* VBAT Registers Registers */ 14 #define MCHP_VBAT_MEMORY_SIZE 128u 15 16 /* Offset 0x00 Power-Fail and Reset Status */ 17 #define MCHP_VBATR_PFRS_OFS 0u 18 #define MCHP_VBATR_PFRS_MASK 0x7cu 19 #define MCHP_VBATR_PFRS_SYS_RST_POS 2u 20 #define MCHP_VBATR_PFRS_JTAG_POS 3u 21 #define MCHP_VBATR_PFRS_RESETI_POS 4u 22 #define MCHP_VBATR_PFRS_WDT_POS 5u 23 #define MCHP_VBATR_PFRS_SYSRESETREQ_POS 6u 24 #define MCHP_VBATR_PFRS_VBAT_RST_POS 7u 25 26 #define MCHP_VBATR_PFRS_SYS_RST BIT(2) 27 #define MCHP_VBATR_PFRS_JTAG BIT(3) 28 #define MCHP_VBATR_PFRS_RESETI BIT(4) 29 #define MCHP_VBATR_PFRS_WDT BIT(5) 30 #define MCHP_VBATR_PFRS_SYSRESETREQ BIT(6) 31 #define MCHP_VBATR_PFRS_VBAT_RST BIT(7) 32 33 /* Offset 0x08 32K Clock Source register */ 34 #define MCHP_VBATR_CS_OFS 0x08u 35 #define MCHP_VBATR_CS_MASK 0x71f1u 36 #define MCHP_VBATR_CS_SO_EN_POS 0 37 #define MCHP_VBATR_CS_XTAL_EN_POS 8 38 #define MCHP_VBATR_CS_XTAL_SEL_POS 9 39 #define MCHP_VBATR_CS_XTAL_DHC_POS 10 40 #define MCHP_VBATR_CS_XTAL_CNTR_POS 11 41 #define MCHP_VBATR_CS_PCS_POS 16 42 #define MCHP_VBATR_CS_DI32_VTR_OFF_POS 18 43 44 /* Enable and start internal 32KHz Silicon Oscillator */ 45 #define MCHP_VBATR_CS_SO_EN BIT(0) 46 /* Enable and start the external crystal */ 47 #define MCHP_VBATR_CS_XTAL_EN BIT(8) 48 /* single ended crystal on XTAL2 instead of parallel across XTAL1 and XTAL2 */ 49 #define MCHP_VBATR_CS_XTAL_SE BIT(9) 50 /* disable XTAL high startup current */ 51 #define MCHP_VBATR_CS_XTAL_DHC BIT(10) 52 /* crystal amplifier gain control */ 53 #define MCHP_VBATR_CS_XTAL_CNTR_MSK 0x1800u 54 #define MCHP_VBATR_CS_XTAL_CNTR_DG 0x0800u 55 #define MCHP_VBATR_CS_XTAL_CNTR_RG 0x1000u 56 #define MCHP_VBATR_CS_XTAL_CNTR_MG 0x1800u 57 /* Select source of peripheral 32KHz clock */ 58 #define MCHP_VBATR_CS_PCS_POS 16 59 #define MCHP_VBATR_CS_PCS_MSK 0x30000u 60 #define MCHP_VBATR_CS_PCR_VTR_VBAT_SO_VAL 0 61 #define MCHP_VBATR_CS_PCS_VTR_VBAT_XTAL_VAL 1 62 #define MCHP_VBATR_CS_PCS_VTR_PIN_SO_VAL 2 63 #define MCHP_VBATR_CS_PCS_VTR_PIN_XTAL_VAL 3 64 /* 32K silicon OSC when chip powered by VBAT or VTR */ 65 #define MCHP_VBATR_CS_PCS_VTR_VBAT_SO 0u 66 /* 32K external crystal when chip powered by VBAT or VTR */ 67 #define MCHP_VBATR_CS_PCS_VTR_VBAT_XTAL 0x10000u 68 /* 32K input pin on VTR. Switch to Silicon OSC on VBAT */ 69 #define MCHP_VBATR_CS_PCS_VTR_PIN_SO 0x20000u 70 /* 32K input pin on VTR. Switch to crystal on VBAT */ 71 #define MCHP_VBATR_CS_PCS_VTR_PIN_XTAL 0x30000u 72 /* Disable internal 32K VBAT clock source when VTR is off */ 73 #define MCHP_VBATR_CS_DI32_VTR_OFF_POS 18 74 #define MCHP_VBATR_CS_DI32_VTR_OFF BIT(18) 75 76 /* 77 * Monotonic Counter least significant word (32-bit), read-only. 78 * Increments by one on read. 79 */ 80 #define MCHP_VBATR_MCNT_LSW_OFS 0x20u 81 82 /* Monotonic Counter most significant word (32-bit). Read-Write */ 83 #define MCHP_VBATR_MCNT_MSW_OFS 0x24u 84 85 /* ROM Feature register */ 86 #define MCHP_VBATR_ROM_FEAT_OFS 0x28u 87 88 /* Embedded Reset Debounce Enable register */ 89 #define MCHP_VBATR_EMBRD_EN_OFS 0x34u 90 #define MCHP_VBATR_EMBRD_EN BIT(0) 91 92 /** @brief VBAT Register Bank (VBATR) */ 93 struct vbatr_regs { 94 volatile uint32_t PFRS; 95 uint32_t RSVD1[1]; 96 volatile uint32_t CLK32_SRC; 97 uint32_t RSVD2[5]; 98 volatile uint32_t MCNT_LO; 99 volatile uint32_t MCNT_HI; 100 uint32_t RSVD3[3]; 101 volatile uint32_t EMBRD_EN; 102 }; 103 104 #endif /* #ifndef _MEC172X_VBAT_H */ 105
