1 /* 2 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <stdint.h> 8 #include <stddef.h> 9 10 #ifndef _MEC172X_PCR_H 11 #define _MEC172X_PCR_H 12 13 #define MCHP_PCR_SYS_SLP_CTRL_OFS 0x00u 14 #define MCHP_PCR_SYS_CLK_CTRL_OFS 0x04u 15 #define MCHP_PCR_SLOW_CLK_CTRL_OFS 0x08u 16 #define MCHP_PCR_OSC_ID_OFS 0x0cu 17 #define MCHP_PCR_PRS_OFS 0x10u 18 #define MCHP_PCR_PR_CTRL_OFS 0x14u 19 #define MCHP_PCR_SYS_RESET_OFS 0x18u 20 #define MCHP_PCR_PKE_CLK_CTRL_OFS 0x1cu 21 #define MCHP_PCR_SLP_EN0_OFS 0x30u 22 #define MCHP_PCR_SLP_EN1_OFS 0x34u 23 #define MCHP_PCR_SLP_EN2_OFS 0x38u 24 #define MCHP_PCR_SLP_EN3_OFS 0x3cu 25 #define MCHP_PCR_SLP_EN4_OFS 0x40u 26 #define MCHP_PCR_CLK_REQ0_OFS 0x50u 27 #define MCHP_PCR_CLK_REQ1_OFS 0x54u 28 #define MCHP_PCR_CLK_REQ2_OFS 0x58u 29 #define MCHP_PCR_CLK_REQ3_OFS 0x5cu 30 #define MCHP_PCR_CLK_REQ4_OFS 0x60u 31 #define MCHP_PCR_PERIPH_RST0_OFS 0x70u 32 #define MCHP_PCR_PERIPH_RST1_OFS 0x74u 33 #define MCHP_PCR_PERIPH_RST2_OFS 0x78u 34 #define MCHP_PCR_PERIPH_RST3_OFS 0x7cu 35 #define MCHP_PCR_PERIPH_RST4_OFS 0x80u 36 #define MCHP_PCR_PERIPH_RST_LCK_OFS 0x84u 37 #define MCHP_PCR_VBAT_SRST_OFS 0x88u 38 #define MCHP_PCR_CLK32K_SRC_VTR_OFS 0x8cu 39 #define MCHP_PCR_CNT32K_PER_OFS 0xc0u 40 #define MCHP_PCR_CNT32K_PULSE_HI_OFS 0xc4u 41 #define MCHP_PCR_CNT32K_PER_MIN_OFS 0xc8u 42 #define MCHP_PCR_CNT32K_PER_MAX_OFS 0xccu 43 #define MCHP_PCR_CNT32K_DV_OFS 0xd0u 44 #define MCHP_PCR_CNT32K_DV_MAX_OFS 0xd4u 45 #define MCHP_PCR_CNT32K_VALID_OFS 0xd8u 46 #define MCHP_PCR_CNT32K_VALID_MIN_OFS 0xdcu 47 #define MCHP_PCR_CNT32K_CTRL_OFS 0xe0u 48 #define MCHP_PCR_CLK32K_MON_ISTS_OFS 0xe4u 49 #define MCHP_PCR_CLK32K_MON_IEN_OFS 0xe8u 50 51 /* 52 * MEC172x PCR implements multiple SLP_EN, CLR_REQ, and RST_EN registers. 53 * CLK_REQ bits are read-only. The peripheral sets its CLK_REQ if it requires 54 * clocks. CLK_REQ bits must all be zero for the PCR block to put the MEC17xx 55 * into light or heavy sleep. 56 * SLP_EN bit = 1 instructs HW to gate off clock tree to peripheral only if 57 * peripherals PCR CLK_REQ bit is 0. 58 * RST_EN bit = 1 will reset the peripheral at any time. The RST_EN registers 59 * must be unlocked by writing the unlock code to PCR Peripheral Reset Lock 60 * register. 61 * SLP_EN usage is: 62 * Initialization set all PCR SLP_EN bits = 0 except for crypto blocks as 63 * these IP do not implement internal clock gating. 64 * When firmware wants to enter light or heavy sleep. 65 * Configure wake up source(s) 66 * Write MCHP_PCR_SYS_SLP_CTR register to value based on light/heavy with 67 * SLEEP_ALL bit = 1. 68 * Execute Cortex-M4 WFI sequence. DSB(), ISB(), WFI(), NOP() 69 * Cortex-M4 will assert sleep signal to PCR block. 70 * PCR HW will spin until all CLK_REQ==0 71 * PCR will then turn off clocks based on light/heavy sleep. 72 * 73 * RST_EN usage is: 74 * Save and disable maskable interrupts 75 * Write unlock code to PCR Peripheral Reset Lock 76 * Write bit patterns to one or more of PCR RST_EN[0, 4] registers 77 * Selected peripherals will be reset. 78 * Write lock code to PCR Peripheral Reset Lock. 79 * Restore interrupts. 80 */ 81 #define MCHP_MAX_PCR_SCR_REGS 5u 82 83 /* VTR Powered PCR registers */ 84 #define MCHP_PCR_SLP(bitpos) BIT(bitpos) 85 86 /* PCR System Sleep Control */ 87 #define MCHP_PCR_SYS_SLP_CTRL_MASK 0x0109u 88 #define MCHP_PCR_SYS_SLP_CTRL_SLP_HEAVY BIT(0) 89 #define MCHP_PCR_SYS_SLP_CTRL_SLP_ALL BIT(3) 90 /* 91 * bit[8] can be used to prevent entry to heavy sleep unless the 92 * PLL is locked. 93 * bit[8]==0 (POR default) system will allow entry to light or heavy 94 * sleep if and only if PLL is locked. 95 * bit[8]==1 system will allow entry to heavy sleep before PLL is locked. 96 */ 97 #define MCHP_PCR_SYS_SLP_CTRL_ALLOW_SLP_NO_PLL_LOCK BIT(8) 98 99 /* Assert all peripheral sleep enables once CPU asserts its sleep signal */ 100 #define MCHP_PCR_SYS_SLP_LIGHT BIT(3) 101 #define MCHP_PCR_SYS_SLP_HEAVY (BIT(3) | BIT(0)) 102 103 /* 104 * PCR Process Clock Control 105 * Divides 96MHz clock to ARM Cortex-M4 core including 106 * SysTick and NVIC. 107 */ 108 #define MCHP_PCR_PROC_CLK_CTRL_MASK GENMASK(7, 0) 109 #define MCHP_PCR_PROC_CLK_CTRL_96MHZ 1 110 #define MCHP_PCR_PROC_CLK_CTRL_48MHZ 2 111 #define MCHP_PCR_PROC_CLK_CTRL_24MHZ 4 112 #define MCHP_PCR_PROC_CLK_CTRL_12MHZ 8 113 #define MCHP_PCR_PROC_CLK_CTRL_6MHZ 16 114 #define MCHP_PCR_PROC_CLK_CTRL_2MHZ 48 115 #define MCHP_PCR_PROC_CLK_CTRL_DFLT MCHP_PCR_PROC_CLK_CTRL_24MHZ 116 117 /* PCR Slow Clock Control. Clock divider for 100KHz clock domain */ 118 #define MCHP_PCR_SLOW_CLK_CTRL_MASK GENMASK(9, 0) 119 #define MCHP_PCR_SLOW_CLK_CTRL_100KHZ 0x1e0u 120 121 /* PCR Oscillator ID register (Read-Only) */ 122 #define MCHP_PCR_OSC_ID_MASK GENMASK(8, 0) 123 #define MCHP_PCR_OSC_ID_PLL_LOCK BIT(8) 124 125 /* PCR Power Reset Status Register */ 126 #define MCHP_PCR_PRS_MASK \ 127 (GENMASK(11, 10) | GENMASK(8, 2)) 128 #define MCHP_PCR_PRS_VCC_PWRGD_STATE_RO BIT(2) 129 #define MCHP_PCR_PRS_HOST_RESET_STATE_RO BIT(3) 130 #define MCHP_PCR_PRS_VTR_RST_RWC BIT(4) 131 #define MCHP_PCR_PRS_VBAT_RST_RWC BIT(5) 132 #define MCHP_PCR_PRS_RST_SYS_RWC BIT(6) 133 #define MCHP_PCR_PRS_JTAG_RST_RO BIT(7) 134 #define MCHP_PCR_PRS_WDT_EVENT_RWC BIT(8) 135 #define MCHP_PCR_PRS_32K_ACTIVE_RO BIT(10) 136 #define MCHP_PCR_PRS_LPC_ESPI_CLK_ACTIVE_RO BIT(11) 137 138 /* PCR Power Reset Control Register */ 139 #define MCHP_PCR_PR_CTRL_MASK (BIT(8) | BIT(0)) 140 #define MCHP_PCR_PR_CTRL_PWR_INV BIT(0) 141 #define MCHP_PCR_PR_CTRL_USE_ESPI_PLTRST 0u 142 #define MCHP_PCR_PR_CTRL_USE_PCI_RST BIT(8) 143 144 /* PCR System Reset Register */ 145 #define MCHP_PCR_SYS_RESET_MASK BIT(8) 146 #define MCHP_PCR_SYS_RESET_NOW BIT(8) 147 148 /* Turbo Clock Register */ 149 #define MCHP_PCR_TURBO_CLK_MASK BIT(2) 150 #define MCHP_PCR_TURBO_CLK_96M BIT(2) 151 152 /* 153 * Sleep Enable Reg 0 (Offset +30h) 154 * Clock Required Reg 0 (Offset +50h) 155 * Reset Enable Reg 0 (Offset +70h) 156 */ 157 #define MCHP_PCR0_JTAG_STAP_POS 0 158 #define MCHP_PCR0_OTP_POS 1 159 #define MCHP_PCR0_ISPI_EMC_POS 2 160 161 /* 162 * Sleep Enable Reg 1 (Offset +34h) 163 * Clock Required Reg 1 (Offset +54h) 164 * Reset Enable Reg 1 (Offset +74h) 165 */ 166 #define MCHP_PCR1_ECIA_POS 0 167 #define MCHP_PCR1_PECI_POS 1 168 #define MCHP_PCR1_TACH0_POS 2 169 #define MCHP_PCR1_PWM0_POS 4 170 #define MCHP_PCR1_PMC_POS 5 171 #define MCHP_PCR1_DMA_POS 6 172 #define MCHP_PCR1_TFDP_POS 7 173 #define MCHP_PCR1_CPU_POS 8 174 #define MCHP_PCR1_WDT_POS 9 175 #define MCHP_PCR1_SMB0_POS 10 176 #define MCHP_PCR1_TACH1_POS 11 177 #define MCHP_PCR1_TACH2_POS 12 178 #define MCHP_PCR1_TACH3_POS 13 179 #define MCHP_PCR1_PWM1_POS 20 180 #define MCHP_PCR1_PWM2_POS 21 181 #define MCHP_PCR1_PWM3_POS 22 182 #define MCHP_PCR1_PWM4_POS 23 183 #define MCHP_PCR1_PWM5_POS 24 184 #define MCHP_PCR1_PWM6_POS 25 185 #define MCHP_PCR1_PWM7_POS 26 186 #define MCHP_PCR1_PWM8_POS 27 187 #define MCHP_PCR1_ECS_POS 29 188 #define MCHP_PCR1_B16TMR0_POS 30 189 #define MCHP_PCR1_B16TMR1_POS 31 190 191 /* 192 * Sleep Enable Reg 2 (Offset +38h) 193 * Clock Required Reg 2 (Offset +58h) 194 * Reset Enable Reg 2 (Offset +78h) 195 */ 196 #define MCHP_PCR2_EMI0_POS 0 197 #define MCHP_PCR2_UART0_POS 1 198 #define MCHP_PCR2_UART1_POS 2 199 #define MCHP_PCR2_GCFG_POS 12 200 #define MCHP_PCR2_ACPI_EC0_POS 13 201 #define MCHP_PCR2_ACPI_EC1_POS 14 202 #define MCHP_PCR2_ACPI_PM1_POS 15 203 #define MCHP_PCR2_KBC_POS 16 204 #define MCHP_PCR2_MBOX_POS 17 205 #define MCHP_PCR2_RTC_POS 18 206 #define MCHP_PCR2_ESPI_POS 19 207 #define MCHP_PCR2_SCR32_POS 20 208 #define MCHP_PCR2_ACPI_EC2_POS 21 209 #define MCHP_PCR2_ACPI_EC3_POS 22 210 #define MCHP_PCR2_ACPI_EC4_POS 23 211 #define MCHP_PCR2_P80BD_POS 25 212 #define MCHP_PCR2_ESPI_SAF_POS 27 213 #define MCHP_PCR2_GLUE_POS 29 214 215 /* 216 * Sleep Enable Reg 3 (Offset +3Ch) 217 * Clock Required Reg 3 (Offset +5Ch) 218 * Reset Enable Reg 3 (Offset +7Ch) 219 */ 220 #define MCHP_PCR3_ADC_POS 3 221 #define MCHP_PCR3_PS2_0_POS 5 222 #define MCHP_PCR3_GPSPI0_POS 9 223 #define MCHP_PCR3_HTMR0_POS 10 224 #define MCHP_PCR3_KEYSCAN_POS 11 225 #define MCHP_PCR3_RPMFAN0_POS 12 226 #define MCHP_PCR3_SMB1_POS 13 227 #define MCHP_PCR3_SMB2_POS 14 228 #define MCHP_PCR3_SMB3_POS 15 229 #define MCHP_PCR3_LED0_POS 16 230 #define MCHP_PCR3_LED1_POS 17 231 #define MCHP_PCR3_LED2_POS 18 232 #define MCHP_PCR3_BCL0_POS 19 233 #define MCHP_PCR3_SMB4_POS 20 234 #define MCHP_PCR3_B16TMR2_POS 21 235 #define MCHP_PCR3_B16TMR3_POS 22 236 #define MCHP_PCR3_B32TMR0_POS 23 237 #define MCHP_PCR3_B32TMR1_POS 24 238 #define MCHP_PCR3_LED3_POS 25 239 #define MCHP_PCR3_CRYPTO_POS 26 240 #define MCHP_PCR3_HTMR1_POS 29 241 #define MCHP_PCR3_CCT_POS 30 242 #define MCHP_PCR3_PWM9_POS 31 243 244 #define MCHP_PCR3_CRYPTO_MASK BIT(MCHP_PCR3_CRYPTO_POS) 245 246 /* 247 * Sleep Enable Reg 4 (Offset +40h) 248 * Clock Required Reg 4 (Offset +60h) 249 * Reset Enable Reg 4 (Offset +80h) 250 */ 251 #define MCHP_PCR4_PWM10_POS 0 252 #define MCHP_PCR4_PWM11_POS 1 253 #define MCHP_CTMR0_POS 2 254 #define MCHP_CTMR1_POS 3 255 #define MCHP_CTMR2_POS 4 256 #define MCHP_CTMR3_POS 5 257 #define MCHP_PCR4_RTMR_POS 6 258 #define MCHP_PCR4_RPMFAN1_POS 7 259 #define MCHP_PCR4_QMSPI_POS 8 260 #define MCHP_PCR4_RCID0_POS 10 261 #define MCHP_PCR4_RCID1_POS 11 262 #define MCHP_PCR4_RCID2_POS 12 263 #define MCHP_PCR4_PHOT_POS 13 264 #define MCHP_PCR4_EEPROM_POS 14 265 #define MCHP_PCR4_SPIP_POS 16 266 #define MCHP_PCR4_GPSPI1_POS 22 267 268 /* Reset Enable Lock (Offset +84h) */ 269 #define MCHP_PCR_RSTEN_UNLOCK 0xa6382d4cu 270 #define MCHP_PCR_RSTEN_LOCK 0xa6382d4du 271 272 /* VBAT Soft Reset (Offset +88h) */ 273 #define MCHP_PCR_VBSR_MASK BIT(0) 274 #define MCHP_PCR_VBSR_EN BIT(0) /* self clearing */ 275 276 /* VTR Source 32 KHz Clock (Offset +8Ch) */ 277 #define MCHP_PCR_VTR_32K_SRC_MASK GENMASK(1, 0) 278 #define MCHP_PCR_VTR_32K_SRC_SILOSC 0u 279 #define MCHP_PCR_VTR_32K_SRC_XTAL BIT(0) 280 #define MCHP_PCR_VTR_32K_SRC_PIN BIT(1) 281 #define MCHP_PCR_VTR_32K_SRC_NONE (BIT(0) | BIT(1)) 282 283 /* 284 * Clock monitor 32KHz period counter (Offset +C0h, RO) 285 * Clock monitor 32KHz high counter (Offset +C4h, RO) 286 * Clock monitor 32KHz period counter minimum (Offset +C8h, RW) 287 * Clock monitor 32KHz period counter maximum (Offset +CCh, RW) 288 * Clock monitor 32KHz Duty Cycle variation counter (Offset +D0h, RO) 289 * Clock monitor 32KHz Duty Cycle variation counter maximum (Offset +D4h, RW) 290 */ 291 #define MCHP_PCR_CLK32M_CNT_MASK GENMASK(15, 0) 292 293 /* 294 * Clock monitor 32KHz Valid Count (Offset +0xD8, RO) 295 * Clock monitor 32KHz Valid Count minimum (Offset +0xDC, RW) 296 */ 297 #define MCHP_PCR_CLK32M_VALID_CNT_MASK GENMASK(7, 0) 298 299 /* Clock monitor control register (Offset +0xE0, RW) */ 300 #define MCHP_PCR_CLK32M_CTRL_MASK (BIT(24) | BIT(4) | GENMASK(2, 0)) 301 #define MCHP_PCR_CLK32M_CTRL_PER_EN BIT(0) 302 #define MCHP_PCR_CLK32M_CTRL_DC_EN BIT(1) 303 #define MCHP_PCR_CLK32M_CTRL_VAL_EN BIT(2) 304 #define MCHP_PCR_CLK32M_CTRL_SRC_SO BIT(4) 305 #define MCHP_PCR_CLK32M_CTRL_CLR_CNT BIT(24) 306 307 /* Clock monitor interrupt status (Offset +0xE4, R/W1C) */ 308 #define MCHP_PCR_CLK32M_ISTS_MASK GENMASK(6, 0) 309 #define MCHP_PCR_CLK32M_ISTS_PULSE_RDY BIT(0) 310 #define MCHP_PCR_CLK32M_ISTS_PASS_PER BIT(1) 311 #define MCHP_PCR_CLK32M_ISTS_PASS_DC BIT(2) 312 #define MCHP_PCR_CLK32M_ISTS_FAIL BIT(3) 313 #define MCHP_PCR_CLK32M_ISTS_STALL BIT(4) 314 #define MCHP_PCR_CLK32M_ISTS_VALID BIT(5) 315 #define MCHP_PCR_CLK32M_ISTS_UNWELL BIT(6) 316 317 /* Clock monitor interrupt enable (Offset +0xE8, RW) */ 318 #define MCHP_PCR_CLK32M_IEN_MASK GENMASK(6, 0) 319 #define MCHP_PCR_CLK32M_IEN_PULSE_RDY BIT(0) 320 #define MCHP_PCR_CLK32M_IEN_PASS_PER BIT(1) 321 #define MCHP_PCR_CLK32M_IEN_PASS_DC BIT(2) 322 #define MCHP_PCR_CLK32M_IEN_FAIL BIT(3) 323 #define MCHP_PCR_CLK32M_IEN_STALL BIT(4) 324 #define MCHP_PCR_CLK32M_IEN_VALID BIT(5) 325 #define MCHP_PCR_CLK32M_IEN_UNWELL BIT(6) 326 327 /* PCR 32KHz clock monitor uses 48 MHz for all counters */ 328 #define MCHP_PCR_CLK32M_CLOCK 48000000u 329 330 struct pcr_regs { 331 volatile uint32_t SYS_SLP_CTRL; 332 volatile uint32_t PROC_CLK_CTRL; 333 volatile uint32_t SLOW_CLK_CTRL; 334 volatile uint32_t OSC_ID; 335 volatile uint32_t PWR_RST_STS; 336 volatile uint32_t PWR_RST_CTRL; 337 volatile uint32_t SYS_RST; 338 volatile uint32_t TURBO_CLK; 339 volatile uint32_t TEST20; 340 uint32_t RSVD1[3]; 341 volatile uint32_t SLP_EN[5]; 342 uint32_t RSVD2[3]; 343 volatile uint32_t CLK_REQ[5]; 344 uint32_t RSVD3[3]; 345 volatile uint32_t RST_EN[5]; 346 volatile uint32_t RST_EN_LOCK; 347 volatile uint32_t VBAT_SRST; 348 volatile uint32_t CLK32K_SRC_VTR; 349 volatile uint32_t TEST90; 350 uint32_t RSVD4[(0x00c0 - 0x0094) / 4]; 351 volatile uint32_t CNT32K_PER; 352 volatile uint32_t CNT32K_PULSE_HI; 353 volatile uint32_t CNT32K_PER_MIN; 354 volatile uint32_t CNT32K_PER_MAX; 355 volatile uint32_t CNT32K_DV; 356 volatile uint32_t CNT32K_DV_MAX; 357 volatile uint32_t CNT32K_VALID; 358 volatile uint32_t CNT32K_VALID_MIN; 359 volatile uint32_t CNT32K_CTRL; 360 volatile uint32_t CLK32K_MON_ISTS; 361 volatile uint32_t CLK32K_MON_IEN; 362 }; 363 364 #endif /* #ifndef _MEC172X_PCR_H */ 365
