1 /*
2  * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include <stdint.h>
8 #include <stddef.h>
9 
10 #ifndef _MEC172X_ECS_H
11 #define _MEC172X_ECS_H
12 
13 /* AHB Error Address, write any value to clear */
14 #define MCHP_ECS_AHB_ERR_ADDR_OFS	0x04u
15 
16 /* AHB Error Control */
17 #define MCHP_ECS_AHB_ERR_CTRL_OFS	0x14u
18 #define MCHP_ECS_AHB_ERR_CTRL_DIS_POS	0
19 #define MCHP_ECS_AHB_ERR_CTRL_DIS	BIT(MCHP_ECS_AHB_ERR_CTRL_DIS_POS)
20 
21 /* Interrupt Control */
22 #define MCHP_ECS_ICTRL_OFS		0x18u
23 #define MCHP_ECS_ICTRL_DIRECT_POS	0
24 #define MCHP_ECS_ICTRL_DIRECT_EN	BIT(MCHP_ECS_ICTRL_DIRECT_POS)
25 
26 /* ETM Control Register */
27 #define MCHP_ECS_ETM_CTRL_OFS		0x1cu
28 #define MCHP_ECS_ETM_CTRL_EN_POS	0
29 #define MCHP_ECS_ETM_CTRL_EN		BIT(MCHP_ECS_ETM_CTRL_EN_POS)
30 
31 /* Debug Control Register */
32 #define MCHP_ECS_DCTRL_OFS		0x20u
33 #define MCHP_ECS_DCTRL_MASK		0x1fu
34 #define MCHP_ECS_DCTRL_DBG_EN_POS	0u
35 #define MCHP_ECS_DCTRL_DBG_EN		BIT(MCHP_ECS_DCTRL_DBG_EN_POS)
36 #define MCHP_ECS_DCTRL_MODE_POS		1u
37 #define MCHP_ECS_DCTRL_MODE_MASK0	0x03u
38 #define MCHP_ECS_DCTRL_MODE_MASK \
39 	SHLU32(MCHP_ECS_DCTRL_DBG_MODE_MASK0, MCHP_ECS_DCTRL_DBG_MODE_POS)
40 
41 #define MCHP_ECS_DCTRL_DBG_MODE_POS	1u
42 #define MCHP_ECS_DCTRL_MODE_JTAG	0x00u
43 #define MCHP_ECS_DCTRL_MODE_SWD		SHLU32(0x02u, 1u)
44 #define MCHP_ECS_DCTRL_MODE_SWD_SWV	SHLU32(0x01u, 1u)
45 #define MCHP_ECS_DCTRL_PUEN_POS		3u
46 #define MCHP_ECS_DCTRL_PUEN		BIT(MCHP_ECS_DCTRL_PUEN_POS)
47 #define MCHP_ECS_DCTRL_BSCAN_POS	4u
48 #define MCHP_ECS_DCTRL_BSCAN_EN		BIT(MCHP_ECS_DCTRL_BSCAN_POS)
49 
50 /* WDT Event Count */
51 #define MCHP_ECS_WDT_EVC_OFS		0x28u
52 #define MCHP_ECS_WDT_EVC_MASK		0x0fu
53 
54 /* PECI Disable */
55 #define MCHP_ECS_PECI_DIS_OFS		0x40u
56 #define MCHP_ECS_PECI_DIS_MASK		0x01u
57 #define MCHP_ECS_PECI_DIS_POS		0
58 #define MCHP_ECS_PECI_DISABLE		BIT(0)
59 
60 /* VCI FW Override */
61 #define MCHP_ECS_VCI_FW_OVR_OFS		0x50u
62 #define MCHP_ECS_VCI_FW_OVR_MASK	0x01u
63 #define MCHP_ECS_VCI_FW_OVR_SSHD_POS	0
64 #define MCHP_ECS_VCI_FW_OVR_SSHD	BIT(0)
65 
66 /* Boot-ROM Status */
67 #define MCHP_ECS_BROM_STS_OFS		0x54u
68 #define MCHP_ECS_BROM_STS_MASK		0x03u
69 #define MCHP_ECS_BROM_STS_VTR_POS	0
70 #define MCHP_ECS_BROM_STS_WDT_POS	1
71 #define MCHP_ECS_BROM_STS_VTR		BIT(0)
72 #define MCHP_ECS_BROM_STS_WDT		BIT(1)
73 
74 /* JTAG Controller Config */
75 #define MCHP_ECS_JTCC_OFS		0x70u
76 #define MCHP_ECS_JTCC_MASK		0x0fu
77 #define MCHP_ECS_JTCC_CLK_POS		0
78 #define MCHP_ECS_JTCC_CLK_DFLT		3u
79 #define MCHP_ECS_JTCC_CLK_24M		1u
80 #define MCHP_ECS_JTCC_CLK_12M		2u
81 #define MCHP_ECS_JTCC_CLK_6M		3u
82 #define MCHP_ECS_JTCC_CLK_3M		4u
83 #define MCHP_ECS_JTCC_CLK_1500K		5u
84 #define MCHP_ECS_JTCC_CLK_750K		6u
85 #define MCHP_ECS_JTCC_CLK_375K		7u
86 #define MCHP_ECS_JTCC_MS_POS		3
87 #define MCHP_ECS_JTCC_M			BIT(3)
88 
89 /* JTAG Controller Status */
90 #define MCHP_ECS_JTST_OFS		0x74u
91 #define MCHP_ECS_JTST_MASK		0x01u
92 #define MCHP_ECS_JTST_DONE		BIT(0)
93 
94 #define MCHP_ECS_JT_TDO_OFS		0x78u
95 #define MCHP_ECS_JT_TDI_OFS		0x7cu
96 #define MCHP_ECS_JT_TMS_OFS		0x80u
97 
98 /* JTAG Controller Command */
99 #define MCHP_ECS_JT_CMD_OFS		0x84u
100 #define MCHP_ECS_JT_CMD_MASK		0x1fu
101 
102 /* VWire Source Configuration */
103 #define MCHP_ECS_VWSC_OFS		0x90u
104 #define MCHP_ECS_VWSC_MASK		0x07u
105 #define MCHP_ECS_VWSC_DFLT		0x07u
106 #define MCHP_ECS_VWSC_EC_SCI_DIS	BIT(0)
107 #define MCHP_ECS_VWSC_MBH_SMI_DIS	BIT(1)
108 
109 /* Analog Comparator Control */
110 #define MCHP_ECS_ACC_OFS		0x94u
111 #define MCHP_ECS_ACC_MASK		0x15u
112 #define MCHP_ECS_ACC_EN0		BIT(0)
113 #define MCHP_ECS_ACC_CFG_LOCK0		BIT(2)
114 #define MCHP_ECS_ACC_EN1		BIT(4)
115 
116 /* Analog Comparator Sleep Control */
117 #define MCHP_ECS_ACSC_OFS		0x98u
118 #define MCHP_ECS_ACSC_MASK		0x03u
119 #define MCHP_ECS_ACSC_DSLP_EN0		BIT(0)
120 #define MCHP_ECS_ACSC_DSLP_EN1		BIT(1)
121 
122 /* Embedded Reset Enable */
123 #define MCHP_ECS_EMBR_EN_OFS		0xb0u
124 #define MCHP_ECS_EMBR_EN_MASK		0x01u
125 #define MCHP_ECS_EMBR_EN_ON		BIT(0)
126 
127 /* Embedded Reset Timeout value */
128 #define MCHP_ECS_EMBR_TMOUT_OFS		0xb4u
129 #define MCHP_ECS_EMBR_TMOUT_MASK	0x07u
130 #define MCHP_ECS_EMBR_TMOUT_6S		0u
131 #define MCHP_ECS_EMBR_TMOUT_7S		1u
132 #define MCHP_ECS_EMBR_TMOUT_8S		2u
133 #define MCHP_ECS_EMBR_TMOUT_9S		3u
134 #define MCHP_ECS_EMBR_TMOUT_10S		4u
135 #define MCHP_ECS_EMBR_TMOUT_11S		5u
136 #define MCHP_ECS_EMBR_TMOUT_12S		6u
137 #define MCHP_ECS_EMBR_TMOUT_14S		7u
138 
139 /* Embedded Reset Status */
140 #define MCHP_ECS_EMBR_STS_OFS		0xb8u
141 #define MCHP_ECS_EMBR_STS_MASK		0x01u
142 #define MCHP_ECS_EMBR_STS_RST		BIT(0)
143 
144 /* Embedded Reset Count (RO) */
145 #define MCHP_ECS_EMBR_CNT_OFS		0xbcu
146 #define MCHP_ECS_EMBR_CNT_MASK		0x7ffffu
147 
148 /**  @brief EC Subsystem (ECS) */
149 struct ecs_regs {
150 	uint32_t RSVD1[1];
151 	volatile uint32_t AHB_ERR_ADDR;		/* +0x04 */
152 	uint32_t RSVD2[2];
153 	volatile uint32_t OSC_ID;		/* +0x10 */
154 	volatile uint32_t AHB_ERR_CTRL;		/* +0x14 */
155 	volatile uint32_t INTR_CTRL;		/* +0x18 */
156 	volatile uint32_t ETM_CTRL;		/* +0x1c */
157 	volatile uint32_t DEBUG_CTRL;		/* +0x20 */
158 	volatile uint32_t OTP_LOCK;		/* +0x24 */
159 	volatile uint32_t WDT_CNT;		/* +0x28 */
160 	uint32_t RSVD3[5];
161 	volatile uint32_t PECI_DIS;		/* +0x40 */
162 	uint32_t RSVD4[3];
163 	volatile uint32_t VCI_FW_OVR;		/* +0x50 */
164 	volatile uint32_t BROM_STS;		/* +0x54 */
165 	volatile uint32_t CRYPTO_CFG;		/* +0x58 */
166 	uint32_t RSVD6[5];
167 	volatile uint32_t JTAG_MCFG;		/* +0x70 */
168 	volatile uint32_t JTAG_MSTS;		/* +0x74 */
169 	volatile uint32_t JTAG_MTDO;		/* +0x78 */
170 	volatile uint32_t JTAG_MTDI;		/* +0x7c */
171 	volatile uint32_t JTAG_MTMS;		/* +0x80 */
172 	volatile uint32_t JTAG_MCMD;		/* +0x84 */
173 	volatile uint32_t VCI_OUT_SEL;		/* +0x88 */
174 	uint32_t RSVD7[1];
175 	volatile uint32_t VW_FW_OVR;		/* +0x90 */
176 	volatile uint32_t CMP_CTRL;		/* +0x94 */
177 	volatile uint32_t CMP_SLP_CTRL;		/* +0x98 */
178 	uint32_t RSVD8[(0xb0 - 0x9c) / 4];
179 	volatile uint32_t EMB_RST_EN1;		/* +0xb0 */
180 	volatile uint32_t EMB_RST_TMOUT1;	/* +0xb4 */
181 	volatile uint32_t EMB_RST_STS;		/* +0xb8 */
182 	volatile uint32_t EMB_RST_CNT;		/* +0xbc */
183 	uint32_t RSVD9[(0x144 - 0xc0) / 4];
184 	volatile uint32_t SLP_STS_MIRROR;	/* +0x144 */
185 };
186 
187 #endif /* #ifndef _MEC172X_ECS_H */
188