1 /* 2 * Copyright (c) 2020 DENX Software Engineering GmbH 3 * Lukasz Majewski <lukma@denx.de> 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef __DSA_KSZ8794_H__ 8 #define __DSA_KSZ8794_H__ 9 10 /* SPI commands */ 11 #define KSZ8794_SPI_CMD_WR (BIT(6)) 12 #define KSZ8794_SPI_CMD_RD (BIT(6) | BIT(5)) 13 14 /* PHY registers */ 15 #define KSZ8794_BMCR 0x00 16 #define KSZ8794_BMSR 0x01 17 #define KSZ8794_PHYID1 0x02 18 #define KSZ8794_PHYID2 0x03 19 #define KSZ8794_ANAR 0x04 20 #define KSZ8794_ANLPAR 0x05 21 #define KSZ8794_LINKMD 0x1D 22 #define KSZ8794_PHYSCS 0x1F 23 24 /* SWITCH registers */ 25 #define KSZ8794_CHIP_ID0 0x00 26 #define KSZ8794_CHIP_ID1 0x01 27 #define KSZ8794_GLOBAL_CTRL0 0x02 28 #define KSZ8794_GLOBAL_CTRL1 0x03 29 #define KSZ8794_GLOBAL_CTRL2 0x04 30 #define KSZ8794_GLOBAL_CTRL3 0x05 31 #define KSZ8794_GLOBAL_CTRL4 0x06 32 #define KSZ8794_GLOBAL_CTRL5 0x07 33 #define KSZ8794_GLOBAL_CTRL6_MIB_CTRL 0x08 34 #define KSZ8794_GLOBAL_CTRL7 0x09 35 #define KSZ8794_GLOBAL_CTRL8 0x0A 36 #define KSZ8794_GLOBAL_CTRL9 0x0B 37 #define KSZ8794_GLOBAL_CTRL10 0x0C 38 #define KSZ8794_GLOBAL_CTRL11 0x0D 39 #define KSZ8794_PD_MGMT_CTRL1 0x0E 40 #define KSZ8794_PD_MGMT_CTRL2 0x0F 41 #define KSZ8794_PORT1_CTRL0 0x10 42 #define KSZ8794_PORT1_CTRL1 0x11 43 #define KSZ8794_PORT1_CTRL2 0x12 44 #define KSZ8794_PORT1_CTRL3 0x13 45 #define KSZ8794_PORT1_CTRL4 0x14 46 #define KSZ8794_PORT1_CTRL5 0x15 47 #define KSZ8794_PORT1_CTRL7 0x17 48 #define KSZ8794_PORT1_STAT0 0x18 49 #define KSZ8794_PORT1_STAT1 0x19 50 #define KSZ8794_PORT1_PHY_CTRL8 0x1A 51 #define KSZ8794_PORT1_LINKMD 0x1B 52 #define KSZ8794_PORT1_PHY_CTRL9 0x1C 53 #define KSZ8794_PORT1_PHY_CTRL10 0x1D 54 #define KSZ8794_PORT1_STAT2 0x1E 55 #define KSZ8794_PORT1_CTRL11_STAT3 0x1F 56 #define KSZ8794_PORT2_CTRL0 0x20 57 #define KSZ8794_PORT2_CTRL1 0x21 58 #define KSZ8794_PORT2_CTRL2 0x22 59 #define KSZ8794_PORT2_CTRL3 0x23 60 #define KSZ8794_PORT2_CTRL4 0x24 61 #define KSZ8794_PORT2_CTRL5 0x25 62 #define KSZ8794_PORT2_CTRL7 0x27 63 #define KSZ8794_PORT2_STAT0 0x28 64 #define KSZ8794_PORT2_STAT1 0x29 65 #define KSZ8794_PORT2_PHY_CTRL8 0x2A 66 #define KSZ8794_PORT2_LINKMD 0x2B 67 #define KSZ8794_PORT2_PHY_CTRL9 0x2C 68 #define KSZ8794_PORT2_PHY_CTRL10 0x2D 69 #define KSZ8794_PORT2_STAT2 0x2E 70 #define KSZ8794_PORT2_CTRL11_STAT3 0x2F 71 #define KSZ8794_PORT3_CTRL0 0x30 72 #define KSZ8794_PORT3_CTRL1 0x31 73 #define KSZ8794_PORT3_CTRL2 0x32 74 #define KSZ8794_PORT3_CTRL3 0x33 75 #define KSZ8794_PORT3_CTRL4 0x34 76 #define KSZ8794_PORT3_CTRL5 0x35 77 #define KSZ8794_PORT3_CTRL7 0x37 78 #define KSZ8794_PORT3_STAT0 0x38 79 #define KSZ8794_PORT3_STAT1 0x39 80 #define KSZ8794_PORT3_PHY_CTRL8 0x3A 81 #define KSZ8794_PORT3_LINKMD 0x3B 82 #define KSZ8794_PORT3_PHY_CTRL9 0x3C 83 #define KSZ8794_PORT3_PHY_CTRL10 0x3D 84 #define KSZ8794_PORT3_STAT2 0x3E 85 #define KSZ8794_PORT3_CTRL11_STAT3 0x3F 86 #define KSZ8794_PORT4_CTRL0 0x50 87 #define KSZ8794_PORT4_CTRL1 0x51 88 #define KSZ8794_PORT4_CTRL2 0x52 89 #define KSZ8794_PORT4_CTRL3 0x53 90 #define KSZ8794_PORT4_CTRL4 0x54 91 #define KSZ8794_PORT4_CTRL5 0x55 92 #define KSZ8794_PORT4_IF_CTRL6 0x56 93 #define KSZ8794_MAC_ADDR0 0x68 94 #define KSZ8794_MAC_ADDR1 0x69 95 #define KSZ8794_MAC_ADDR2 0x6A 96 #define KSZ8794_MAC_ADDR3 0x6B 97 #define KSZ8794_MAC_ADDR4 0x6C 98 #define KSZ8794_MAC_ADDR5 0x6D 99 #define KSZ8794_IND_ACCESS_CTRL0 0x6E 100 #define KSZ8794_IND_ACCESS_CTRL1 0x6F 101 #define KSZ8794_IND_DATA8 0x70 102 #define KSZ8794_IND_DATA7 0x71 103 #define KSZ8794_IND_DATA6 0x72 104 #define KSZ8794_IND_DATA5 0x73 105 #define KSZ8794_IND_DATA4 0x74 106 #define KSZ8794_IND_DATA3 0x75 107 #define KSZ8794_IND_DATA2 0x76 108 #define KSZ8794_IND_DATA1 0x77 109 #define KSZ8794_IND_DATA0 0x78 110 #define KSZ8794_INT_STAT 0x7C 111 #define KSZ8794_INT_MASK 0x7D 112 #define KSZ8794_ACL_INT_STAT 0x7E 113 #define KSZ8794_ACL_CTRL 0x7F 114 #define KSZ8794_GLOBAL_CTRL12 0x80 115 #define KSZ8794_GLOBAL_CTRL13 0x81 116 #define KSZ8794_GLOBAL_CTRL14 0x82 117 #define KSZ8794_GLOBAL_CTRL15 0x83 118 #define KSZ8794_GLOBAL_CTRL16 0x84 119 #define KSZ8794_GLOBAL_CTRL17 0x85 120 #define KSZ8794_GLOBAL_CTRL18 0x86 121 #define KSZ8794_GLOBAL_CTRL19 0x87 122 #define KSZ8794_TOS_PRIO_CTRL0 0x90 123 #define KSZ8794_TOS_PRIO_CTRL1 0x91 124 #define KSZ8794_TOS_PRIO_CTRL2 0x92 125 #define KSZ8794_TOS_PRIO_CTRL3 0x93 126 #define KSZ8794_TOS_PRIO_CTRL4 0x94 127 #define KSZ8794_TOS_PRIO_CTRL5 0x95 128 #define KSZ8794_TOS_PRIO_CTRL6 0x96 129 #define KSZ8794_TOS_PRIO_CTRL7 0x97 130 #define KSZ8794_TOS_PRIO_CTRL8 0x98 131 #define KSZ8794_TOS_PRIO_CTRL9 0x99 132 #define KSZ8794_TOS_PRIO_CTRL10 0x9A 133 #define KSZ8794_TOS_PRIO_CTRL11 0x9B 134 #define KSZ8794_TOS_PRIO_CTRL12 0x9C 135 #define KSZ8794_TOS_PRIO_CTRL13 0x9D 136 #define KSZ8794_TOS_PRIO_CTRL14 0x9E 137 #define KSZ8794_TOS_PRIO_CTRL15 0x9F 138 #define KSZ8794_IND_BYTE 0xA0 139 #define KSZ8794_GLOBAL_CTRL20 0xA3 140 #define KSZ8794_GLOBAL_CTRL21 0xA4 141 #define KSZ8794_PORT1_CTRL12 0xB0 142 #define KSZ8794_PORT1_CTRL13 0xB1 143 #define KSZ8794_PORT1_CTRL14 0xB2 144 #define KSZ8794_PORT1_CTRL15 0xB3 145 #define KSZ8794_PORT1_CTRL16 0xB4 146 #define KSZ8794_PORT1_CTRL17 0xB5 147 #define KSZ8794_PORT1_RATE_LIMIT_CTRL 0xB6 148 #define KSZ8794_PORT1_PRIO0_IG_LIMIT_CTRL1 0xB7 149 #define KSZ8794_PORT1_PRIO1_IG_LIMIT_CTRL2 0xB8 150 #define KSZ8794_PORT1_PRIO2_IG_LIMIT_CTRL3 0xB9 151 #define KSZ8794_PORT1_PRIO3_IG_LIMIT_CTRL4 0xBA 152 #define KSZ8794_PORT1_QUEUE0_EG_LIMIT_CTRL1 0xBB 153 #define KSZ8794_PORT1_QUEUE1_EG_LIMIT_CTRL2 0xBC 154 #define KSZ8794_PORT1_QUEUE2_EG_LIMIT_CTRL3 0xBD 155 #define KSZ8794_PORT1_QUEUE3_EG_LIMIT_CTRL4 0xBE 156 #define KSZ8794_TEST 0xBF 157 #define KSZ8794_PORT2_CTRL12 0xC0 158 #define KSZ8794_PORT2_CTRL13 0xC1 159 #define KSZ8794_PORT2_CTRL14 0xC2 160 #define KSZ8794_PORT2_CTRL15 0xC3 161 #define KSZ8794_PORT2_CTRL16 0xC4 162 #define KSZ8794_PORT2_CTRL17 0xC5 163 #define KSZ8794_PORT2_RATE_LIMIT_CTRL 0xC6 164 #define KSZ8794_PORT2_PRIO0_IG_LIMIT_CTRL1 0xC7 165 #define KSZ8794_PORT2_PRIO1_IG_LIMIT_CTRL2 0xC8 166 #define KSZ8794_PORT2_PRIO2_IG_LIMIT_CTRL3 0xC9 167 #define KSZ8794_PORT2_PRIO3_IG_LIMIT_CTRL4 0xCA 168 #define KSZ8794_PORT2_QUEUE0_EG_LIMIT_CTRL1 0xCB 169 #define KSZ8794_PORT2_QUEUE1_EG_LIMIT_CTRL2 0xCC 170 #define KSZ8794_PORT2_QUEUE2_EG_LIMIT_CTRL3 0xCD 171 #define KSZ8794_PORT2_QUEUE3_EG_LIMIT_CTRL4 0xCE 172 #define KSZ8794_PORT3_CTRL12 0xD0 173 #define KSZ8794_PORT3_CTRL13 0xD1 174 #define KSZ8794_PORT3_CTRL14 0xD2 175 #define KSZ8794_PORT3_CTRL15 0xD3 176 #define KSZ8794_PORT3_CTRL16 0xD4 177 #define KSZ8794_PORT3_CTRL17 0xD5 178 #define KSZ8794_PORT3_RATE_LIMIT_CTRL 0xD6 179 #define KSZ8794_PORT3_PRIO0_IG_LIMIT_CTRL1 0xD7 180 #define KSZ8794_PORT3_PRIO1_IG_LIMIT_CTRL2 0xD8 181 #define KSZ8794_PORT3_PRIO2_IG_LIMIT_CTRL3 0xD9 182 #define KSZ8794_PORT3_PRIO3_IG_LIMIT_CTRL4 0xDA 183 #define KSZ8794_PORT3_QUEUE0_EG_LIMIT_CTRL1 0xDB 184 #define KSZ8794_PORT3_QUEUE1_EG_LIMIT_CTRL2 0xDC 185 #define KSZ8794_PORT3_QUEUE2_EG_LIMIT_CTRL3 0xDD 186 #define KSZ8794_PORT3_QUEUE3_EG_LIMIT_CTRL4 0xDE 187 #define KSZ8794_TEST2 0xDF 188 #define KSZ8794_TEST3 0xEF 189 #define KSZ8794_PORT4_CTRL12 0xF0 190 #define KSZ8794_PORT4_CTRL13 0xF1 191 #define KSZ8794_PORT4_CTRL14 0xF2 192 #define KSZ8794_PORT4_CTRL15 0xF3 193 #define KSZ8794_PORT4_CTRL16 0xF4 194 #define KSZ8794_PORT4_CTRL17 0xF5 195 #define KSZ8794_PORT4_RATE_LIMIT_CTRL 0xF6 196 #define KSZ8794_PORT4_PRIO0_IG_LIMIT_CTRL1 0xF7 197 #define KSZ8794_PORT4_PRIO1_IG_LIMIT_CTRL2 0xF8 198 #define KSZ8794_PORT4_PRIO2_IG_LIMIT_CTRL3 0xF9 199 #define KSZ8794_PORT4_PRIO3_IG_LIMIT_CTRL4 0xFA 200 #define KSZ8794_PORT4_QUEUE0_EG_LIMIT_CTRL1 0xFB 201 #define KSZ8794_PORT4_QUEUE1_EG_LIMIT_CTRL2 0xFC 202 #define KSZ8794_PORT4_QUEUE2_EG_LIMIT_CTRL3 0xFD 203 #define KSZ8794_PORT4_QUEUE3_EG_LIMIT_CTRL4 0xFE 204 #define KSZ8794_TEST4 0xFF 205 206 /* Basic Control register */ 207 #define KSZ8794_BMCR_RESET 0x8000 208 #define KSZ8794_BMCR_LOOPBACK 0x4000 209 #define KSZ8794_BMCR_FORCE_100 0x2000 210 #define KSZ8794_BMCR_AN_EN 0x1000 211 #define KSZ8794_BMCR_POWER_DOWN 0x0800 212 #define KSZ8794_BMCR_ISOLATE 0x0400 213 #define KSZ8794_BMCR_RESTART_AN 0x0200 214 #define KSZ8794_BMCR_FORCE_FULL_DUPLEX 0x0100 215 #define KSZ8794_BMCR_HP_MDIX 0x0020 216 #define KSZ8794_BMCR_FORCE_MDI 0x0010 217 #define KSZ8794_BMCR_AUTO_MDIX_DIS 0x0008 218 #define KSZ8794_BMCR_FAR_END_FAULT_DIS 0x0004 219 #define KSZ8794_BMCR_TRANSMIT_DIS 0x0002 220 #define KSZ8794_BMCR_LED_DIS 0x0001 221 222 /* Basic Status register */ 223 #define KSZ8794_BMSR_100BT4 0x8000 224 #define KSZ8794_BMSR_100BTX_FD 0x4000 225 #define KSZ8794_BMSR_100BTX_HD 0x2000 226 #define KSZ8794_BMSR_10BT_FD 0x1000 227 #define KSZ8794_BMSR_10BT_HD 0x0800 228 #define KSZ8794_BMSR_AN_COMPLETE 0x0020 229 #define KSZ8794_BMSR_FAR_END_FAULT 0x0010 230 #define KSZ8794_BMSR_AN_CAPABLE 0x0008 231 #define KSZ8794_BMSR_LINK_STATUS 0x0004 232 #define KSZ8794_BMSR_EXTENDED_CAPABLE 0x0001 233 234 #define KSZ8794_GLOBAL_CTRL10_TAIL_TAG_EN BIT(1) 235 #define KSZ8794_GLOBAL_CTRL2_LEG_MAX_PKT_SIZ_CHK_DIS BIT(1) 236 237 #define KSZ8794_CTRL2_PORTn(n) (0x12 + ((n) * 0x10)) 238 #define KSZ8794_CTRL2_TRANSMIT_EN BIT(2) 239 #define KSZ8794_CTRL2_RECEIVE_EN BIT(1) 240 #define KSZ8794_CTRL2_LEARNING_DIS BIT(0) 241 242 #define KSZ8794_STAT2_PORTn(n) (0x1E + ((n) * 0x10)) 243 #define KSZ8794_STAT2_LINK_GOOD BIT(5) 244 245 #define KSZ8794_CHIP_ID0_ID_DEFAULT 0x87 246 #define KSZ8794_CHIP_ID1_ID_DEFAULT 0x61 247 #define KSZ8794_PWR_MGNT_MODE_SOFT_DOWN BIT(4) 248 249 #define KSZ8794_GLOBAL_CTRL20_LOWSPEED_MASK 0x07 250 #define KSZ8794_GLOBAL_CTRL20_LOWSPEED_2MA 0x00 251 #define KSZ8794_GLOBAL_CTRL20_LOWSPEED_4MA 0x01 252 #define KSZ8794_GLOBAL_CTRL20_LOWSPEED_8MA 0x02 253 #define KSZ8794_GLOBAL_CTRL20_LOWSPEED_12MA 0x03 254 #define KSZ8794_GLOBAL_CTRL20_LOWSPEED_16MA 0x04 255 #define KSZ8794_GLOBAL_CTRL20_LOWSPEED_20MA 0x05 256 #define KSZ8794_GLOBAL_CTRL20_LOWSPEED_24MA 0x06 257 #define KSZ8794_GLOBAL_CTRL20_LOWSPEED_28MA 0x07 258 259 enum { 260 /* 261 * KSZ8794 register's MAP 262 * (0x00 - 0x0F): Global Registers 263 * Port registers (offsets): 264 * (0x10): Port 1 265 * (0x20): Port 2 266 * (0x30): Port 3 267 * (0x40): Reserved 268 * (0x50): Port 4 269 */ 270 /* LAN ports for the ksz8794 switch */ 271 KSZ8794_PORT1 = 0, 272 KSZ8794_PORT2, 273 KSZ8794_PORT3, 274 /* 275 * SWITCH <-> CPU port 276 * 277 * We also need to consider the "Reserved' offset 278 * defined above. 279 */ 280 KSZ8794_PORT4 = 4, 281 }; 282 283 #define KSZ8794_REG_IND_DATA_8 0x70 284 #define KSZ8794_REG_IND_DATA_7 0x71 285 #define KSZ8794_REG_IND_DATA_6 0x72 286 #define KSZ8794_REG_IND_DATA_5 0x73 287 #define KSZ8794_REG_IND_DATA_4 0x74 288 #define KSZ8794_REG_IND_DATA_3 0x75 289 #define KSZ8794_REG_IND_DATA_2 0x76 290 #define KSZ8794_REG_IND_DATA_1 0x77 291 #define KSZ8794_REG_IND_DATA_0 0x78 292 293 #define KSZ8794_REG_IND_CTRL_0 0x6E 294 #define KSZ8794_REG_IND_CTRL_1 0x6F 295 296 #define KSZ8794_STATIC_MAC_TABLE_VALID BIT(5) 297 #define KSZ8794_STATIC_MAC_TABLE_OVRD BIT(6) 298 299 #define KSZ8XXX_CHIP_ID0 KSZ8794_CHIP_ID0 300 #define KSZ8XXX_CHIP_ID1 KSZ8794_CHIP_ID1 301 #define KSZ8XXX_CHIP_ID0_ID_DEFAULT KSZ8794_CHIP_ID0_ID_DEFAULT 302 #define KSZ8XXX_CHIP_ID1_ID_DEFAULT KSZ8794_CHIP_ID1_ID_DEFAULT 303 #define KSZ8XXX_FIRST_PORT KSZ8794_PORT1 304 #define KSZ8XXX_LAST_PORT KSZ8794_PORT3 305 #define KSZ8XXX_CPU_PORT KSZ8794_PORT4 306 #define KSZ8XXX_REG_IND_CTRL_0 KSZ8794_REG_IND_CTRL_0 307 #define KSZ8XXX_REG_IND_CTRL_1 KSZ8794_REG_IND_CTRL_1 308 #define KSZ8XXX_REG_IND_DATA_8 KSZ8794_REG_IND_DATA_8 309 #define KSZ8XXX_REG_IND_DATA_7 KSZ8794_REG_IND_DATA_7 310 #define KSZ8XXX_REG_IND_DATA_6 KSZ8794_REG_IND_DATA_6 311 #define KSZ8XXX_REG_IND_DATA_5 KSZ8794_REG_IND_DATA_5 312 #define KSZ8XXX_REG_IND_DATA_4 KSZ8794_REG_IND_DATA_4 313 #define KSZ8XXX_REG_IND_DATA_3 KSZ8794_REG_IND_DATA_3 314 #define KSZ8XXX_REG_IND_DATA_2 KSZ8794_REG_IND_DATA_2 315 #define KSZ8XXX_REG_IND_DATA_1 KSZ8794_REG_IND_DATA_1 316 #define KSZ8XXX_REG_IND_DATA_0 KSZ8794_REG_IND_DATA_0 317 #define KSZ8XXX_STATIC_MAC_TABLE_VALID KSZ8794_STATIC_MAC_TABLE_VALID 318 #define KSZ8XXX_STATIC_MAC_TABLE_OVRD KSZ8794_STATIC_MAC_TABLE_OVRD 319 #define KSZ8XXX_STAT2_LINK_GOOD KSZ8794_STAT2_LINK_GOOD 320 #define KSZ8XXX_RESET_REG KSZ8794_PD_MGMT_CTRL1 321 #define KSZ8XXX_RESET_SET KSZ8794_PWR_MGNT_MODE_SOFT_DOWN 322 #define KSZ8XXX_RESET_CLEAR 0 323 #define KSZ8XXX_STAT2_PORTn KSZ8794_STAT2_PORTn 324 #define KSZ8XXX_SPI_CMD_RD KSZ8794_SPI_CMD_RD 325 #define KSZ8XXX_SPI_CMD_WR KSZ8794_SPI_CMD_WR 326 #define KSZ8XXX_SOFT_RESET_DURATION 1000 327 #define KSZ8XXX_HARD_RESET_WAIT 10000 328 #endif /* __DSA_KSZ8794_H__ */ 329
