1 /* 2 * Copyright 2022-2023 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _NXP_S32_S32ZE_SOC_H_ 8 #define _NXP_S32_S32ZE_SOC_H_ 9 10 /* Do not let CMSIS to handle GIC */ 11 #define __GIC_PRESENT 0 12 13 #if defined(CONFIG_SOC_S32Z27_R52) 14 #include <S32Z2.h> 15 #else 16 #error "SoC not supported" 17 #endif 18 19 #if defined(CONFIG_CMSIS_RTOS_V2) 20 #include <cmsis_rtos_v2_adapt.h> 21 #endif 22 23 /* Aliases for peripheral base addresses */ 24 25 /* SIUL2 */ 26 #define IP_SIUL2_2_BASE 0U /* instance does not exist on this SoC */ 27 28 /* LINFlexD*/ 29 #define IP_LINFLEX_12_BASE IP_MSC_0_LIN_BASE 30 31 /* SWT */ 32 #define IP_SWT_0_BASE IP_CE_SWT_0_BASE 33 #define IP_SWT_1_BASE IP_CE_SWT_1_BASE 34 #define IP_SWT_2_BASE IP_RTU0__SWT_0_BASE 35 #define IP_SWT_3_BASE IP_RTU0__SWT_1_BASE 36 #define IP_SWT_4_BASE IP_RTU0__SWT_2_BASE 37 #define IP_SWT_5_BASE IP_RTU0__SWT_3_BASE 38 #define IP_SWT_6_BASE IP_RTU0__SWT_4_BASE 39 #define IP_SWT_7_BASE IP_RTU1__SWT_0_BASE 40 #define IP_SWT_8_BASE IP_RTU1__SWT_1_BASE 41 #define IP_SWT_9_BASE IP_RTU1__SWT_2_BASE 42 #define IP_SWT_10_BASE IP_RTU1__SWT_3_BASE 43 #define IP_SWT_11_BASE IP_RTU1__SWT_4_BASE 44 #define IP_SWT_12_BASE IP_SMU__SWT_BASE 45 46 /* STM */ 47 #define IP_STM_0_BASE IP_CE_STM_0_BASE 48 #define IP_STM_1_BASE IP_CE_STM_1_BASE 49 #define IP_STM_2_BASE IP_CE_STM_2_BASE 50 #define IP_STM_3_BASE IP_RTU0__STM_0_BASE 51 #define IP_STM_4_BASE IP_RTU0__STM_1_BASE 52 #define IP_STM_5_BASE IP_RTU0__STM_2_BASE 53 #define IP_STM_6_BASE IP_RTU0__STM_3_BASE 54 #define IP_STM_7_BASE IP_RTU1__STM_0_BASE 55 #define IP_STM_8_BASE IP_RTU1__STM_1_BASE 56 #define IP_STM_9_BASE IP_RTU1__STM_2_BASE 57 #define IP_STM_10_BASE IP_RTU1__STM_3_BASE 58 #define IP_STM_11_BASE IP_SMU__STM_0_BASE 59 #define IP_STM_12_BASE IP_SMU__STM_2_BASE 60 61 /* NETC */ 62 #define IP_NETC_EMDIO_0_BASE IP_NETC__EMDIO_BASE_BASE 63 64 /* MRU */ 65 #define IP_MRU_0_BASE IP_RTU0__MRU_0_BASE 66 #define IP_MRU_1_BASE IP_RTU0__MRU_1_BASE 67 #define IP_MRU_2_BASE IP_RTU0__MRU_2_BASE 68 #define IP_MRU_3_BASE IP_RTU0__MRU_3_BASE 69 #define IP_MRU_4_BASE IP_RTU1__MRU_0_BASE 70 #define IP_MRU_5_BASE IP_RTU1__MRU_1_BASE 71 #define IP_MRU_6_BASE IP_RTU1__MRU_2_BASE 72 #define IP_MRU_7_BASE IP_RTU1__MRU_3_BASE 73 74 #endif /* _NXP_S32_S32ZE_SOC_H_ */ 75
