1 /*
2 * Copyright 2022 Intel Corporation
3 * Copyright 2023 Meta Platforms, Inc. and its affiliates
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #ifndef ZEPHYR_INCLUDE_DRIVERS_I3C_CCC_H_
9 #define ZEPHYR_INCLUDE_DRIVERS_I3C_CCC_H_
10
11 /**
12 * @brief I3C Common Command Codes
13 * @defgroup i3c_ccc I3C Common Command Codes
14 * @ingroup i3c_interface
15 * @{
16 */
17
18 #include <zephyr/types.h>
19 #include <zephyr/device.h>
20 #include <zephyr/toolchain.h>
21 #include <zephyr/sys/util.h>
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /** Maximum CCC ID for broadcast */
28 #define I3C_CCC_BROADCAST_MAX_ID 0x7FU
29
30 /**
31 * Enable Events Command
32 *
33 * @param broadcast True if broadcast, false if direct.
34 */
35 #define I3C_CCC_ENEC(broadcast) ((broadcast) ? 0x00U : 0x80U)
36
37 /**
38 * Disable Events Command
39 *
40 * @param broadcast True if broadcast, false if direct.
41 */
42 #define I3C_CCC_DISEC(broadcast) ((broadcast) ? 0x01U : 0x81U)
43
44 /**
45 * Enter Activity State
46 *
47 * @param as Desired activity state
48 * @param broadcast True if broadcast, false if direct.
49 */
50 #define I3C_CCC_ENTAS(as, broadcast) (((broadcast) ? 0x02U : 0x82U) + (as))
51
52 /**
53 * Enter Activity State 0
54 *
55 * @param broadcast True if broadcast, false if direct.
56 */
57 #define I3C_CCC_ENTAS0(broadcast) I3C_CCC_ENTAS(0, broadcast)
58
59 /**
60 * Enter Activity State 1
61 *
62 * @param broadcast True if broadcast, false if direct.
63 */
64 #define I3C_CCC_ENTAS1(broadcast) I3C_CCC_ENTAS(1, broadcast)
65
66 /**
67 * Enter Activity State 2
68 *
69 * @param broadcast True if broadcast, false if direct.
70 */
71 #define I3C_CCC_ENTAS2(broadcast) I3C_CCC_ENTAS(2, broadcast)
72
73 /**
74 * Enter Activity State 3
75 *
76 * @param broadcast True if broadcast, false if direct.
77 */
78 #define I3C_CCC_ENTAS3(broadcast) I3C_CCC_ENTAS(3, broadcast)
79
80 /** Reset Dynamic Address Assignment (Broadcast) */
81 #define I3C_CCC_RSTDAA 0x06U
82
83 /** Enter Dynamic Address Assignment (Broadcast) */
84 #define I3C_CCC_ENTDAA 0x07U
85
86 /** Define List of Targets (Broadcast) */
87 #define I3C_CCC_DEFTGTS 0x08U
88
89 /**
90 * Set Max Write Length (Broadcast or Direct)
91 *
92 * @param broadcast True if broadcast, false if direct.
93 */
94 #define I3C_CCC_SETMWL(broadcast) ((broadcast) ? 0x09U : 0x89U)
95
96 /**
97 * Set Max Read Length (Broadcast or Direct)
98 *
99 * @param broadcast True if broadcast, false if direct.
100 */
101 #define I3C_CCC_SETMRL(broadcast) ((broadcast) ? 0x0AU : 0x8AU)
102
103 /** Enter Test Mode (Broadcast) */
104 #define I3C_CCC_ENTTM 0x0BU
105
106 /** Set Bus Context (Broadcast) */
107 #define I3C_CCC_SETBUSCON 0x0CU
108
109 /**
110 * Data Transfer Ending Procedure Control
111 *
112 * @param broadcast True if broadcast, false if direct.
113 */
114 #define I3C_CCC_ENDXFER(broadcast) ((broadcast) ? 0x12U : 0x92U)
115
116 /** Enter HDR Mode (HDR-DDR) (Broadcast) */
117 #define I3C_CCC_ENTHDR(x) (0x20U + (x))
118
119 /** Enter HDR Mode 0 (HDR-DDR) (Broadcast) */
120 #define I3C_CCC_ENTHDR0 0x20U
121
122 /** Enter HDR Mode 1 (HDR-TSP) (Broadcast) */
123 #define I3C_CCC_ENTHDR1 0x21U
124
125 /** Enter HDR Mode 2 (HDR-TSL) (Broadcast) */
126 #define I3C_CCC_ENTHDR2 0x22U
127
128 /** Enter HDR Mode 3 (HDR-BT) (Broadcast) */
129 #define I3C_CCC_ENTHDR3 0x23U
130
131 /** Enter HDR Mode 4 (Broadcast) */
132 #define I3C_CCC_ENTHDR4 0x24U
133
134 /** Enter HDR Mode 5 (Broadcast) */
135 #define I3C_CCC_ENTHDR5 0x25U
136
137 /** Enter HDR Mode 6 (Broadcast) */
138 #define I3C_CCC_ENTHDR6 0x26U
139
140 /** Enter HDR Mode 7 (Broadcast) */
141 #define I3C_CCC_ENTHDR7 0x27U
142
143 /**
144 * Exchange Timing Information (Broadcast or Direct)
145 *
146 * @param broadcast True if broadcast, false if direct.
147 */
148 #define I3C_CCC_SETXTIME(broadcast) ((broadcast) ? 0x28U : 0x98U)
149
150 /** Set All Addresses to Static Addresses (Broadcast) */
151 #define I3C_CCC_SETAASA 0x29U
152
153 /**
154 * Target Reset Action
155 *
156 * @param broadcast True if broadcast, false if direct.
157 */
158 #define I3C_CCC_RSTACT(broadcast) ((broadcast) ? 0x2AU : 0x9AU)
159
160 /** Define List of Group Address (Broadcast) */
161 #define I3C_CCC_DEFGRPA 0x2BU
162
163 /**
164 * Reset Group Address
165 *
166 * @param broadcast True if broadcast, false if direct.
167 */
168 #define I3C_CCC_RSTGRPA(broadcast) ((broadcast) ? 0x2CU : 0x9CU)
169
170 /** Multi-Lane Data Transfer Control (Broadcast) */
171 #define I3C_CCC_MLANE(broadcast) ((broadcast) ? 0x2DU : 0x9DU)
172
173 /**
174 * Vendor/Standard Extension
175 *
176 * @param broadcast True if broadcast, false if direct.
177 * @param id Extension ID.
178 */
179 #define I3C_CCC_VENDOR(broadcast, id) ((id) + ((broadcast) ? 0x61U : 0xE0U))
180
181 /** Set Dynamic Address from Static Address (Direct) */
182 #define I3C_CCC_SETDASA 0x87U
183
184 /** Set New Dynamic Address (Direct) */
185 #define I3C_CCC_SETNEWDA 0x88U
186
187 /** Get Max Write Length (Direct) */
188 #define I3C_CCC_GETMWL 0x8BU
189
190 /** Get Max Read Length (Direct) */
191 #define I3C_CCC_GETMRL 0x8CU
192
193 /** Get Provisioned ID (Direct) */
194 #define I3C_CCC_GETPID 0x8DU
195
196 /** Get Bus Characteristics Register (Direct) */
197 #define I3C_CCC_GETBCR 0x8EU
198
199 /** Get Device Characteristics Register (Direct) */
200 #define I3C_CCC_GETDCR 0x8FU
201
202 /** Get Device Status (Direct) */
203 #define I3C_CCC_GETSTATUS 0x90U
204
205 /** Get Accept Controller Role (Direct) */
206 #define I3C_CCC_GETACCCR 0x91U
207
208 /** Set Bridge Targets (Direct) */
209 #define I3C_CCC_SETBRGTGT 0x93U
210
211 /** Get Max Data Speed (Direct) */
212 #define I3C_CCC_GETMXDS 0x94U
213
214 /** Get Optional Feature Capabilities (Direct) */
215 #define I3C_CCC_GETCAPS 0x95U
216
217 /** Set Route (Direct) */
218 #define I3C_CCC_SETROUTE 0x96U
219
220 /** Device to Device(s) Tunneling Control (Direct) */
221 #define I3C_CCC_D2DXFER 0x97U
222
223 /** Get Exchange Timing Information (Direct) */
224 #define I3C_CCC_GETXTIME 0x99U
225
226 /** Set Group Address (Direct) */
227 #define I3C_CCC_SETGRPA 0x9BU
228
229 struct i3c_device_desc;
230
231 /**
232 * @brief Payload structure for Direct CCC to one target.
233 */
234 struct i3c_ccc_target_payload {
235 /** Target address */
236 uint8_t addr;
237
238 /** @c 0 for Write, @c 1 for Read */
239 uint8_t rnw:1;
240
241 /**
242 * - For Write CCC, pointer to the byte array of data
243 * to be sent, which may contain the Sub-Command Byte
244 * and additional data.
245 * - For Read CCC, pointer to the byte buffer for data
246 * to be read into.
247 */
248 uint8_t *data;
249
250 /** Length in bytes for @p data. */
251 size_t data_len;
252
253 /**
254 * Total number of bytes transferred
255 *
256 * A Target can issue an EoD or the Controller can abort a transfer
257 * before the length of the buffer. It is expected for the driver to
258 * write to this after the transfer.
259 */
260 size_t num_xfer;
261 };
262
263 /**
264 * @brief Payload structure for one CCC transaction.
265 */
266 struct i3c_ccc_payload {
267 struct {
268 /**
269 * The CCC ID (@c I3C_CCC_*).
270 */
271 uint8_t id;
272
273 /**
274 * Pointer to byte array of data for this CCC.
275 *
276 * This is the bytes following the CCC command in CCC frame.
277 * Set to @c NULL if no associated data.
278 */
279 uint8_t *data;
280
281 /** Length in bytes for optional data array. */
282 size_t data_len;
283
284 /**
285 * Total number of bytes transferred
286 *
287 * A Controller can abort a transfer before the length of the buffer.
288 * It is expected for the driver to write to this after the transfer.
289 */
290 size_t num_xfer;
291 } ccc;
292
293 struct {
294 /**
295 * Array of struct i3c_ccc_target_payload.
296 *
297 * Each element describes the target and associated
298 * payloads for this CCC.
299 *
300 * Use with Direct CCC.
301 */
302 struct i3c_ccc_target_payload *payloads;
303
304 /** Number of targets */
305 size_t num_targets;
306 } targets;
307 };
308
309 /**
310 * @brief Payload for ENEC/DISEC CCC (Target Events Command).
311 */
312 struct i3c_ccc_events {
313 /**
314 * Event byte:
315 * - Bit[0]: ENINT/DISINT:
316 * - Target Interrupt Requests
317 * - Bit[1]: ENCR/DISCR:
318 * - Controller Role Requests
319 * - Bit[3]: ENHJ/DISHJ:
320 * - Hot-Join Event
321 */
322 uint8_t events;
323 } __packed;
324
325 /** Enable Events (ENEC) - Target Interrupt Requests. */
326 #define I3C_CCC_ENEC_EVT_ENINTR BIT(0)
327
328 /** Enable Events (ENEC) - Controller Role Requests. */
329 #define I3C_CCC_ENEC_EVT_ENCR BIT(1)
330
331 /** Enable Events (ENEC) - Hot-Join Event. */
332 #define I3C_CCC_ENEC_EVT_ENHJ BIT(3)
333
334 #define I3C_CCC_ENEC_EVT_ALL \
335 (I3C_CCC_ENEC_EVT_ENINTR | I3C_CCC_ENEC_EVT_ENCR | I3C_CCC_ENEC_EVT_ENHJ)
336
337 /** Disable Events (DISEC) - Target Interrupt Requests. */
338 #define I3C_CCC_DISEC_EVT_DISINTR BIT(0)
339
340 /** Disable Events (DISEC) - Controller Role Requests. */
341 #define I3C_CCC_DISEC_EVT_DISCR BIT(1)
342
343 /** Disable Events (DISEC) - Hot-Join Event. */
344 #define I3C_CCC_DISEC_EVT_DISHJ BIT(3)
345
346 #define I3C_CCC_DISEC_EVT_ALL \
347 (I3C_CCC_DISEC_EVT_DISINTR | I3C_CCC_DISEC_EVT_DISCR | I3C_CCC_DISEC_EVT_DISHJ)
348
349 /*
350 * Events for both enabling and disabling since
351 * they have the same bits.
352 */
353
354 /** Events - Target Interrupt Requests. */
355 #define I3C_CCC_EVT_INTR BIT(0)
356
357 /** Events - Controller Role Requests. */
358 #define I3C_CCC_EVT_CR BIT(1)
359
360 /** Events - Hot-Join Event. */
361 #define I3C_CCC_EVT_HJ BIT(3)
362
363 /** Bitmask for all events. */
364 #define I3C_CCC_EVT_ALL \
365 (I3C_CCC_EVT_INTR | I3C_CCC_EVT_CR | I3C_CCC_EVT_HJ)
366
367 /**
368 * @brief Payload for SETMWL/GETMWL CCC (Set/Get Maximum Write Length).
369 *
370 * @note For drivers and help functions, the raw data coming
371 * back from target device is in big endian. This needs to be
372 * translated back to CPU endianness before passing back to
373 * function caller.
374 */
375 struct i3c_ccc_mwl {
376 /** Maximum Write Length */
377 uint16_t len;
378 } __packed;
379
380 /**
381 * @brief Payload for SETMRL/GETMRL CCC (Set/Get Maximum Read Length).
382 *
383 * @note For drivers and help functions, the raw data coming
384 * back from target device is in big endian. This needs to be
385 * translated back to CPU endianness before passing back to
386 * function caller.
387 */
388 struct i3c_ccc_mrl {
389 /** Maximum Read Length */
390 uint16_t len;
391
392 /** Optional IBI Payload Size */
393 uint8_t ibi_len;
394 } __packed;
395
396 /**
397 * @brief The active controller part of payload for DEFTGTS CCC.
398 *
399 * This is used by DEFTGTS (Define List of Targets) CCC to describe
400 * the active controller on the I3C bus.
401 */
402 struct i3c_ccc_deftgts_active_controller {
403 /** Dynamic Address of Active Controller */
404 uint8_t addr;
405
406 /** Device Characteristic Register of Active Controller */
407 uint8_t dcr;
408
409 /** Bus Characteristic Register of Active Controller */
410 uint8_t bcr;
411
412 /** Static Address of Active Controller */
413 uint8_t static_addr;
414 };
415
416 /**
417 * @brief The target device part of payload for DEFTGTS CCC.
418 *
419 * This is used by DEFTGTS (Define List of Targets) CCC to describe
420 * the existing target devices on the I3C bus.
421 */
422 struct i3c_ccc_deftgts_target {
423 /** Dynamic Address of a target device, or a group address */
424 uint8_t addr;
425
426 union {
427 /**
428 * Device Characteristic Register of a I3C target device
429 * or a group.
430 */
431 uint8_t dcr;
432
433 /** Legacy Virtual Register for legacy I2C device. */
434 uint8_t lvr;
435 };
436
437 /** Bus Characteristic Register of a target device or a group */
438 uint8_t bcr;
439
440 /** Static Address of a target device or a group */
441 uint8_t static_addr;
442 };
443
444 /**
445 * @brief Payload for DEFTGTS CCC (Define List of Targets).
446 *
447 * @note @p i3c_ccc_deftgts_target is an array of targets, where
448 * the number of elements is dependent on the number of I3C targets
449 * on the bus. Please have enough space for both read and write of
450 * this CCC.
451 */
452 struct i3c_ccc_deftgts {
453 /** Data describing the active controller */
454 struct i3c_ccc_deftgts_active_controller active_controller;
455
456 /** Data describing the target(s) on the bus */
457 struct i3c_ccc_deftgts_target targets[];
458 } __packed;
459
460 /**
461 * @brief Payload for a single device address.
462 *
463 * This is used for:
464 * - SETDASA (Set Dynamic Address from Static Address)
465 * - SETNEWDA (Set New Dynamic Address)
466 * - SETGRPA (Set Group Address)
467 * - GETACCCR (Get Accept Controller Role)
468 *
469 * Note that the target address is encoded within
470 * struct i3c_ccc_target_payload instead of being encoded in
471 * this payload.
472 */
473 struct i3c_ccc_address {
474 /**
475 * - For SETDASA, Static Address to be assigned as
476 * Dynamic Address.
477 * - For SETNEWDA, new Dynamic Address to be assigned.
478 * - For SETGRPA, new Group Address to be set.
479 * - For GETACCCR, the correct address of Secondary
480 * Controller.
481 *
482 * @note For SETDATA, SETNEWDA and SETGRAP,
483 * the address is left-shift by 1, and bit[0] is always 0.
484 *
485 * @note Fpr SET GETACCCR, the address is left-shift by 1,
486 * and bit[0] is the calculated odd parity bit.
487 */
488 uint8_t addr;
489 } __packed;
490
491 /**
492 * @brief Payload for GETPID CCC (Get Provisioned ID).
493 */
494 struct i3c_ccc_getpid {
495 /**
496 * 48-bit Provisioned ID.
497 *
498 * @note Data is big-endian where first byte is MSB.
499 */
500 uint8_t pid[6];
501 } __packed;
502
503 /**
504 * @brief Payload for GETBCR CCC (Get Bus Characteristics Register).
505 */
506 struct i3c_ccc_getbcr {
507 /** Bus Characteristics Register */
508 uint8_t bcr;
509 } __packed;
510
511 /**
512 * @brief Payload for GETDCR CCC (Get Device Characteristics Register).
513 */
514 struct i3c_ccc_getdcr {
515 /** Device Characteristics Register */
516 uint8_t dcr;
517 } __packed;
518
519
520 /**
521 * @brief Indicate which format of GETSTATUS to use.
522 */
523 enum i3c_ccc_getstatus_fmt {
524 /** GETSTATUS Format 1 */
525 GETSTATUS_FORMAT_1,
526
527 /** GETSTATUS Format 2 */
528 GETSTATUS_FORMAT_2,
529 };
530
531 /**
532 * @brief Defining byte values for GETSTATUS Format 2.
533 */
534 enum i3c_ccc_getstatus_defbyte {
535 /** Target status. */
536 GETSTATUS_FORMAT_2_TGTSTAT = 0x00U,
537
538 /** PRECR - Alternate status format describing Controller-capable device. */
539 GETSTATUS_FORMAT_2_PRECR = 0x91U,
540
541 /** Invalid defining byte. */
542 GETSTATUS_FORMAT_2_INVALID = 0x100U
543 };
544
545 /**
546 * @brief Payload for GETSTATUS CCC (Get Device Status).
547 */
548 union i3c_ccc_getstatus {
549 struct {
550 /**
551 * Device Status
552 * - Bit[15:8]: Reserved.
553 * - Bit[7:6]: Activity Mode.
554 * - Bit[5]: Protocol Error.
555 * - Bit[4]: Reserved.
556 * - Bit[3:0]: Number of Pending Interrupts.
557 *
558 * @note For drivers and help functions, the raw data coming
559 * back from target device is in big endian. This needs to be
560 * translated back to CPU endianness before passing back to
561 * function caller.
562 */
563 uint16_t status;
564 } fmt1;
565
566 union {
567 /**
568 * Defining Byte 0x00: TGTSTAT
569 *
570 * @see i3c_ccc_getstatus::fmt1::status
571 */
572 uint16_t tgtstat;
573
574 /**
575 * Defining Byte 0x91: PRECR
576 * - Bit[15:8]: Vendor Reserved
577 * - Bit[7:2]: Reserved
578 * - Bit[1]: Handoff Delay NACK
579 * - Bit[0]: Deep Sleep Detected
580 *
581 * @note For drivers and help functions, the raw data coming
582 * back from target device is in big endian. This needs to be
583 * translated back to CPU endianness before passing back to
584 * function caller.
585 */
586 uint16_t precr;
587
588 uint16_t raw_u16;
589 } fmt2;
590 } __packed;
591
592 /** GETSTATUS Format 1 - Protocol Error bit. */
593 #define I3C_CCC_GETSTATUS_PROTOCOL_ERR BIT(5)
594
595 /** GETSTATUS Format 1 - Activity Mode bit shift value. */
596 #define I3C_CCC_GETSTATUS_ACTIVITY_MODE_SHIFT 6
597
598 /** GETSTATUS Format 1 - Activity Mode bitmask. */
599 #define I3C_CCC_GETSTATUS_ACTIVITY_MODE_MASK \
600 (0x03U << I3C_CCC_GETSTATUS_ACTIVITY_MODE_SHIFT)
601
602 /**
603 * @brief GETSTATUS Format 1 - Activity Mode
604 *
605 * Obtain Activity Mode from GETSTATUS Format 1 value obtained via
606 * GETSTATUS.
607 *
608 * @param status GETSTATUS Format 1 value
609 */
610 #define I3C_CCC_GETSTATUS_ACTIVITY_MODE(status) \
611 (((status) & I3C_CCC_GETSTATUS_ACTIVITY_MODE_MASK) \
612 >> I3C_CCC_GETSTATUS_ACTIVITY_MODE_SHIFT)
613
614 /** GETSTATUS Format 1 - Number of Pending Interrupts bit shift value. */
615 #define I3C_CCC_GETSTATUS_NUM_INT_SHIFT 0
616
617 /** GETSTATUS Format 1 - Number of Pending Interrupts bitmask. */
618 #define I3C_CCC_GETSTATUS_NUM_INT_MASK \
619 (0x0FU << I3C_CCC_GETSTATUS_NUM_INT_SHIFT)
620
621 /**
622 * @brief GETSTATUS Format 1 - Number of Pending Interrupts
623 *
624 * Obtain Number of Pending Interrupts from GETSTATUS Format 1 value
625 * obtained via GETSTATUS.
626 *
627 * @param status GETSTATUS Format 1 value
628 */
629 #define I3C_CCC_GETSTATUS_NUM_INT(status) \
630 (((status) & I3C_CCC_GETSTATUS_NUM_INT_MASK) \
631 >> I3C_CCC_GETSTATUS_NUM_INT_SHIFT)
632
633 /** GETSTATUS Format 2 - PERCR - Deep Sleep Detected bit. */
634 #define I3C_CCC_GETSTATUS_PRECR_DEEP_SLEEP_DETECTED BIT(0)
635
636 /** GETSTATUS Format 2 - PERCR - Handoff Delay NACK. */
637 #define I3C_CCC_GETSTATUS_PRECR_HANDOFF_DELAY_NACK BIT(1)
638
639 /**
640 * @brief One Bridged Target for SETBRGTGT payload.
641 */
642 struct i3c_ccc_setbrgtgt_tgt {
643 /**
644 * Dynamic address of the bridged target.
645 *
646 * @note The address is left-shift by 1, and bit[0]
647 * is always 0.
648 */
649 uint8_t addr;
650
651 /**
652 * 16-bit ID for the bridged target.
653 *
654 * @note For drivers and help functions, the raw data coming
655 * back from target device is in big endian. This needs to be
656 * translated back to CPU endianness before passing back to
657 * function caller.
658 */
659 uint16_t id;
660 } __packed;
661
662 /**
663 * @brief Payload for SETBRGTGT CCC (Set Bridge Targets).
664 *
665 * Note that the bridge target address is encoded within
666 * struct i3c_ccc_target_payload instead of being encoded in
667 * this payload.
668 */
669 struct i3c_ccc_setbrgtgt {
670 /** Number of bridged targets */
671 uint8_t count;
672
673 /** Array of bridged targets */
674 struct i3c_ccc_setbrgtgt_tgt targets[];
675 } __packed;
676
677 /**
678 * @brief Payload for GETMXDS CCC (Get Max Data Speed).
679 *
680 * @note This is only for GETMXDS Format 1 and Format 2.
681 */
682 union i3c_ccc_getmxds {
683 struct {
684 /** maxWr */
685 uint8_t maxwr;
686
687 /** maxRd */
688 uint8_t maxrd;
689 } fmt1;
690
691 struct {
692 /** maxWr */
693 uint8_t maxwr;
694
695 /** maxRd */
696 uint8_t maxrd;
697
698 /**
699 * Maximum Read Turnaround Time in microsecond.
700 *
701 * This is in little-endian where first byte is LSB.
702 */
703 uint8_t maxrdturn[3];
704 } fmt2;
705
706 struct {
707 /**
708 * Defining Byte 0x00: WRRDTURN
709 *
710 * @see i3c_ccc_getmxds::fmt2
711 */
712 uint8_t wrrdturn;
713
714 /**
715 * Defining Byte 0x91: CRHDLY
716 * - Bit[2]: Set Bus Actibity State
717 * - Bit[1:0]: Controller Handoff Activity State
718 */
719 uint8_t crhdly1;
720 } fmt3;
721 } __packed;
722
723 /** Get Max Data Speed (GETMXDS) - Default Max Sustained Data Rate. */
724 #define I3C_CCC_GETMXDS_MAX_SDR_FSCL_MAX 0
725
726 /** Get Max Data Speed (GETMXDS) - 8MHz Max Sustained Data Rate. */
727 #define I3C_CCC_GETMXDS_MAX_SDR_FSCL_8MHZ 1
728
729 /** Get Max Data Speed (GETMXDS) - 6MHz Max Sustained Data Rate. */
730 #define I3C_CCC_GETMXDS_MAX_SDR_FSCL_6MHZ 2
731
732 /** Get Max Data Speed (GETMXDS) - 4MHz Max Sustained Data Rate. */
733 #define I3C_CCC_GETMXDS_MAX_SDR_FSCL_4MHZ 3
734
735 /** Get Max Data Speed (GETMXDS) - 2MHz Max Sustained Data Rate. */
736 #define I3C_CCC_GETMXDS_MAX_SDR_FSCL_2MHZ 4
737
738 /** Get Max Data Speed (GETMXDS) - Clock to Data Turnaround <= 8ns. */
739 #define I3C_CCC_GETMXDS_TSCO_8NS 0
740
741 /** Get Max Data Speed (GETMXDS) - Clock to Data Turnaround <= 9ns. */
742 #define I3C_CCC_GETMXDS_TSCO_9NS 1
743
744 /** Get Max Data Speed (GETMXDS) - Clock to Data Turnaround <= 10ns. */
745 #define I3C_CCC_GETMXDS_TSCO_10NS 2
746
747 /** Get Max Data Speed (GETMXDS) - Clock to Data Turnaround <= 11ns. */
748 #define I3C_CCC_GETMXDS_TSCO_11NS 3
749
750 /** Get Max Data Speed (GETMXDS) - Clock to Data Turnaround <= 12ns. */
751 #define I3C_CCC_GETMXDS_TSCO_12NS 4
752
753 /** Get Max Data Speed (GETMXDS) - Clock to Data Turnaround > 12ns. */
754 #define I3C_CCC_GETMXDS_TSCO_GT_12NS 7
755
756 /** Get Max Data Speed (GETMXDS) - maxWr - Optional Defining Byte Support. */
757 #define I3C_CCC_GETMXDS_MAXWR_DEFINING_BYTE_SUPPORT BIT(3)
758
759 /** Get Max Data Speed (GETMXDS) - Max Sustained Data Rate bit shift value. */
760 #define I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_SHIFT 0
761
762 /** Get Max Data Speed (GETMXDS) - Max Sustained Data Rate bitmask. */
763 #define I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_MASK \
764 (0x07U << I3C_CCC_GET_MXDS_MAXWR_MAX_SDR_FSCL_SHIFT)
765
766 /**
767 * @brief Get Max Data Speed (GETMXDS) - maxWr - Max Sustained Data Rate
768 *
769 * Obtain Max Sustained Data Rate value from GETMXDS maxWr value
770 * obtained via GETMXDS.
771 *
772 * @param maxwr GETMXDS maxWr value.
773 */
774 #define I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL(maxwr) \
775 (((maxwr) & \
776 I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_MASK) \
777 >> I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_SHIFT)
778
779 /** Get Max Data Speed (GETMXDS) - maxRd - Write-to-Read Permits Stop Between. */
780 #define I3C_CCC_GETMXDS_MAXRD_W2R_PERMITS_STOP_BETWEEN BIT(6)
781
782 /** Get Max Data Speed (GETMXDS) - maxRd - Clock to Data Turnaround bit shift value. */
783 #define I3C_CCC_GETMXDS_MAXRD_TSCO_SHIFT 3
784
785 /** Get Max Data Speed (GETMXDS) - maxRd - Clock to Data Turnaround bitmask. */
786 #define I3C_CCC_GETMXDS_MAXRD_TSCO_MASK \
787 (0x07U << I3C_CCC_GETMXDS_MAXRD_TSCO_SHIFT)
788
789 /**
790 * @brief Get Max Data Speed (GETMXDS) - maxRd - Clock to Data Turnaround
791 *
792 * Obtain Clock to Data Turnaround value from GETMXDS maxRd value
793 * obtained via GETMXDS.
794 *
795 * @param maxrd GETMXDS maxRd value.
796 */
797 #define I3C_CCC_GETMXDS_MAXRD_TSCO(maxrd) \
798 (((maxrd) & I3C_CCC_GETMXDS_MAXRD_TSCO_MASK) \
799 >> I3C_CCC_GETMXDS_MAXRD_TSCO_SHIFT)
800
801 /** Get Max Data Speed (GETMXDS) - maxRd - Max Sustained Data Rate bit shift value. */
802 #define I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_SHIFT 0
803
804 /** Get Max Data Speed (GETMXDS) - maxRd - Max Sustained Data Rate bitmask. */
805 #define I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_MASK \
806 (0x07U << I3C_CCC_GET_MXDS_MAXRD_MAX_SDR_FSCL_SHIFT)
807
808 /**
809 * @brief Get Max Data Speed (GETMXDS) - maxRd - Max Sustained Data Rate
810 *
811 * Obtain Max Sustained Data Rate value from GETMXDS maxRd value
812 * obtained via GETMXDS.
813 *
814 * @param maxrd GETMXDS maxRd value.
815 */
816 #define I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL(maxrd) \
817 (((maxrd) & \
818 I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_MASK) \
819 >> I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_SHIFT)
820
821 /** Get Max Data Speed (GETMXDS) - CRDHLY1 - Set Bus Activity State bit shift value. */
822 #define I3C_CCC_GETMXDS_CRDHLY1_SET_BUS_ACT_STATE BIT(2)
823
824 /** Get Max Data Speed (GETMXDS) - CRDHLY1 - Controller Handoff Activity State bit shift value. */
825 #define I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE_SHIFT 0
826
827 /** Get Max Data Speed (GETMXDS) - CRDHLY1 - Controller Handoff Activity State bitmask. */
828 #define I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE_MASK \
829 (0x03U << I3C_CCC_GETMXDS_CRDHLY1_SET_BUS_ACT_STATE_SHIFT)
830
831 /**
832 * @brief Get Max Data Speed (GETMXDS) - CRDHLY1 - Controller Handoff Activity State
833 *
834 * Obtain Controller Handoff Activity State value from GETMXDS value
835 * obtained via GETMXDS.
836 *
837 * @param crhdly1 GETMXDS value.
838 */
839 #define I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE(crhdly1) \
840 (((crhdly1) & \
841 I3C_CCC_GETMXDS_CRDHLY1_SET_BUS_ACT_STATE_MASK) \
842 >> I3C_CCC_GETMXDS_CRDHLY1_SET_BUS_ACT_STATE_SHIFT)
843
844 /**
845 * @brief Payload for GETCAPS CCC (Get Optional Feature Capabilities).
846 *
847 * @note Only support GETCAPS Format 1.
848 */
849 struct i3c_ccc_getcaps {
850 /**
851 * GETCAP[1-4] bytes.
852 */
853 uint8_t getcaps[4];
854 } __packed;
855
856 /** Get Optional Feature Capabilities (GETCAPS) Format 1 - HDR-DDR mode bit. */
857 #define I3C_CCC_GETCAPS1_HDR_DDR BIT(0)
858
859 /** Get Optional Feature Capabilities (GETCAPS) Format 1 - HDR-BT mode bit. */
860 #define I3C_CCC_GETCAPS1_HDR_BT BIT(3)
861
862 /**
863 * @brief Get Optional Feature Capabilities (GETCAPS) - HDR Mode
864 *
865 * Get the bit corresponding to HDR mode.
866 *
867 * @param x HDR mode
868 */
869 #define I3C_CCC_GETCAPS1_HDR_MODE(x) BIT(x)
870
871 /** Get Optional Feature Capabilities (GETCAPS) Format 1 - HDR Mode 0. */
872 #define I3C_CCC_GETCAPS1_HDR_MODE0 BIT(0)
873
874 /** Get Optional Feature Capabilities (GETCAPS) Format 1 - HDR Mode 1. */
875 #define I3C_CCC_GETCAPS1_HDR_MODE1 BIT(1)
876
877 /** Get Optional Feature Capabilities (GETCAPS) Format 1 - HDR Mode 2. */
878 #define I3C_CCC_GETCAPS1_HDR_MODE2 BIT(2)
879
880 /** Get Optional Feature Capabilities (GETCAPS) Format 1 - HDR Mode 3. */
881 #define I3C_CCC_GETCAPS1_HDR_MODE3 BIT(3)
882
883 /** Get Optional Feature Capabilities (GETCAPS) Format 1 - HDR Mode 4. */
884 #define I3C_CCC_GETCAPS1_HDR_MODE4 BIT(4)
885
886 /** Get Optional Feature Capabilities (GETCAPS) Format 1 - HDR Mode 5. */
887 #define I3C_CCC_GETCAPS1_HDR_MODE5 BIT(5)
888
889 /** Get Optional Feature Capabilities (GETCAPS) Format 1 - HDR Mode 6. */
890 #define I3C_CCC_GETCAPS1_HDR_MODE6 BIT(6)
891
892 /** Get Optional Feature Capabilities (GETCAPS) Format 1 - HDR Mode 7. */
893 #define I3C_CCC_GETCAPS1_HDR_MODE7 BIT(7)
894
895 /** Get Optional Feature Capabilities (GETCAPS) Format 2 - HDR-DDR Write Abort bit. */
896 #define I3C_CCC_GETCAPS2_HDRDDR_WRITE_ABORT BIT(6)
897
898 /** Get Optional Feature Capabilities (GETCAPS) Format 2 - HDR-DDR Abort CRC bit. */
899 #define I3C_CCC_GETCAPS2_HDRDDR_ABORT_CRC BIT(7)
900
901 /**
902 * @brief Get Optional Feature Capabilities (GETCAPS) Format 2 -
903 * Group Address Capabilities bit shift value.
904 */
905 #define I3C_CCC_GETCAPS2_GRPADDR_CAP_SHIFT 4
906
907 /**
908 * @brief Get Optional Feature Capabilities (GETCAPS) Format 2 -
909 * Group Address Capabilities bitmask.
910 */
911 #define I3C_CCC_GETCAPS2_GRPADDR_CAP_MASK \
912 (0x03U << I3C_CCC_GETCAPS2_GRPADDR_CAP_SHIFT)
913
914 /**
915 * @brief Get Optional Feature Capabilities (GETCAPS) Format 2 - Group Address Capabilities.
916 *
917 * Obtain Group Address Capabilities value from GETCAPS Format 2 value
918 * obtained via GETCAPS.
919 *
920 * @param getcaps2 GETCAPS2 value.
921 */
922 #define I3C_CCC_GETCAPS2_GRPADDR_CAP(getcaps2) \
923 (((getcaps2) & \
924 I3C_CCC_GETCAPS2_GRPADDR_CAP_MASK) \
925 >> I3C_CCC_GETCAPS_GRPADDR_CAP_SHIFT)
926
927 /**
928 * @brief Get Optional Feature Capabilities (GETCAPS) Format 2 -
929 * I3C 1.x Specification Version bit shift value.
930 */
931 #define I3C_CCC_GETCAPS2_SPEC_VER_SHIFT 0
932
933 /**
934 * @brief Get Optional Feature Capabilities (GETCAPS) Format 2 -
935 * I3C 1.x Specification Version bitmask.
936 */
937 #define I3C_CCC_GETCAPS2_SPEC_VER_MASK \
938 (0x0FU << I3C_CCC_GETCAPS2_SPEC_VER_SHIFT)
939
940 /**
941 * @brief Get Optional Feature Capabilities (GETCAPS) Format 2 -
942 * I3C 1.x Specification Version.
943 *
944 * Obtain I3C 1.x Specification Version value from GETCAPS Format 2 value
945 * obtained via GETCAPS.
946 *
947 * @param getcaps2 GETCAPS2 value.
948 */
949 #define I3C_CCC_GETCAPS2_SPEC_VER(getcaps2) \
950 (((getcaps2) & \
951 I3C_CCC_GETCAPS2_SPEC_VER_MASK) \
952 >> I3C_CCC_GETCAPS_SPEC_VER_SHIFT)
953
954 /**
955 * @brief Get Optional Feature Capabilities (GETCAPS) Format 3 -
956 * Multi-Lane Data Transfer Support bit.
957 */
958 #define I3C_CCC_GETCAPS3_MLANE_SUPPORT BIT(0)
959
960 /**
961 * @brief Get Optional Feature Capabilities (GETCAPS) Format 3 -
962 * Device to Device Transfer (D2DXFER) Support bit.
963 */
964 #define I3C_CCC_GETCAPS3_D2DXFER_SUPPORT BIT(1)
965
966 /**
967 * @brief Get Optional Feature Capabilities (GETCAPS) Format 3 -
968 * Device to Device Transfer (D2DXFER) IBI Capable bit.
969 */
970 #define I3C_CCC_GETCAPS3_D2DXFER_IBI_CAPABLE BIT(2)
971
972 /**
973 * @brief Get Optional Feature Capabilities (GETCAPS) Format 3 -
974 * Defining Byte Support in GETCAPS bit.
975 */
976 #define I3C_CCC_GETCAPS3_GETCAPS_DEFINING_BYTE_SUPPORT BIT(3)
977
978 /**
979 * @brief Get Optional Feature Capabilities (GETCAPS) Format 3 -
980 * Defining Byte Support in GETSTATUS bit.
981 */
982 #define I3C_CCC_GETCAPS3_GETSTATUS_DEFINING_BYTE_SUPPORT BIT(4)
983
984 /**
985 * @brief Get Optional Feature Capabilities (GETCAPS) Format 3 -
986 * HDR-BT CRC-32 Support bit.
987 */
988 #define I3C_CCC_GETCAPS3_HDRBT_CRC32_SUPPORT BIT(5)
989
990 /**
991 * @brief Get Optional Feature Capabilities (GETCAPS) Format 3 -
992 * IBI MDB Support for Pending Read Notification bit.
993 */
994 #define I3C_CCC_GETCAPS3_IBI_MDR_PENDING_READ_NOTIFICATION BIT(6)
995
996 /**
997 * @brief Enum for I3C Reset Action (RSTACT) Defining Byte Values.
998 */
999 enum i3c_ccc_rstact_defining_byte {
1000 /** No Reset on Target Reset Pattern. */
1001 I3C_CCC_RSTACT_NO_RESET = 0x00U,
1002
1003 /** Reset the I3C Peripheral Only. */
1004 I3C_CCC_RSTACT_PERIPHERAL_ONLY = 0x01U,
1005
1006 /** Reset the Whole Target. */
1007 I3C_CCC_RSTACT_RESET_WHOLE_TARGET = 0x02U,
1008
1009 /** Debug Network Adapter Reset. */
1010 I3C_CCC_RSTACT_DEBUG_NETWORK_ADAPTER = 0x03U,
1011
1012 /** Virtual Target Detect. */
1013 I3C_CCC_RSTACT_VIRTUAL_TARGET_DETECT = 0x04U,
1014 };
1015
1016 /**
1017 * @brief Test if I3C CCC payload is for broadcast.
1018 *
1019 * This tests if the CCC payload is for broadcast.
1020 *
1021 * @param[in] payload Pointer to the CCC payload.
1022 *
1023 * @retval true if payload target is broadcast
1024 * @retval false if payload target is direct
1025 */
i3c_ccc_is_payload_broadcast(const struct i3c_ccc_payload * payload)1026 static inline bool i3c_ccc_is_payload_broadcast(const struct i3c_ccc_payload *payload)
1027 {
1028 return (payload->ccc.id <= I3C_CCC_BROADCAST_MAX_ID);
1029 }
1030
1031 /**
1032 * @brief Get BCR from a target
1033 *
1034 * Helper function to get BCR (Bus Characteristic Register) from
1035 * target device.
1036 *
1037 * @param[in] target Pointer to the target device descriptor.
1038 * @param[out] bcr Pointer to the BCR payload structure.
1039 *
1040 * @return @see i3c_do_ccc
1041 */
1042 int i3c_ccc_do_getbcr(struct i3c_device_desc *target,
1043 struct i3c_ccc_getbcr *bcr);
1044
1045 /**
1046 * @brief Get DCR from a target
1047 *
1048 * Helper function to get DCR (Device Characteristic Register) from
1049 * target device.
1050 *
1051 * @param[in] target Pointer to the target device descriptor.
1052 * @param[out] dcr Pointer to the DCR payload structure.
1053 *
1054 * @return @see i3c_do_ccc
1055 */
1056 int i3c_ccc_do_getdcr(struct i3c_device_desc *target,
1057 struct i3c_ccc_getdcr *dcr);
1058
1059 /**
1060 * @brief Get PID from a target
1061 *
1062 * Helper function to get PID (Provisioned ID) from
1063 * target device.
1064 *
1065 * @param[in] target Pointer to the target device descriptor.
1066 * @param[out] pid Pointer to the PID payload structure.
1067 *
1068 * @return @see i3c_do_ccc
1069 */
1070 int i3c_ccc_do_getpid(struct i3c_device_desc *target,
1071 struct i3c_ccc_getpid *pid);
1072
1073 /**
1074 * @brief Broadcast RSTACT to reset I3C Peripheral.
1075 *
1076 * Helper function to broadcast Target Reset Action (RSTACT) to
1077 * all connected targets to Reset the I3C Peripheral Only (0x01).
1078 *
1079 * @param[in] controller Pointer to the controller device driver instance.
1080 * @param[in] action What reset action to perform.
1081 *
1082 * @return @see i3c_do_ccc
1083 */
1084 int i3c_ccc_do_rstact_all(const struct device *controller,
1085 enum i3c_ccc_rstact_defining_byte action);
1086
1087 /**
1088 * @brief Broadcast RSTDAA to reset dynamic addresses for all targets.
1089 *
1090 * Helper function to reset dynamic addresses of all connected targets.
1091 *
1092 * @param[in] controller Pointer to the controller device driver instance.
1093 *
1094 * @return @see i3c_do_ccc
1095 */
1096 int i3c_ccc_do_rstdaa_all(const struct device *controller);
1097
1098 /**
1099 * @brief Set Dynamic Address from Static Address for a target
1100 *
1101 * Helper function to do SETDASA (Set Dynamic Address from Static Address)
1102 * for a particular target.
1103 *
1104 * Note this does not update @p target with the new dynamic address.
1105 *
1106 * @param[in] target Pointer to the target device descriptor where
1107 * the device is configured with a static address.
1108 *
1109 * @return @see i3c_do_ccc
1110 */
1111 int i3c_ccc_do_setdasa(const struct i3c_device_desc *target);
1112
1113 /**
1114 * @brief Set New Dynamic Address for a target
1115 *
1116 * Helper function to do SETNEWDA(Set New Dynamic Address) for a particular target.
1117 *
1118 * Note this does not update @p target with the new dynamic address.
1119 *
1120 * @param[in] target Pointer to the target device descriptor where
1121 * the device is configured with a static address.
1122 * @param[in] new_da Pointer to the new_da struct.
1123 *
1124 * @return @see i3c_do_ccc
1125 */
1126 int i3c_ccc_do_setnewda(const struct i3c_device_desc *target,
1127 struct i3c_ccc_address new_da);
1128
1129 /**
1130 * @brief Broadcast ENEC/DISEC to enable/disable target events.
1131 *
1132 * Helper function to broadcast Target Events Command to enable or
1133 * disable target events (ENEC/DISEC).
1134 *
1135 * @param[in] controller Pointer to the controller device driver instance.
1136 * @param[in] enable ENEC if true, DISEC if false.
1137 * @param[in] events Pointer to the event struct.
1138 *
1139 * @return @see i3c_do_ccc
1140 */
1141 int i3c_ccc_do_events_all_set(const struct device *controller,
1142 bool enable, struct i3c_ccc_events *events);
1143
1144 /**
1145 * @brief Direct CCC ENEC/DISEC to enable/disable target events.
1146 *
1147 * Helper function to send Target Events Command to enable or
1148 * disable target events (ENEC/DISEC) on a single target.
1149 *
1150 * @param[in] target Pointer to the target device descriptor.
1151 * @param[in] enable ENEC if true, DISEC if false.
1152 * @param[in] events Pointer to the event struct.
1153 *
1154 * @return @see i3c_do_ccc
1155 */
1156 int i3c_ccc_do_events_set(struct i3c_device_desc *target,
1157 bool enable, struct i3c_ccc_events *events);
1158
1159 /**
1160 * @brief Broadcast SETMWL to Set Maximum Write Length.
1161 *
1162 * Helper function to do SETMWL (Set Maximum Write Length) to
1163 * all connected targets.
1164 *
1165 * @param[in] controller Pointer to the controller device driver instance.
1166 * @param[in] mwl Pointer to SETMWL payload.
1167 *
1168 * @return @see i3c_do_ccc
1169 */
1170 int i3c_ccc_do_setmwl_all(const struct device *controller,
1171 const struct i3c_ccc_mwl *mwl);
1172
1173 /**
1174 * @brief Single target SETMWL to Set Maximum Write Length.
1175 *
1176 * Helper function to do SETMWL (Set Maximum Write Length) to
1177 * one target.
1178 *
1179 * @param[in] target Pointer to the target device descriptor.
1180 * @param[in] mwl Pointer to SETMWL payload.
1181 *
1182 * @return @see i3c_do_ccc
1183 */
1184 int i3c_ccc_do_setmwl(const struct i3c_device_desc *target,
1185 const struct i3c_ccc_mwl *mwl);
1186
1187 /**
1188 * @brief Single target GETMWL to Get Maximum Write Length.
1189 *
1190 * Helper function to do GETMWL (Get Maximum Write Length) of
1191 * one target.
1192 *
1193 * @param[in] target Pointer to the target device descriptor.
1194 * @param[out] mwl Pointer to GETMWL payload.
1195 *
1196 * @return @see i3c_do_ccc
1197 */
1198 int i3c_ccc_do_getmwl(const struct i3c_device_desc *target,
1199 struct i3c_ccc_mwl *mwl);
1200
1201 /**
1202 * @brief Broadcast SETMRL to Set Maximum Read Length.
1203 *
1204 * Helper function to do SETMRL (Set Maximum Read Length) to
1205 * all connected targets.
1206 *
1207 * @param[in] controller Pointer to the controller device driver instance.
1208 * @param[in] mrl Pointer to SETMRL payload.
1209 * @param[in] has_ibi_size True if also sending the optional IBI payload
1210 * size. False if not sending.
1211 *
1212 * @return @see i3c_do_ccc
1213 */
1214 int i3c_ccc_do_setmrl_all(const struct device *controller,
1215 const struct i3c_ccc_mrl *mrl,
1216 bool has_ibi_size);
1217
1218 /**
1219 * @brief Single target SETMRL to Set Maximum Read Length.
1220 *
1221 * Helper function to do SETMRL (Set Maximum Read Length) to
1222 * one target.
1223 *
1224 * Note this uses the BCR of the target to determine whether
1225 * to send the optional IBI payload size.
1226 *
1227 * @param[in] target Pointer to the target device descriptor.
1228 * @param[in] mrl Pointer to SETMRL payload.
1229 *
1230 * @return @see i3c_do_ccc
1231 */
1232 int i3c_ccc_do_setmrl(const struct i3c_device_desc *target,
1233 const struct i3c_ccc_mrl *mrl);
1234
1235 /**
1236 * @brief Single target GETMRL to Get Maximum Read Length.
1237 *
1238 * Helper function to do GETMRL (Get Maximum Read Length) of
1239 * one target.
1240 *
1241 * Note this uses the BCR of the target to determine whether
1242 * to send the optional IBI payload size.
1243 *
1244 * @param[in] target Pointer to the target device descriptor.
1245 * @param[out] mrl Pointer to GETMRL payload.
1246 *
1247 * @return @see i3c_do_ccc
1248 */
1249 int i3c_ccc_do_getmrl(const struct i3c_device_desc *target,
1250 struct i3c_ccc_mrl *mrl);
1251
1252 /**
1253 * @brief Single target GETSTATUS to Get Target Status.
1254 *
1255 * Helper function to do GETSTATUS (Get Target Status) of
1256 * one target.
1257 *
1258 * Note this uses the BCR of the target to determine whether
1259 * to send the optional IBI payload size.
1260 *
1261 * @param[in] target Pointer to the target device descriptor.
1262 * @param[out] status Pointer to GETSTATUS payload.
1263 * @param[in] fmt Which GETSTATUS to use.
1264 * @param[in] defbyte Defining Byte if using format 2.
1265 *
1266 * @return @see i3c_do_ccc
1267 */
1268 int i3c_ccc_do_getstatus(const struct i3c_device_desc *target,
1269 union i3c_ccc_getstatus *status,
1270 enum i3c_ccc_getstatus_fmt fmt,
1271 enum i3c_ccc_getstatus_defbyte defbyte);
1272
1273 /**
1274 * @brief Single target GETSTATUS to Get Target Status (Format 1).
1275 *
1276 * Helper function to do GETSTATUS (Get Target Status, format 1) of
1277 * one target.
1278 *
1279 * @param[in] target Pointer to the target device descriptor.
1280 * @param[out] status Pointer to GETSTATUS payload.
1281 *
1282 * @return @see i3c_do_ccc
1283 */
i3c_ccc_do_getstatus_fmt1(const struct i3c_device_desc * target,union i3c_ccc_getstatus * status)1284 static inline int i3c_ccc_do_getstatus_fmt1(const struct i3c_device_desc *target,
1285 union i3c_ccc_getstatus *status)
1286 {
1287 return i3c_ccc_do_getstatus(target, status,
1288 GETSTATUS_FORMAT_1,
1289 GETSTATUS_FORMAT_2_INVALID);
1290 }
1291
1292 /**
1293 * @brief Single target GETSTATUS to Get Target Status (Format 2).
1294 *
1295 * Helper function to do GETSTATUS (Get Target Status, format 2) of
1296 * one target.
1297 *
1298 * @param[in] target Pointer to the target device descriptor.
1299 * @param[out] status Pointer to GETSTATUS payload.
1300 * @param[in] defbyte Defining Byte for GETSTATUS format 2.
1301 *
1302 * @return @see i3c_do_ccc
1303 */
i3c_ccc_do_getstatus_fmt2(const struct i3c_device_desc * target,union i3c_ccc_getstatus * status,enum i3c_ccc_getstatus_defbyte defbyte)1304 static inline int i3c_ccc_do_getstatus_fmt2(const struct i3c_device_desc *target,
1305 union i3c_ccc_getstatus *status,
1306 enum i3c_ccc_getstatus_defbyte defbyte)
1307 {
1308 return i3c_ccc_do_getstatus(target, status,
1309 GETSTATUS_FORMAT_2, defbyte);
1310 }
1311
1312
1313 #ifdef __cplusplus
1314 }
1315 #endif
1316
1317 /**
1318 * @}
1319 */
1320
1321 #endif /* ZEPHYR_INCLUDE_DRIVERS_I3C_CCC_H_ */
1322
