HCLK_DIV_REG_TO_VAL (reference) in projects: Zephyr-Core-3.6.0

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/Zephyr-Core-3.6.0/drivers/clock_control/
D	clock_control_ast10x0.c	`44 #define HCLK_DIV_REG_TO_VAL(x) ((x == 0) ? 2 : x + 1) macro 118 clk_div = HCLK_DIV_REG_TO_VAL(FIELD_GET(HCLK_DIV_SEL, reg)); in aspeed_clock_control_get_rate()`

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