1 /*
2 * Copyright (c) 2020 Amarula Solutions.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT st_stm32_sdmmc
8
9 #include <zephyr/devicetree.h>
10 #include <zephyr/drivers/disk.h>
11 #include <zephyr/drivers/clock_control.h>
12 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
13 #include <zephyr/drivers/pinctrl.h>
14 #include <zephyr/drivers/gpio.h>
15 #include <zephyr/drivers/reset.h>
16 #include <zephyr/logging/log.h>
17 #include <zephyr/irq.h>
18 #include <soc.h>
19 #include <stm32_ll_rcc.h>
20
21 LOG_MODULE_REGISTER(stm32_sdmmc, CONFIG_SDMMC_LOG_LEVEL);
22
23 #define STM32_SDMMC_USE_DMA DT_NODE_HAS_PROP(DT_DRV_INST(0), dmas)
24
25 #if STM32_SDMMC_USE_DMA
26 #include <zephyr/drivers/dma.h>
27 #include <zephyr/drivers/dma/dma_stm32.h>
28 #include <stm32_ll_dma.h>
29 #endif
30
31 #ifndef MMC_TypeDef
32 #define MMC_TypeDef SDMMC_TypeDef
33 #endif
34
35 #ifndef SDMMC_BUS_WIDE_1B
36 #define SDMMC_BUS_WIDE_1B SDIO_BUS_WIDE_1B
37 #endif
38
39 #ifndef SDMMC_BUS_WIDE_4B
40 #define SDMMC_BUS_WIDE_4B SDIO_BUS_WIDE_4B
41 #endif
42
43 #ifndef SDMMC_BUS_WIDE_8B
44 #define SDMMC_BUS_WIDE_8B SDIO_BUS_WIDE_8B
45 #endif
46
47 typedef void (*irq_config_func_t)(const struct device *dev);
48
49 #if STM32_SDMMC_USE_DMA
50
51 static const uint32_t table_priority[] = {
52 DMA_PRIORITY_LOW,
53 DMA_PRIORITY_MEDIUM,
54 DMA_PRIORITY_HIGH,
55 DMA_PRIORITY_VERY_HIGH
56 };
57
58 struct sdmmc_dma_stream {
59 const struct device *dev;
60 uint32_t channel;
61 uint32_t channel_nb;
62 DMA_TypeDef *reg;
63 struct dma_config cfg;
64 };
65 #endif
66
67 struct stm32_sdmmc_priv {
68 irq_config_func_t irq_config;
69 struct k_sem thread_lock;
70 struct k_sem sync;
71 SD_HandleTypeDef hsd;
72 int status;
73 struct k_work work;
74 struct gpio_callback cd_cb;
75 struct gpio_dt_spec cd;
76 struct gpio_dt_spec pe;
77 struct stm32_pclken *pclken;
78 const struct pinctrl_dev_config *pcfg;
79 const struct reset_dt_spec reset;
80
81 #if STM32_SDMMC_USE_DMA
82 struct sdmmc_dma_stream dma_rx;
83 struct sdmmc_dma_stream dma_tx;
84 #endif
85 };
86
87 #ifdef CONFIG_SDMMC_STM32_HWFC
stm32_sdmmc_fc_enable(struct stm32_sdmmc_priv * priv)88 static void stm32_sdmmc_fc_enable(struct stm32_sdmmc_priv *priv)
89 {
90 MMC_TypeDef *sdmmcx = priv->hsd.Instance;
91
92 sdmmcx->CLKCR |= SDMMC_CLKCR_HWFC_EN;
93 }
94 #endif
95
stm32_sdmmc_isr(const struct device * dev)96 static void stm32_sdmmc_isr(const struct device *dev)
97 {
98 struct stm32_sdmmc_priv *priv = dev->data;
99
100 HAL_SD_IRQHandler(&priv->hsd);
101 }
102
HAL_SD_TxCpltCallback(SD_HandleTypeDef * hsd)103 void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
104 {
105 struct stm32_sdmmc_priv *priv =
106 CONTAINER_OF(hsd, struct stm32_sdmmc_priv, hsd);
107
108 priv->status = hsd->ErrorCode;
109
110 k_sem_give(&priv->sync);
111 }
112
HAL_SD_RxCpltCallback(SD_HandleTypeDef * hsd)113 void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
114 {
115 struct stm32_sdmmc_priv *priv =
116 CONTAINER_OF(hsd, struct stm32_sdmmc_priv, hsd);
117
118 priv->status = hsd->ErrorCode;
119
120 k_sem_give(&priv->sync);
121 }
122
HAL_SD_ErrorCallback(SD_HandleTypeDef * hsd)123 void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)
124 {
125 struct stm32_sdmmc_priv *priv =
126 CONTAINER_OF(hsd, struct stm32_sdmmc_priv, hsd);
127
128 priv->status = hsd->ErrorCode;
129
130 k_sem_give(&priv->sync);
131 }
132
stm32_sdmmc_clock_enable(struct stm32_sdmmc_priv * priv)133 static int stm32_sdmmc_clock_enable(struct stm32_sdmmc_priv *priv)
134 {
135 const struct device *clock;
136
137 /* HSI48 Clock is enabled through using the device tree */
138 clock = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
139
140 if (DT_INST_NUM_CLOCKS(0) > 1) {
141 if (clock_control_configure(clock,
142 (clock_control_subsys_t)&priv->pclken[1],
143 NULL) != 0) {
144 LOG_ERR("Failed to enable SDMMC domain clock");
145 return -EIO;
146 }
147 }
148
149 if (IS_ENABLED(CONFIG_SDMMC_STM32_CLOCK_CHECK)) {
150 uint32_t sdmmc_clock_rate;
151
152 if (clock_control_get_rate(clock,
153 (clock_control_subsys_t)&priv->pclken[1],
154 &sdmmc_clock_rate) != 0) {
155 LOG_ERR("Failed to get SDMMC domain clock rate");
156 return -EIO;
157 }
158
159 if (sdmmc_clock_rate != MHZ(48)) {
160 LOG_ERR("SDMMC Clock is not 48MHz (%d)", sdmmc_clock_rate);
161 return -ENOTSUP;
162 }
163 }
164
165 /* Enable the APB clock for stm32_sdmmc */
166 return clock_control_on(clock, (clock_control_subsys_t)&priv->pclken[0]);
167 }
168
stm32_sdmmc_clock_disable(struct stm32_sdmmc_priv * priv)169 static int stm32_sdmmc_clock_disable(struct stm32_sdmmc_priv *priv)
170 {
171 const struct device *clock;
172
173 clock = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
174
175 return clock_control_off(clock,
176 (clock_control_subsys_t)&priv->pclken);
177 }
178
179 #if STM32_SDMMC_USE_DMA
180
stm32_sdmmc_dma_cb(const struct device * dev,void * arg,uint32_t channel,int status)181 static void stm32_sdmmc_dma_cb(const struct device *dev, void *arg,
182 uint32_t channel, int status)
183 {
184 DMA_HandleTypeDef *hdma = arg;
185
186 if (status != 0) {
187 LOG_ERR("DMA callback error with channel %d.", channel);
188
189 }
190
191 HAL_DMA_IRQHandler(hdma);
192 }
193
stm32_sdmmc_configure_dma(DMA_HandleTypeDef * handle,struct sdmmc_dma_stream * dma)194 static int stm32_sdmmc_configure_dma(DMA_HandleTypeDef *handle, struct sdmmc_dma_stream *dma)
195 {
196 int ret;
197
198 if (!device_is_ready(dma->dev)) {
199 LOG_ERR("Failed to get dma dev");
200 return -ENODEV;
201 }
202
203 dma->cfg.user_data = handle;
204
205 ret = dma_config(dma->dev, dma->channel, &dma->cfg);
206 if (ret != 0) {
207 LOG_ERR("Failed to conig");
208 return ret;
209 }
210
211 handle->Instance = __LL_DMA_GET_STREAM_INSTANCE(dma->reg, dma->channel_nb);
212 handle->Init.Channel = dma->cfg.dma_slot * DMA_CHANNEL_1;
213 handle->Init.PeriphInc = DMA_PINC_DISABLE;
214 handle->Init.MemInc = DMA_MINC_ENABLE;
215 handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
216 handle->Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
217 handle->Init.Mode = DMA_PFCTRL;
218 handle->Init.Priority = table_priority[dma->cfg.channel_priority],
219 handle->Init.FIFOMode = DMA_FIFOMODE_ENABLE;
220 handle->Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
221 handle->Init.MemBurst = DMA_MBURST_INC4;
222 handle->Init.PeriphBurst = DMA_PBURST_INC4;
223
224 return ret;
225 }
226
stm32_sdmmc_dma_init(struct stm32_sdmmc_priv * priv)227 static int stm32_sdmmc_dma_init(struct stm32_sdmmc_priv *priv)
228 {
229 static DMA_HandleTypeDef dma_tx_handle;
230 static DMA_HandleTypeDef dma_rx_handle;
231 int err;
232
233 LOG_DBG("using dma");
234
235 err = stm32_sdmmc_configure_dma(&dma_tx_handle, &priv->dma_tx);
236 if (err) {
237 LOG_ERR("failed to init tx dma");
238 return err;
239 }
240 __HAL_LINKDMA(&priv->hsd, hdmatx, dma_tx_handle);
241 HAL_DMA_DeInit(&dma_tx_handle);
242 HAL_DMA_Init(&dma_tx_handle);
243
244 err = stm32_sdmmc_configure_dma(&dma_rx_handle, &priv->dma_rx);
245 if (err) {
246 LOG_ERR("failed to init rx dma");
247 return err;
248 }
249 __HAL_LINKDMA(&priv->hsd, hdmarx, dma_rx_handle);
250 HAL_DMA_DeInit(&dma_rx_handle);
251 HAL_DMA_Init(&dma_rx_handle);
252
253 return err;
254 }
255
256 #endif
257
stm32_sdmmc_access_init(struct disk_info * disk)258 static int stm32_sdmmc_access_init(struct disk_info *disk)
259 {
260 const struct device *dev = disk->dev;
261 struct stm32_sdmmc_priv *priv = dev->data;
262 int err;
263
264 if (priv->status == DISK_STATUS_OK) {
265 return 0;
266 }
267
268 if (priv->status == DISK_STATUS_NOMEDIA) {
269 return -ENODEV;
270 }
271
272 #if STM32_SDMMC_USE_DMA
273 err = stm32_sdmmc_dma_init(priv);
274 if (err) {
275 LOG_ERR("DMA init failed");
276 return err;
277 }
278 #endif
279
280 err = stm32_sdmmc_clock_enable(priv);
281 if (err) {
282 LOG_ERR("failed to init clocks");
283 return err;
284 }
285
286 err = reset_line_toggle_dt(&priv->reset);
287 if (err) {
288 LOG_ERR("failed to reset peripheral");
289 return err;
290 }
291
292 err = HAL_SD_Init(&priv->hsd);
293 if (err != HAL_OK) {
294 LOG_ERR("failed to init stm32_sdmmc (ErrorCode 0x%X)", priv->hsd.ErrorCode);
295 return -EIO;
296 }
297
298 #ifdef CONFIG_SDMMC_STM32_HWFC
299 stm32_sdmmc_fc_enable(priv);
300 #endif
301
302 priv->status = DISK_STATUS_OK;
303 return 0;
304 }
305
stm32_sdmmc_access_deinit(struct stm32_sdmmc_priv * priv)306 static void stm32_sdmmc_access_deinit(struct stm32_sdmmc_priv *priv)
307 {
308 HAL_SD_DeInit(&priv->hsd);
309 stm32_sdmmc_clock_disable(priv);
310 }
311
stm32_sdmmc_access_status(struct disk_info * disk)312 static int stm32_sdmmc_access_status(struct disk_info *disk)
313 {
314 const struct device *dev = disk->dev;
315 struct stm32_sdmmc_priv *priv = dev->data;
316
317 return priv->status;
318 }
319
stm32_sdmmc_access_read(struct disk_info * disk,uint8_t * data_buf,uint32_t start_sector,uint32_t num_sector)320 static int stm32_sdmmc_access_read(struct disk_info *disk, uint8_t *data_buf,
321 uint32_t start_sector, uint32_t num_sector)
322 {
323 const struct device *dev = disk->dev;
324 struct stm32_sdmmc_priv *priv = dev->data;
325 int err;
326
327 k_sem_take(&priv->thread_lock, K_FOREVER);
328
329 #if STM32_SDMMC_USE_DMA || IS_ENABLED(DT_PROP(DT_DRV_INST(0), idma))
330 err = HAL_SD_ReadBlocks_DMA(&priv->hsd, data_buf, start_sector,
331 num_sector);
332 #else
333 err = HAL_SD_ReadBlocks_IT(&priv->hsd, data_buf, start_sector,
334 num_sector);
335 #endif
336 if (err != HAL_OK) {
337 LOG_ERR("sd read block failed %d", err);
338 err = -EIO;
339 goto end;
340 }
341
342 k_sem_take(&priv->sync, K_FOREVER);
343
344 if (priv->status != DISK_STATUS_OK) {
345 LOG_ERR("sd read error %d", priv->status);
346 err = -EIO;
347 goto end;
348 }
349
350 while (HAL_SD_GetCardState(&priv->hsd) != HAL_SD_CARD_TRANSFER) {
351 }
352
353 end:
354 k_sem_give(&priv->thread_lock);
355 return err;
356 }
357
stm32_sdmmc_access_write(struct disk_info * disk,const uint8_t * data_buf,uint32_t start_sector,uint32_t num_sector)358 static int stm32_sdmmc_access_write(struct disk_info *disk,
359 const uint8_t *data_buf,
360 uint32_t start_sector, uint32_t num_sector)
361 {
362 const struct device *dev = disk->dev;
363 struct stm32_sdmmc_priv *priv = dev->data;
364 int err;
365
366 k_sem_take(&priv->thread_lock, K_FOREVER);
367
368 #if STM32_SDMMC_USE_DMA || IS_ENABLED(DT_PROP(DT_DRV_INST(0), idma))
369 err = HAL_SD_WriteBlocks_DMA(&priv->hsd, (uint8_t *)data_buf, start_sector,
370 num_sector);
371 #else
372 err = HAL_SD_WriteBlocks_IT(&priv->hsd, (uint8_t *)data_buf, start_sector,
373 num_sector);
374 #endif
375 if (err != HAL_OK) {
376 LOG_ERR("sd write block failed %d", err);
377 err = -EIO;
378 goto end;
379 }
380
381 k_sem_take(&priv->sync, K_FOREVER);
382
383 if (priv->status != DISK_STATUS_OK) {
384 LOG_ERR("sd write error %d", priv->status);
385 err = -EIO;
386 goto end;
387 }
388
389 while (HAL_SD_GetCardState(&priv->hsd) != HAL_SD_CARD_TRANSFER) {
390 }
391
392 end:
393 k_sem_give(&priv->thread_lock);
394 return err;
395 }
396
stm32_sdmmc_access_ioctl(struct disk_info * disk,uint8_t cmd,void * buff)397 static int stm32_sdmmc_access_ioctl(struct disk_info *disk, uint8_t cmd,
398 void *buff)
399 {
400 const struct device *dev = disk->dev;
401 struct stm32_sdmmc_priv *priv = dev->data;
402 HAL_SD_CardInfoTypeDef info;
403 int err;
404
405 switch (cmd) {
406 case DISK_IOCTL_GET_SECTOR_COUNT:
407 err = HAL_SD_GetCardInfo(&priv->hsd, &info);
408 if (err != HAL_OK) {
409 return -EIO;
410 }
411 *(uint32_t *)buff = info.LogBlockNbr;
412 break;
413 case DISK_IOCTL_GET_SECTOR_SIZE:
414 err = HAL_SD_GetCardInfo(&priv->hsd, &info);
415 if (err != HAL_OK) {
416 return -EIO;
417 }
418 *(uint32_t *)buff = info.LogBlockSize;
419 break;
420 case DISK_IOCTL_GET_ERASE_BLOCK_SZ:
421 *(uint32_t *)buff = 1;
422 break;
423 case DISK_IOCTL_CTRL_SYNC:
424 /* we use a blocking API, so nothing to do for sync */
425 break;
426 default:
427 return -EINVAL;
428 }
429 return 0;
430 }
431
432 static const struct disk_operations stm32_sdmmc_ops = {
433 .init = stm32_sdmmc_access_init,
434 .status = stm32_sdmmc_access_status,
435 .read = stm32_sdmmc_access_read,
436 .write = stm32_sdmmc_access_write,
437 .ioctl = stm32_sdmmc_access_ioctl,
438 };
439
440 static struct disk_info stm32_sdmmc_info = {
441 .name = CONFIG_SDMMC_VOLUME_NAME,
442 .ops = &stm32_sdmmc_ops,
443 };
444
445 /*
446 * Check if the card is present or not. If no card detect gpio is set, assume
447 * the card is present. If reading the gpio fails for some reason, assume the
448 * card is there.
449 */
stm32_sdmmc_card_present(struct stm32_sdmmc_priv * priv)450 static bool stm32_sdmmc_card_present(struct stm32_sdmmc_priv *priv)
451 {
452 int err;
453
454 if (!priv->cd.port) {
455 return true;
456 }
457
458 err = gpio_pin_get_dt(&priv->cd);
459 if (err < 0) {
460 LOG_WRN("reading card detect failed %d", err);
461 return true;
462 }
463 return err;
464 }
465
stm32_sdmmc_cd_handler(struct k_work * item)466 static void stm32_sdmmc_cd_handler(struct k_work *item)
467 {
468 struct stm32_sdmmc_priv *priv = CONTAINER_OF(item,
469 struct stm32_sdmmc_priv,
470 work);
471
472 if (stm32_sdmmc_card_present(priv)) {
473 LOG_DBG("card inserted");
474 priv->status = DISK_STATUS_UNINIT;
475 } else {
476 LOG_DBG("card removed");
477 stm32_sdmmc_access_deinit(priv);
478 priv->status = DISK_STATUS_NOMEDIA;
479 }
480 }
481
stm32_sdmmc_cd_callback(const struct device * gpiodev,struct gpio_callback * cb,uint32_t pin)482 static void stm32_sdmmc_cd_callback(const struct device *gpiodev,
483 struct gpio_callback *cb,
484 uint32_t pin)
485 {
486 struct stm32_sdmmc_priv *priv = CONTAINER_OF(cb,
487 struct stm32_sdmmc_priv,
488 cd_cb);
489
490 k_work_submit(&priv->work);
491 }
492
stm32_sdmmc_card_detect_init(struct stm32_sdmmc_priv * priv)493 static int stm32_sdmmc_card_detect_init(struct stm32_sdmmc_priv *priv)
494 {
495 int err;
496
497 if (!priv->cd.port) {
498 return 0;
499 }
500
501 if (!gpio_is_ready_dt(&priv->cd)) {
502 return -ENODEV;
503 }
504
505 gpio_init_callback(&priv->cd_cb, stm32_sdmmc_cd_callback,
506 1 << priv->cd.pin);
507
508 err = gpio_add_callback(priv->cd.port, &priv->cd_cb);
509 if (err) {
510 return err;
511 }
512
513 err = gpio_pin_configure_dt(&priv->cd, GPIO_INPUT);
514 if (err) {
515 goto remove_callback;
516 }
517
518 err = gpio_pin_interrupt_configure_dt(&priv->cd, GPIO_INT_EDGE_BOTH);
519 if (err) {
520 goto unconfigure_pin;
521 }
522 return 0;
523
524 unconfigure_pin:
525 gpio_pin_configure_dt(&priv->cd, GPIO_DISCONNECTED);
526 remove_callback:
527 gpio_remove_callback(priv->cd.port, &priv->cd_cb);
528 return err;
529 }
530
stm32_sdmmc_card_detect_uninit(struct stm32_sdmmc_priv * priv)531 static int stm32_sdmmc_card_detect_uninit(struct stm32_sdmmc_priv *priv)
532 {
533 if (!priv->cd.port) {
534 return 0;
535 }
536
537 gpio_pin_interrupt_configure_dt(&priv->cd, GPIO_INT_MODE_DISABLED);
538 gpio_pin_configure_dt(&priv->cd, GPIO_DISCONNECTED);
539 gpio_remove_callback(priv->cd.port, &priv->cd_cb);
540 return 0;
541 }
542
stm32_sdmmc_pwr_init(struct stm32_sdmmc_priv * priv)543 static int stm32_sdmmc_pwr_init(struct stm32_sdmmc_priv *priv)
544 {
545 int err;
546
547 if (!priv->pe.port) {
548 return 0;
549 }
550
551 if (!gpio_is_ready_dt(&priv->pe)) {
552 return -ENODEV;
553 }
554
555 err = gpio_pin_configure_dt(&priv->pe, GPIO_OUTPUT_ACTIVE);
556 if (err) {
557 return err;
558 }
559
560 k_sleep(K_MSEC(50));
561
562 return 0;
563 }
564
stm32_sdmmc_pwr_uninit(struct stm32_sdmmc_priv * priv)565 static int stm32_sdmmc_pwr_uninit(struct stm32_sdmmc_priv *priv)
566 {
567 if (!priv->pe.port) {
568 return 0;
569 }
570
571 gpio_pin_configure_dt(&priv->pe, GPIO_DISCONNECTED);
572 return 0;
573 }
574
disk_stm32_sdmmc_init(const struct device * dev)575 static int disk_stm32_sdmmc_init(const struct device *dev)
576 {
577 struct stm32_sdmmc_priv *priv = dev->data;
578 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
579 int err;
580
581 if (!device_is_ready(clk)) {
582 LOG_ERR("clock control device not ready");
583 return -ENODEV;
584 }
585
586 if (!device_is_ready(priv->reset.dev)) {
587 LOG_ERR("reset control device not ready");
588 return -ENODEV;
589 }
590
591 k_work_init(&priv->work, stm32_sdmmc_cd_handler);
592
593 /* Configure dt provided device signals when available */
594 err = pinctrl_apply_state(priv->pcfg, PINCTRL_STATE_DEFAULT);
595 if (err < 0) {
596 return err;
597 }
598
599 priv->irq_config(dev);
600
601 /* Initialize semaphores */
602 k_sem_init(&priv->thread_lock, 1, 1);
603 k_sem_init(&priv->sync, 0, 1);
604
605 err = stm32_sdmmc_card_detect_init(priv);
606 if (err) {
607 return err;
608 }
609
610 err = stm32_sdmmc_pwr_init(priv);
611 if (err) {
612 goto err_card_detect;
613 }
614
615 if (stm32_sdmmc_card_present(priv)) {
616 priv->status = DISK_STATUS_UNINIT;
617 } else {
618 priv->status = DISK_STATUS_NOMEDIA;
619 }
620
621 stm32_sdmmc_info.dev = dev;
622 err = disk_access_register(&stm32_sdmmc_info);
623 if (err) {
624 goto err_pwr;
625 }
626 return 0;
627
628 err_pwr:
629 stm32_sdmmc_pwr_uninit(priv);
630 err_card_detect:
631 stm32_sdmmc_card_detect_uninit(priv);
632 return err;
633 }
634
635 #if DT_NODE_HAS_STATUS(DT_DRV_INST(0), okay)
636
637 #if STM32_SDMMC_USE_DMA
638
639 #define SDMMC_DMA_CHANNEL_INIT(dir, dir_cap) \
640 .dev = DEVICE_DT_GET(STM32_DMA_CTLR(0, dir)), \
641 .channel = DT_INST_DMAS_CELL_BY_NAME(0, dir, channel), \
642 .channel_nb = DT_DMAS_CELL_BY_NAME( \
643 DT_DRV_INST(0), dir, channel), \
644 .reg = (DMA_TypeDef *)DT_REG_ADDR( \
645 DT_PHANDLE_BY_NAME(DT_DRV_INST(0), dmas, dir)), \
646 .cfg = { \
647 .dma_slot = STM32_DMA_SLOT(0, dir, slot), \
648 .channel_priority = STM32_DMA_CONFIG_PRIORITY( \
649 STM32_DMA_CHANNEL_CONFIG(0, dir)), \
650 .dma_callback = stm32_sdmmc_dma_cb, \
651 .linked_channel = STM32_DMA_HAL_OVERRIDE, \
652 }, \
653
654
655 #define SDMMC_DMA_CHANNEL(dir, DIR) \
656 .dma_##dir = { \
657 COND_CODE_1(DT_INST_DMAS_HAS_NAME(0, dir), \
658 (SDMMC_DMA_CHANNEL_INIT(dir, DIR)), \
659 (NULL)) \
660 },
661
662 #else
663 #define SDMMC_DMA_CHANNEL(dir, DIR)
664 #endif
665
666 PINCTRL_DT_INST_DEFINE(0);
667
stm32_sdmmc_irq_config_func(const struct device * dev)668 static void stm32_sdmmc_irq_config_func(const struct device *dev)
669 {
670 IRQ_CONNECT(DT_INST_IRQN(0),
671 DT_INST_IRQ(0, priority),
672 stm32_sdmmc_isr, DEVICE_DT_INST_GET(0),
673 0);
674 irq_enable(DT_INST_IRQN(0));
675 }
676
677 #if DT_INST_PROP(0, bus_width) == 1
678 #define SDMMC_BUS_WIDTH SDMMC_BUS_WIDE_1B
679 #elif DT_INST_PROP(0, bus_width) == 4
680 #define SDMMC_BUS_WIDTH SDMMC_BUS_WIDE_4B
681 #elif DT_INST_PROP(0, bus_width) == 8
682 #define SDMMC_BUS_WIDTH SDMMC_BUS_WIDE_8B
683 #endif /* DT_INST_PROP(0, bus_width) */
684
685 static struct stm32_pclken pclken_sdmmc[] = STM32_DT_INST_CLOCKS(0);
686
687 static struct stm32_sdmmc_priv stm32_sdmmc_priv_1 = {
688 .irq_config = stm32_sdmmc_irq_config_func,
689 .hsd = {
690 .Instance = (MMC_TypeDef *)DT_INST_REG_ADDR(0),
691 .Init.BusWide = SDMMC_BUS_WIDTH,
692 #if DT_INST_NODE_HAS_PROP(0, clk_div)
693 .Init.ClockDiv = DT_INST_PROP(0, clk_div),
694 #endif
695 },
696 #if DT_INST_NODE_HAS_PROP(0, cd_gpios)
697 .cd = GPIO_DT_SPEC_INST_GET(0, cd_gpios),
698 #endif
699 #if DT_INST_NODE_HAS_PROP(0, pwr_gpios)
700 .pe = GPIO_DT_SPEC_INST_GET(0, pwr_gpios),
701 #endif
702 .pclken = pclken_sdmmc,
703 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
704 .reset = RESET_DT_SPEC_INST_GET(0),
705 SDMMC_DMA_CHANNEL(rx, RX)
706 SDMMC_DMA_CHANNEL(tx, TX)
707 };
708
709 DEVICE_DT_INST_DEFINE(0, disk_stm32_sdmmc_init, NULL,
710 &stm32_sdmmc_priv_1, NULL, POST_KERNEL,
711 CONFIG_SD_INIT_PRIORITY,
712 NULL);
713 #endif
714
