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Searched refs:GENMASK (Results 1 – 25 of 128) sorted by relevance

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/Zephyr-Core-3.6.0/soc/xtensa/intel_adsp/ace/
Dcomm_widget.h33 #define DSATTR_DSTPID GENMASK(7, 0)
41 #define DSATTR_SRCPID GENMASK(15, 8)
49 #define DSATTR_OPC GENMASK(23, 16)
57 #define DSATTR_BE GENMASK(27, 24)
63 #define DSATTR_RSVD31 GENMASK(31, 28)
90 #define DSUADDR_UADDR GENMASK(15, 0)
96 #define DSUADDR_RSVD30 GENMASK(30, 16)
121 #define DSSAI_SAI GENMASK(15, 0)
129 #define DSSAI_RS GENMASK(19, 16)
135 #define DSSAI_RSVD30 GENMASK(30, 20)
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Dpmc_interface.h20 #define CW_PMC_IPC_OP_CODE GENMASK(7, 0)
26 #define CW_PMC_IPC_CC GENMASK(7, 0)
31 #define CW_PMC_IPC_PARAM1 GENMASK(15, 8)
36 #define CW_PMC_IPC_PARAM2 GENMASK(23, 16)
41 #define CW_PMC_IPC_PARAM3 GENMASK(27, 24)
46 #define CW_PMC_IPC_RSVD GENMASK(30, 28)
80 #define CW_PMC_IPC_SRAM_USED_BANKS GENMASK(17, 8)
85 #define CW_PMC_IPC_SRAM_RESERVED GENMASK(30, 18)
/Zephyr-Core-3.6.0/soc/xtensa/intel_adsp/ace/include/
Ddmic_regs.h40 #define TS_LOCAL_TSCTRL_DMATS GENMASK(13, 12)
43 #define TS_LOCAL_TSCTRL_CLNKS GENMASK(11, 10)
55 #define TS_LOCAL_TSCTRL_CDMAS GENMASK(4, 0)
58 #define TS_LOCAL_OFFS_FRM GENMASK(15, 12)
61 #define TS_LOCAL_OFFS_CLK GENMASK(11, 0)
167 #define OUTCONTROL_BFTH GENMASK(23, 20)
170 #define OUTCONTROL_OF GENMASK(19, 18)
174 #define OUTCONTROL_IPM GENMASK(17, 15)
177 #define OUTCONTROL_IPM_SOURCE_1 GENMASK(14, 13)
180 #define OUTCONTROL_IPM_SOURCE_2 GENMASK(12, 11)
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/Zephyr-Core-3.6.0/soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/
Ddmic_regs.h52 #define TS_LOCAL_TSCTRL_CDMAS GENMASK(4, 0)
55 #define TS_LOCAL_OFFS_FRM GENMASK(15, 12)
58 #define TS_LOCAL_OFFS_CLK GENMASK(11, 0)
164 #define OUTCONTROL_BFTH GENMASK(23, 20)
167 #define OUTCONTROL_OF GENMASK(19, 18)
171 #define OUTCONTROL_IPM GENMASK(17, 16)
174 #define OUTCONTROL_IPM_SOURCE_1 GENMASK(14, 13)
177 #define OUTCONTROL_IPM_SOURCE_2 GENMASK(12, 11)
180 #define OUTCONTROL_IPM_SOURCE_3 GENMASK(10, 9)
183 #define OUTCONTROL_IPM_SOURCE_4 GENMASK(8, 7)
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/Zephyr-Core-3.6.0/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/
Ddmic_regs_ace1x.h17 #define DMICLCAP_LCOUNT GENMASK(2, 0)
38 #define DMICLCAP_PGD GENMASK(30, 28)
45 #define DMICIPPTR_PTR GENMASK(20, 0)
48 #define DMICIPPTR_VER GENMASK(23, 21)
55 #define DMICSYNC_SYNCPRD GENMASK(14, 0)
74 #define DMICPCMSCAP_ISS GENMASK(3, 0)
77 #define DMICPCMSCAP_OSS GENMASK(7, 4)
80 #define DMICPCMSCAP_BSS GENMASK(12, 8)
91 #define DMICPCMSyCM_LCHAN GENMASK(3, 0)
94 #define DMICPCMSyCM_HCHAN GENMASK(7, 4)
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/Zephyr-Core-3.6.0/drivers/ethernet/
Deth_smsc91x_priv.h13 #define BSR_BANK_MASK GENMASK(2, 0) /* Which bank is currently selected */
15 #define BSR_IDENTIFY_MASK GENMASK(15, 8)
35 #define ECR_SNGLCOL_MASK GENMASK(3, 0) /* Single collisions */
36 #define ECR_MULCOL_MASK GENMASK(7, 4) /* Multiple collisions */
37 #define ECR_TX_DEFR_MASK GENMASK(11, 8) /* Transmit deferrals */
38 #define ECR_EXC_DEFR_MASK GENMASK(15, 12) /* Excessive deferrals */
42 #define MIR_SIZE_MASK GENMASK(7, 0) /* Memory size (2k pages) */
43 #define MIR_FREE_MASK GENMASK(15, 8) /* Memory free (2k pages) */
50 #define RPCR_LSA_MASK GENMASK(7, 5)
51 #define RPCR_LSB_MASK GENMASK(4, 2)
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Deth_dwmac_priv.h98 #define MAC_CONF_SARC GENMASK(30, 28)
100 #define MAC_CONF_IPG GENMASK(26, 24)
117 #define MAC_CONF_BL GENMASK(6, 5)
119 #define MAC_CONF_PRELEN GENMASK(3, 2)
128 #define MAC_EXT_CONF_EIPG GENMASK(29, 25)
130 #define MAC_EXT_CONF_HDSMS GENMASK(22, 20)
135 #define MAC_EXT_CONF_GPSL GENMASK(13, 0)
148 #define MAC_PKT_FILTER_PCF GENMASK(7, 6)
161 #define MAC_WDOG_TIMEOUT_WTO GENMASK(3, 0)
176 #define MAC_VLAN_TAG_CTRL_EIVLS GENMASK(29, 28)
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Doa_tc6.h16 #define MMS_REG(m, r) ((((m) & GENMASK(3, 0)) << 16) | ((r) & GENMASK(15, 0)))
30 #define OA_BUFSTS_TXC GENMASK(15, 8)
31 #define OA_BUFSTS_RCA GENMASK(7, 0)
47 #define OA_CTRL_HDR_MMS GENMASK(27, 24)
48 #define OA_CTRL_HDR_ADDR GENMASK(23, 8)
49 #define OA_CTRL_HDR_LEN GENMASK(7, 1)
58 #define OA_DATA_HDR_SWO GENMASK(19, 16)
60 #define OA_DATA_HDR_EBO GENMASK(13, 8)
67 #define OA_DATA_FTR_RCA GENMASK(28, 24)
70 #define OA_DATA_FTR_SWO GENMASK(19, 16)
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/Zephyr-Core-3.6.0/drivers/can/
Dcan_mcp251xfd.h86 #define MCP251XFD_REG_CON_TXBWS_MASK GENMASK(31, 28)
88 #define MCP251XFD_REG_CON_REQOP_MASK GENMASK(26, 24)
97 #define MCP251XFD_REG_CON_OPMOD_MASK GENMASK(23, 21)
105 #define MCP251XFD_REG_CON_WFT_MASK GENMASK(10, 9)
113 #define MCP251XFD_REG_CON_DNCNT_MASK GENMASK(4, 0)
119 #define MCP251XFD_REG_NBTCFG_BRP_MASK GENMASK(31, 24)
120 #define MCP251XFD_REG_NBTCFG_TSEG1_MASK GENMASK(23, 16)
121 #define MCP251XFD_REG_NBTCFG_TSEG2_MASK GENMASK(14, 8)
122 #define MCP251XFD_REG_NBTCFG_SJW_MASK GENMASK(6, 0)
125 #define MCP251XFD_REG_DBTCFG_BRP_MASK GENMASK(31, 24)
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/Zephyr-Core-3.6.0/drivers/charger/
Dbq24190.h14 #define BQ24190_REG_ISC_VINDPM_MASK GENMASK(6, 3)
16 #define BQ24190_REG_ISC_IINLIM_MASK GENMASK(2, 0)
25 #define BQ24190_REG_POC_CHG_CONFIG_MASK GENMASK(5, 4)
31 #define BQ24190_REG_POC_SYS_MIN_MASK GENMASK(3, 1)
40 #define BQ24190_REG_CCC_ICHG_MASK GENMASK(7, 2)
51 #define BQ24190_REG_PCTCC_IPRECHG_MASK GENMASK(7, 4)
57 #define BQ24190_REG_PCTCC_ITERM_MASK GENMASK(3, 0)
66 #define BQ24190_REG_CVC_VREG_MASK GENMASK(7, 2)
83 #define BQ24190_REG_CTTC_WATCHDOG_MASK GENMASK(5, 4)
87 #define BQ24190_REG_CTTC_CHG_TIMER_MASK GENMASK(2, 1)
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/Zephyr-Core-3.6.0/include/zephyr/drivers/can/
Dcan_mcan.h26 #define CAN_MCAN_CREL_REL GENMASK(31, 28)
27 #define CAN_MCAN_CREL_STEP GENMASK(27, 24)
28 #define CAN_MCAN_CREL_SUBSTEP GENMASK(23, 20)
29 #define CAN_MCAN_CREL_YEAR GENMASK(19, 16)
30 #define CAN_MCAN_CREL_MON GENMASK(15, 8)
31 #define CAN_MCAN_CREL_DAY GENMASK(7, 0)
35 #define CAN_MCAN_ENDN_ETV GENMASK(31, 0)
39 #define CAN_MCAN_CUST_CUST GENMASK(31, 0)
44 #define CAN_MCAN_DBTP_DBRP GENMASK(20, 16)
45 #define CAN_MCAN_DBTP_DTSEG1 GENMASK(12, 8)
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/Zephyr-Core-3.6.0/drivers/spi/
Dspi_andes_atcspi200.h48 #define TFMAT_DATA_LEN_MSK GENMASK(12, 8)
49 #define TFMAT_ADDR_LEN_MSK GENMASK(18, 16)
56 #define TCTRL_WR_TCNT_MSK GENMASK(20, 12)
57 #define TCTRL_TRNS_MODE_MSK GENMASK(27, 24)
75 #define CFG_RX_FIFO_SIZE_MSK GENMASK(3, 0)
76 #define CFG_TX_FIFO_SIZE_MSK GENMASK(7, 4)
79 #define STAT_RX_NUM_MSK GENMASK(12, 8)
80 #define STAT_TX_NUM_MSK GENMASK(20, 16)
92 #define CTRL_RX_THRES_MSK GENMASK(12, 8)
93 #define CTRL_TX_THRES_MSK GENMASK(20, 16)
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/Zephyr-Core-3.6.0/drivers/sensor/vcnl36825t/
Dvcnl36825t.h41 #define VCNL36825T_PS_ON_MSK GENMASK(1, 1)
59 #define VCNL36825T_PS_ST_MSK GENMASK(0, 0)
111 #define VCNL36825T_PS_TRIG_MSK GENMASK(5, 5)
178 #define VCNL36825T_PS_DATA_L_MSK GENMASK(7, 0)
179 #define VCNL36825T_PS_DATA_H_MSK GENMASK(11, 8)
188 #define VCNL36825T_PS_IF_AWAY_MSK GENMASK(8, 8)
189 #define VCNL36825T_PS_IF_CLOSE_MSK GENMASK(9, 9)
190 #define VCNL36825T_PS_SPFLAG_MSK GENMASK(12, 12)
191 #define VCNL36825T_PS_ACFLAG_MSK GENMASK(13, 13)
197 #define VCNL36825T_ID_MSK GENMASK(7, 0)
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/Zephyr-Core-3.6.0/drivers/flash/
Dflash_cadence_nand_ll.h21 #define GET_PAGE_SIZE(x) (FIELD_GET(GENMASK(15, 0), x))
22 #define GET_PAGES_PER_BLOCK(x) (FIELD_GET(GENMASK(15, 0), x))
23 #define GET_SPARE_SIZE(x) (FIELD_GET(GENMASK(31, 16), x))
24 #define ONFI_TIMING_MODE_SDR(x) (FIELD_GET(GENMASK(15, 0), x))
25 #define ONFI_TIMING_MODE_NVDDR(x) (FIELD_GET(GENMASK(31, 15), x))
28 #define CNF_GET_NLUNS(x) (FIELD_GET(GENMASK(7, 0), x))
29 #define CNF_GET_DEV_TYPE(x) (FIELD_GET(GENMASK(31, 30), x))
98 #define CNF_OPR_WORK_MODE_SDR_MASK (GENMASK(1, 0))
127 #define CNF_ASYNC_TIMINGS_TRH FIELD_PREP(GENMASK(28, 24), 2)
128 #define CNF_ASYNC_TIMINGS_TRP FIELD_PREP(GENMASK(20, 16), 4)
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Dflash_andes_qspi.h48 #define TFMAT_DATA_LEN_MSK GENMASK(12, 8)
57 #define TCTRL_TRNS_MODE_MSK GENMASK(27, 24)
87 #define CFG_RX_FIFO_SIZE_MSK GENMASK(3, 0)
88 #define CFG_TX_FIFO_SIZE_MSK GENMASK(7, 4)
91 #define STAT_RX_NUM_MSK GENMASK(13, 8)
92 #define STAT_TX_NUM_MSK GENMASK(21, 16)
98 #define CTRL_RX_THRES_MSK GENMASK(15, 8)
99 #define CTRL_TX_THRES_MSK GENMASK(23, 16)
102 #define TIMIN_SCLK_DIV_MSK GENMASK(7, 0)
/Zephyr-Core-3.6.0/soc/arm/microchip_mec/common/reg/
Dmec_global_cfg.h23 #define MCHP_GCFG_DEV_ID_REG_MASK GENMASK(31, 0)
25 #define MCHP_GCFG_DID_REV_MASK GENMASK(7, 0)
27 #define MCHP_GCFG_DID_SUB_ID_MASK GENMASK(15, 8)
29 #define MCHP_GCFG_DID_DEV_ID_MASK GENMASK(31, 16)
42 #define MCHP_GCFG_SUB_ID_PKG_MASK GENMASK(3, 0)
51 #define MCHP_GCFG_SUB_ID_FAM_MASK GENMASK(7, 4)
/Zephyr-Core-3.6.0/drivers/sensor/tmag5273/
Dtmag5273.h52 #define TMAG5273_CONV_AVB_MSK GENMASK(4, 2)
79 #define TMAG5273_OPERATING_MODE_MSK GENMASK(1, 0)
129 #define TMAG5273_ANGLE_EN_MSK GENMASK(3, 2)
130 #define TMAG5273_MEAS_RANGE_X_Y_MSK GENMASK(1, 1)
131 #define TMAG5273_MEAS_RANGE_Z_MSK GENMASK(0, 0)
198 #define TMAG5273_VER_MSK GENMASK(1, 0)
209 #define TMAG5273_DIAG_STATUS_MSK GENMASK(1, 1)
210 #define TMAG5273_RESULT_STATUS_MSK GENMASK(0, 0)
223 #define TMAG5273_INTB_RB_MSK GENMASK(4, 4)
224 #define TMAG5273_OSC_ER_MSK GENMASK(3, 3)
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/Zephyr-Core-3.6.0/drivers/sensor/wsen_itds/
Ditds.h35 #define ITDS_MASK_SCALE GENMASK(5, 4)
36 #define ITDS_MASK_BDU_INC_ADD GENMASK(3, 2)
37 #define ITDS_MASK_FIFOTH GENMASK(4, 0)
38 #define ITDS_MASK_FIFOMODE GENMASK(7, 5)
39 #define ITDS_MASK_MODE GENMASK(3, 0)
40 #define ITDS_MASK_SAMPLES_COUNT GENMASK(5, 0)
41 #define ITDS_MASK_ODR GENMASK(7, 4)
/Zephyr-Core-3.6.0/drivers/sensor/icm42688/
Dicm42688_reg.h17 #define MASK_BANK_SEL GENMASK(2, 0)
29 #define REG_ADDRESS_MASK GENMASK(7, 0)
30 #define REG_BANK_MASK GENMASK(15, 8)
143 #define MASK_FIFO_MODE GENMASK(7, 6)
178 #define MASK_UI_SIFS_CFG GENMASK(1, 0)
187 #define MASK_CLKSEL GENMASK(1, 0)
195 #define MASK_ACCEL_MODE GENMASK(1, 0)
199 #define MASK_GYRO_MODE GENMASK(3, 2)
207 #define MASK_GYRO_UI_FS_SEL GENMASK(7, 5)
216 #define MASK_GYRO_ODR GENMASK(3, 0)
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/Zephyr-Core-3.6.0/soc/arm/microchip_mec/mec172x/reg/
Dmec172x_pcr.h108 #define MCHP_PCR_PROC_CLK_CTRL_MASK GENMASK(7, 0)
118 #define MCHP_PCR_SLOW_CLK_CTRL_MASK GENMASK(9, 0)
122 #define MCHP_PCR_OSC_ID_MASK GENMASK(8, 0)
127 (GENMASK(11, 10) | GENMASK(8, 2))
277 #define MCHP_PCR_VTR_32K_SRC_MASK GENMASK(1, 0)
291 #define MCHP_PCR_CLK32M_CNT_MASK GENMASK(15, 0)
297 #define MCHP_PCR_CLK32M_VALID_CNT_MASK GENMASK(7, 0)
300 #define MCHP_PCR_CLK32M_CTRL_MASK (BIT(24) | BIT(4) | GENMASK(2, 0))
308 #define MCHP_PCR_CLK32M_ISTS_MASK GENMASK(6, 0)
318 #define MCHP_PCR_CLK32M_IEN_MASK GENMASK(6, 0)
/Zephyr-Core-3.6.0/soc/xtensa/intel_adsp/cavs/
Dsram.c44 ebb_avail_mask0 = (uint32_t)GENMASK(EBB_SEG_SIZE - 1, 0); in hp_sram_pm_banks()
45 ebb_avail_mask1 = (uint32_t)GENMASK(total_banks_count - in hp_sram_pm_banks()
48 ebb_avail_mask0 = (uint32_t)GENMASK(total_banks_count - 1, 0); in hp_sram_pm_banks()
54 ebb_mask0 = (uint32_t)GENMASK(EBB_SEG_SIZE - 1, 0); in hp_sram_pm_banks()
55 ebb_mask1 = (uint32_t)GENMASK(banks - EBB_SEG_SIZE - 1, in hp_sram_pm_banks()
59 ebb_mask0 = (uint32_t)GENMASK(banks - 1, 0); in hp_sram_pm_banks()
/Zephyr-Core-3.6.0/drivers/usb_c/ppc/
Dnxp_nx20p3483_priv.h19 #define NX20P3483_REG_DEVICE_ID_VENDOR_MASK GENMASK(7, 3)
21 #define NX20P3483_REG_DEVICE_ID_REVISION_MASK GENMASK(2, 0)
26 #define NX20P3483_REG_DEVICE_STATUS_MODE_MASK GENMASK(2, 0)
99 #define NX20P3483_REG_OVLO_THRESHOLD_MASK GENMASK(2, 0)
/Zephyr-Core-3.6.0/drivers/counter/
Dcounter_ace_v1x_art_regs.h21 #define ACE_TSCTRL_CDMAS_MASK GENMASK(4, 0)
25 #define ACE_TSCTRL_CLNKS_MASK GENMASK(11, 10)
26 #define ACE_TSCTRL_DMATS_MASK GENMASK(13, 12)
/Zephyr-Core-3.6.0/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/
Ddmic_regs_ace2x.h15 #define DMICSYNC_SYNCPRD GENMASK(19, 0)
31 #define DMICLCTL_SCF GENMASK(3, 0)
56 #define DMICLVSCTL_MLCS GENMASK(29, 27)
/Zephyr-Core-3.6.0/include/zephyr/dt-bindings/memory-attr/
Dmemory-attr.h16 #define DT_MEM_ATTR_MASK GENMASK(15, 0)
33 #define DT_MEM_SW_ATTR_MASK GENMASK(19, 16)
46 #define DT_MEM_ARCH_ATTR_MASK GENMASK(31, 20)

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