FIU1DIV_VAL (reference) in projects: Zephyr-Core-3.6.0

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Searched refs:FIU1DIV_VAL (Results 1 – 2 of 2) sorted by relevance

/Zephyr-Core-3.6.0/soc/arm/nuvoton_npcx/common/
D	soc_clock.h	`102 #define FIU1DIV_VAL 1 /* FIU1_CLK = CORE_CLK/2 / macro 104 #define FIU1DIV_VAL 0 / FIU1_CLK = CORE_CLK */ macro 150 #if defined(FIU1DIV_VAL) 151 #define VAL_HFCBCD ((FIU1DIV_VAL << 4) \| (FIUDIV_VAL << 2))`
/Zephyr-Core-3.6.0/drivers/clock_control/
D	clock_control_npcx.c	`94 #if defined(FIU1DIV_VAL) in npcx_clock_control_get_subsys_rate() 96 *rate = CORE_CLK/(FIU1DIV_VAL + 1); in npcx_clock_control_get_subsys_rate() 162 #if defined(FIU1DIV_VAL) 163 BUILD_ASSERT(CORE_CLK / (FIU1DIV_VAL + 1) <= (MAX_OFMCLK / 2) && 164 CORE_CLK / (FIU1DIV_VAL + 1) >= MHZ(4),`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
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Zephyr-Core-3.5.0
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