1 /* 2 * Copyright (c) 2020 ITE Corporation. All Rights Reserved. 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #ifndef CHIP_CHIPREGS_H 7 #define CHIP_CHIPREGS_H 8 9 #include <zephyr/sys/util.h> 10 11 #define EC_REG_BASE_ADDR 0x00f00000 12 13 #ifdef _ASMLANGUAGE 14 #define ECREG(x) x 15 #else 16 17 /* 18 * Macros for hardware registers access. 19 */ 20 #define ECREG(x) (*((volatile unsigned char *)(x))) 21 #define ECREG_u16(x) (*((volatile unsigned short *)(x))) 22 #define ECREG_u32(x) (*((volatile unsigned long *)(x))) 23 24 /* 25 * MASK operation macros 26 */ 27 #define SET_MASK(reg, bit_mask) ((reg) |= (bit_mask)) 28 #define CLEAR_MASK(reg, bit_mask) ((reg) &= (~(bit_mask))) 29 #define IS_MASK_SET(reg, bit_mask) (((reg) & (bit_mask)) != 0) 30 #endif /* _ASMLANGUAGE */ 31 32 #ifndef REG_BASE_ADDR 33 #define REG_BASE_ADDR EC_REG_BASE_ADDR 34 #endif 35 36 /* Common definition */ 37 /* 38 * EC clock frequency (PWM and tachometer driver need it to reply 39 * to api or calculate RPM) 40 */ 41 #ifdef CONFIG_SOC_IT8XXX2_EC_BUS_24MHZ 42 #define EC_FREQ MHZ(24) 43 #else 44 #define EC_FREQ MHZ(8) 45 46 #endif 47 48 /* --- General Control (GCTRL) --- */ 49 #define IT8XXX2_GCTRL_BASE 0x00F02000 50 #define IT8XXX2_GCTRL_EIDSR ECREG(IT8XXX2_GCTRL_BASE + 0x31) 51 52 /* --- External GPIO Control (EGPIO) --- */ 53 #define IT8XXX2_EGPIO_BASE 0x00F02100 54 #define IT8XXX2_EGPIO_EGCR ECREG(IT8XXX2_EGPIO_BASE + 0x04) 55 56 /* EGPIO register fields */ 57 /* 58 * 0x04: External GPIO Control 59 * BIT(4): EXGPIO EGAD Pin Output Driving Disable 60 */ 61 #define IT8XXX2_EGPIO_EEPODD BIT(4) 62 63 /** 64 * 65 * (11xxh) Interrupt controller (INTC) 66 * 67 */ 68 #define ISR0 ECREG(EC_REG_BASE_ADDR + 0x3F00) 69 #define ISR1 ECREG(EC_REG_BASE_ADDR + 0x3F01) 70 #define ISR2 ECREG(EC_REG_BASE_ADDR + 0x3F02) 71 #define ISR3 ECREG(EC_REG_BASE_ADDR + 0x3F03) 72 #define ISR4 ECREG(EC_REG_BASE_ADDR + 0x3F14) 73 #define ISR5 ECREG(EC_REG_BASE_ADDR + 0x3F18) 74 #define ISR6 ECREG(EC_REG_BASE_ADDR + 0x3F1C) 75 #define ISR7 ECREG(EC_REG_BASE_ADDR + 0x3F20) 76 #define ISR8 ECREG(EC_REG_BASE_ADDR + 0x3F24) 77 #define ISR9 ECREG(EC_REG_BASE_ADDR + 0x3F28) 78 #define ISR10 ECREG(EC_REG_BASE_ADDR + 0x3F2C) 79 #define ISR11 ECREG(EC_REG_BASE_ADDR + 0x3F30) 80 #define ISR12 ECREG(EC_REG_BASE_ADDR + 0x3F34) 81 #define ISR13 ECREG(EC_REG_BASE_ADDR + 0x3F38) 82 #define ISR14 ECREG(EC_REG_BASE_ADDR + 0x3F3C) 83 #define ISR15 ECREG(EC_REG_BASE_ADDR + 0x3F40) 84 #define ISR16 ECREG(EC_REG_BASE_ADDR + 0x3F44) 85 #define ISR17 ECREG(EC_REG_BASE_ADDR + 0x3F48) 86 #define ISR18 ECREG(EC_REG_BASE_ADDR + 0x3F4C) 87 #define ISR19 ECREG(EC_REG_BASE_ADDR + 0x3F50) 88 #define ISR20 ECREG(EC_REG_BASE_ADDR + 0x3F54) 89 #define ISR21 ECREG(EC_REG_BASE_ADDR + 0x3F58) 90 #define ISR22 ECREG(EC_REG_BASE_ADDR + 0x3F5C) 91 #define ISR23 ECREG(EC_REG_BASE_ADDR + 0x3F90) 92 93 #define IER0 ECREG(EC_REG_BASE_ADDR + 0x3F04) 94 #define IER1 ECREG(EC_REG_BASE_ADDR + 0x3F05) 95 #define IER2 ECREG(EC_REG_BASE_ADDR + 0x3F06) 96 #define IER3 ECREG(EC_REG_BASE_ADDR + 0x3F07) 97 #define IER4 ECREG(EC_REG_BASE_ADDR + 0x3F15) 98 #define IER5 ECREG(EC_REG_BASE_ADDR + 0x3F19) 99 #define IER6 ECREG(EC_REG_BASE_ADDR + 0x3F1D) 100 #define IER7 ECREG(EC_REG_BASE_ADDR + 0x3F21) 101 #define IER8 ECREG(EC_REG_BASE_ADDR + 0x3F25) 102 #define IER9 ECREG(EC_REG_BASE_ADDR + 0x3F29) 103 #define IER10 ECREG(EC_REG_BASE_ADDR + 0x3F2D) 104 #define IER11 ECREG(EC_REG_BASE_ADDR + 0x3F31) 105 #define IER12 ECREG(EC_REG_BASE_ADDR + 0x3F35) 106 #define IER13 ECREG(EC_REG_BASE_ADDR + 0x3F39) 107 #define IER14 ECREG(EC_REG_BASE_ADDR + 0x3F3D) 108 #define IER15 ECREG(EC_REG_BASE_ADDR + 0x3F41) 109 #define IER16 ECREG(EC_REG_BASE_ADDR + 0x3F45) 110 #define IER17 ECREG(EC_REG_BASE_ADDR + 0x3F49) 111 #define IER18 ECREG(EC_REG_BASE_ADDR + 0x3F4D) 112 #define IER19 ECREG(EC_REG_BASE_ADDR + 0x3F51) 113 #define IER20 ECREG(EC_REG_BASE_ADDR + 0x3F55) 114 #define IER21 ECREG(EC_REG_BASE_ADDR + 0x3F59) 115 #define IER22 ECREG(EC_REG_BASE_ADDR + 0x3F5D) 116 #define IER23 ECREG(EC_REG_BASE_ADDR + 0x3F91) 117 118 #define IELMR0 ECREG(EC_REG_BASE_ADDR + 0x3F08) 119 #define IELMR1 ECREG(EC_REG_BASE_ADDR + 0x3F09) 120 #define IELMR2 ECREG(EC_REG_BASE_ADDR + 0x3F0A) 121 #define IELMR3 ECREG(EC_REG_BASE_ADDR + 0x3F0B) 122 #define IELMR4 ECREG(EC_REG_BASE_ADDR + 0x3F16) 123 #define IELMR5 ECREG(EC_REG_BASE_ADDR + 0x3F1A) 124 #define IELMR6 ECREG(EC_REG_BASE_ADDR + 0x3F1E) 125 #define IELMR7 ECREG(EC_REG_BASE_ADDR + 0x3F22) 126 #define IELMR8 ECREG(EC_REG_BASE_ADDR + 0x3F26) 127 #define IELMR9 ECREG(EC_REG_BASE_ADDR + 0x3F2A) 128 #define IELMR10 ECREG(EC_REG_BASE_ADDR + 0x3F2E) 129 #define IELMR11 ECREG(EC_REG_BASE_ADDR + 0x3F32) 130 #define IELMR12 ECREG(EC_REG_BASE_ADDR + 0x3F36) 131 #define IELMR13 ECREG(EC_REG_BASE_ADDR + 0x3F3A) 132 #define IELMR14 ECREG(EC_REG_BASE_ADDR + 0x3F3E) 133 #define IELMR15 ECREG(EC_REG_BASE_ADDR + 0x3F42) 134 #define IELMR16 ECREG(EC_REG_BASE_ADDR + 0x3F46) 135 #define IELMR17 ECREG(EC_REG_BASE_ADDR + 0x3F4A) 136 #define IELMR18 ECREG(EC_REG_BASE_ADDR + 0x3F4E) 137 #define IELMR19 ECREG(EC_REG_BASE_ADDR + 0x3F52) 138 #define IELMR20 ECREG(EC_REG_BASE_ADDR + 0x3F56) 139 #define IELMR21 ECREG(EC_REG_BASE_ADDR + 0x3F5A) 140 #define IELMR22 ECREG(EC_REG_BASE_ADDR + 0x3F5E) 141 #define IELMR23 ECREG(EC_REG_BASE_ADDR + 0x3F92) 142 143 #define IPOLR0 ECREG(EC_REG_BASE_ADDR + 0x3F0C) 144 #define IPOLR1 ECREG(EC_REG_BASE_ADDR + 0x3F0D) 145 #define IPOLR2 ECREG(EC_REG_BASE_ADDR + 0x3F0E) 146 #define IPOLR3 ECREG(EC_REG_BASE_ADDR + 0x3F0F) 147 #define IPOLR4 ECREG(EC_REG_BASE_ADDR + 0x3F17) 148 #define IPOLR5 ECREG(EC_REG_BASE_ADDR + 0x3F1B) 149 #define IPOLR6 ECREG(EC_REG_BASE_ADDR + 0x3F1F) 150 #define IPOLR7 ECREG(EC_REG_BASE_ADDR + 0x3F23) 151 #define IPOLR8 ECREG(EC_REG_BASE_ADDR + 0x3F27) 152 #define IPOLR9 ECREG(EC_REG_BASE_ADDR + 0x3F2B) 153 #define IPOLR10 ECREG(EC_REG_BASE_ADDR + 0x3F2F) 154 #define IPOLR11 ECREG(EC_REG_BASE_ADDR + 0x3F33) 155 #define IPOLR12 ECREG(EC_REG_BASE_ADDR + 0x3F37) 156 #define IPOLR13 ECREG(EC_REG_BASE_ADDR + 0x3F3B) 157 #define IPOLR14 ECREG(EC_REG_BASE_ADDR + 0x3F3F) 158 #define IPOLR15 ECREG(EC_REG_BASE_ADDR + 0x3F43) 159 #define IPOLR16 ECREG(EC_REG_BASE_ADDR + 0x3F47) 160 #define IPOLR17 ECREG(EC_REG_BASE_ADDR + 0x3F4B) 161 #define IPOLR18 ECREG(EC_REG_BASE_ADDR + 0x3F4F) 162 #define IPOLR19 ECREG(EC_REG_BASE_ADDR + 0x3F53) 163 #define IPOLR20 ECREG(EC_REG_BASE_ADDR + 0x3F57) 164 #define IPOLR21 ECREG(EC_REG_BASE_ADDR + 0x3F5B) 165 #define IPOLR22 ECREG(EC_REG_BASE_ADDR + 0x3F5F) 166 #define IPOLR23 ECREG(EC_REG_BASE_ADDR + 0x3F93) 167 168 #define IVECT ECREG(EC_REG_BASE_ADDR + 0x3F10) 169 170 171 /* 172 * TODO: use pinctrl node instead of following register declarations 173 * to fix in tcpm\it83xx_pd.h. 174 */ 175 /* GPIO control register */ 176 #define GPCRF4 ECREG(EC_REG_BASE_ADDR + 0x163C) 177 #define GPCRF5 ECREG(EC_REG_BASE_ADDR + 0x163D) 178 #define GPCRH1 ECREG(EC_REG_BASE_ADDR + 0x1649) 179 #define GPCRH2 ECREG(EC_REG_BASE_ADDR + 0x164A) 180 181 /* 182 * IT8XXX2 register structure size/offset checking macro function to mitigate 183 * the risk of unexpected compiling results. 184 */ 185 #define IT8XXX2_REG_SIZE_CHECK(reg_def, size) \ 186 BUILD_ASSERT(sizeof(struct reg_def) == size, \ 187 "Failed in size check of register structure!") 188 #define IT8XXX2_REG_OFFSET_CHECK(reg_def, member, offset) \ 189 BUILD_ASSERT(offsetof(struct reg_def, member) == offset, \ 190 "Failed in offset check of register structure member!") 191 192 /** 193 * 194 * (18xxh) PWM & SmartAuto Fan Control (PWM) 195 * 196 */ 197 #ifndef __ASSEMBLER__ 198 struct pwm_it8xxx2_regs { 199 /* 0x000: Channel0 Clock Prescaler */ 200 volatile uint8_t C0CPRS; 201 /* 0x001: Cycle Time0 */ 202 volatile uint8_t CTR; 203 /* 0x002~0x00A: Reserved1 */ 204 volatile uint8_t Reserved1[9]; 205 /* 0x00B: Prescaler Clock Frequency Select */ 206 volatile uint8_t PCFSR; 207 /* 0x00C~0x00F: Reserved2 */ 208 volatile uint8_t Reserved2[4]; 209 /* 0x010: Cycle Time1 MSB */ 210 volatile uint8_t CTR1M; 211 /* 0x011~0x022: Reserved3 */ 212 volatile uint8_t Reserved3[18]; 213 /* 0x023: PWM Clock Control */ 214 volatile uint8_t ZTIER; 215 /* 0x024~0x026: Reserved4 */ 216 volatile uint8_t Reserved4[3]; 217 /* 0x027: Channel4 Clock Prescaler */ 218 volatile uint8_t C4CPRS; 219 /* 0x028: Channel4 Clock Prescaler MSB */ 220 volatile uint8_t C4MCPRS; 221 /* 0x029~0x02A: Reserved5 */ 222 volatile uint8_t Reserved5[2]; 223 /* 0x02B: Channel6 Clock Prescaler */ 224 volatile uint8_t C6CPRS; 225 /* 0x02C: Channel6 Clock Prescaler MSB */ 226 volatile uint8_t C6MCPRS; 227 /* 0x02D: Channel7 Clock Prescaler */ 228 volatile uint8_t C7CPRS; 229 /* 0x02E: Channel7 Clock Prescaler MSB */ 230 volatile uint8_t C7MCPRS; 231 /* 0x02F~0x040: Reserved6 */ 232 volatile uint8_t reserved6[18]; 233 /* 0x041: Cycle Time1 */ 234 volatile uint8_t CTR1; 235 /* 0x042: Cycle Time2 */ 236 volatile uint8_t CTR2; 237 /* 0x043: Cycle Time3 */ 238 volatile uint8_t CTR3; 239 /* 0x044~0x048: Reserved7 */ 240 volatile uint8_t reserved7[5]; 241 /* 0x049: PWM Output Open-Drain Enable */ 242 volatile uint8_t PWMODENR; 243 }; 244 #endif /* !__ASSEMBLER__ */ 245 246 /* PWM register fields */ 247 /* 0x023: PWM Clock Control */ 248 #define IT8XXX2_PWM_PCCE BIT(1) 249 /* 0x048: Tachometer Switch Control */ 250 #define IT8XXX2_PWM_T0DVS BIT(3) 251 #define IT8XXX2_PWM_T0CHSEL BIT(2) 252 #define IT8XXX2_PWM_T1DVS BIT(1) 253 #define IT8XXX2_PWM_T1CHSEL BIT(0) 254 255 256 /* --- Wake-Up Control (WUC) --- */ 257 #define IT8XXX2_WUC_BASE 0x00F01B00 258 259 /* TODO: should a defined interface for configuring wake-up interrupts */ 260 #define IT8XXX2_WUC_WUEMR1 (IT8XXX2_WUC_BASE + 0x00) 261 #define IT8XXX2_WUC_WUEMR5 (IT8XXX2_WUC_BASE + 0x0c) 262 #define IT8XXX2_WUC_WUESR1 (IT8XXX2_WUC_BASE + 0x04) 263 #define IT8XXX2_WUC_WUESR5 (IT8XXX2_WUC_BASE + 0x0d) 264 #define IT8XXX2_WUC_WUBEMR1 (IT8XXX2_WUC_BASE + 0x3c) 265 #define IT8XXX2_WUC_WUBEMR5 (IT8XXX2_WUC_BASE + 0x0f) 266 267 /** 268 * 269 * (1Dxxh) Keyboard Matrix Scan control (KSCAN) 270 * 271 */ 272 #ifndef __ASSEMBLER__ 273 struct kscan_it8xxx2_regs { 274 /* 0x000: Keyboard Scan Out */ 275 volatile uint8_t KBS_KSOL; 276 /* 0x001: Keyboard Scan Out */ 277 volatile uint8_t KBS_KSOH1; 278 /* 0x002: Keyboard Scan Out Control */ 279 volatile uint8_t KBS_KSOCTRL; 280 /* 0x003: Keyboard Scan Out */ 281 volatile uint8_t KBS_KSOH2; 282 /* 0x004: Keyboard Scan In */ 283 volatile uint8_t KBS_KSI; 284 /* 0x005: Keyboard Scan In Control */ 285 volatile uint8_t KBS_KSICTRL; 286 /* 0x006: Keyboard Scan In [7:0] GPIO Control */ 287 volatile uint8_t KBS_KSIGCTRL; 288 /* 0x007: Keyboard Scan In [7:0] GPIO Output Enable */ 289 volatile uint8_t KBS_KSIGOEN; 290 /* 0x008: Keyboard Scan In [7:0] GPIO Data */ 291 volatile uint8_t KBS_KSIGDAT; 292 /* 0x009: Keyboard Scan In [7:0] GPIO Data Mirror */ 293 volatile uint8_t KBS_KSIGDMRR; 294 /* 0x00A: Keyboard Scan Out [15:8] GPIO Control */ 295 volatile uint8_t KBS_KSOHGCTRL; 296 /* 0x00B: Keyboard Scan Out [15:8] GPIO Output Enable */ 297 volatile uint8_t KBS_KSOHGOEN; 298 /* 0x00C: Keyboard Scan Out [15:8] GPIO Data Mirror */ 299 volatile uint8_t KBS_KSOHGDMRR; 300 /* 0x00D: Keyboard Scan Out [7:0] GPIO Control */ 301 volatile uint8_t KBS_KSOLGCTRL; 302 /* 0x00E: Keyboard Scan Out [7:0] GPIO Output Enable */ 303 volatile uint8_t KBS_KSOLGOEN; 304 }; 305 #endif /* !__ASSEMBLER__ */ 306 307 /* KBS register fields */ 308 /* 0x002: Keyboard Scan Out Control */ 309 #define IT8XXX2_KBS_KSOPU BIT(2) 310 #define IT8XXX2_KBS_KSOOD BIT(0) 311 /* 0x005: Keyboard Scan In Control */ 312 #define IT8XXX2_KBS_KSIPU BIT(2) 313 /* 0x00D: Keyboard Scan Out [7:0] GPIO Control */ 314 #define IT8XXX2_KBS_KSO2GCTRL BIT(2) 315 /* 0x00E: Keyboard Scan Out [7:0] GPIO Output Enable */ 316 #define IT8XXX2_KBS_KSO2GOEN BIT(2) 317 318 319 /** 320 * 321 * (1Fxxh) External Timer & External Watchdog (ETWD) 322 * 323 */ 324 #ifndef __ASSEMBLER__ 325 struct wdt_it8xxx2_regs { 326 /* 0x000: Reserved1 */ 327 volatile uint8_t reserved1; 328 /* 0x001: External Timer1/WDT Configuration */ 329 volatile uint8_t ETWCFG; 330 /* 0x002: External Timer1 Prescaler */ 331 volatile uint8_t ET1PSR; 332 /* 0x003: External Timer1 Counter High Byte */ 333 volatile uint8_t ET1CNTLHR; 334 /* 0x004: External Timer1 Counter Low Byte */ 335 volatile uint8_t ET1CNTLLR; 336 /* 0x005: External Timer1/WDT Control */ 337 volatile uint8_t ETWCTRL; 338 /* 0x006: External WDT Counter Low Byte */ 339 volatile uint8_t EWDCNTLR; 340 /* 0x007: External WDT Key */ 341 volatile uint8_t EWDKEYR; 342 /* 0x008: Reserved2 */ 343 volatile uint8_t reserved2; 344 /* 0x009: External WDT Counter High Byte */ 345 volatile uint8_t EWDCNTHR; 346 /* 0x00A: External Timer2 Prescaler */ 347 volatile uint8_t ET2PSR; 348 /* 0x00B: External Timer2 Counter High Byte */ 349 volatile uint8_t ET2CNTLHR; 350 /* 0x00C: External Timer2 Counter Low Byte */ 351 volatile uint8_t ET2CNTLLR; 352 /* 0x00D: Reserved3 */ 353 volatile uint8_t reserved3; 354 /* 0x00E: External Timer2 Counter High Byte2 */ 355 volatile uint8_t ET2CNTLH2R; 356 }; 357 #endif /* !__ASSEMBLER__ */ 358 359 /* WDT register fields */ 360 /* 0x001: External Timer1/WDT Configuration */ 361 #define IT8XXX2_WDT_EWDKEYEN BIT(5) 362 #define IT8XXX2_WDT_EWDSRC BIT(4) 363 #define IT8XXX2_WDT_LEWDCNTL BIT(3) 364 #define IT8XXX2_WDT_LET1CNTL BIT(2) 365 #define IT8XXX2_WDT_LET1PS BIT(1) 366 #define IT8XXX2_WDT_LETWCFG BIT(0) 367 /* 0x002: External Timer1 Prescaler */ 368 #define IT8XXX2_WDT_ETPS_32P768_KHZ 0x00 369 #define IT8XXX2_WDT_ETPS_1P024_KHZ 0x01 370 #define IT8XXX2_WDT_ETPS_32_HZ 0x02 371 /* 0x005: External Timer1/WDT Control */ 372 #define IT8XXX2_WDT_EWDSCEN BIT(5) 373 #define IT8XXX2_WDT_EWDSCMS BIT(4) 374 #define IT8XXX2_WDT_ET2TC BIT(3) 375 #define IT8XXX2_WDT_ET2RST BIT(2) 376 #define IT8XXX2_WDT_ET1TC BIT(1) 377 #define IT8XXX2_WDT_ET1RST BIT(0) 378 379 /* External Timer register fields */ 380 /* External Timer 3~8 control */ 381 #define IT8XXX2_EXT_ETX_COMB_RST_EN (IT8XXX2_EXT_ETXCOMB | \ 382 IT8XXX2_EXT_ETXRST | \ 383 IT8XXX2_EXT_ETXEN) 384 #define IT8XXX2_EXT_ETXCOMB BIT(3) 385 #define IT8XXX2_EXT_ETXRST BIT(1) 386 #define IT8XXX2_EXT_ETXEN BIT(0) 387 388 /* Control external timer3~8 */ 389 #define IT8XXX2_EXT_TIMER_BASE DT_REG_ADDR(DT_NODELABEL(timer)) /*0x00F01F10*/ 390 #define IT8XXX2_EXT_CTRLX(n) ECREG(IT8XXX2_EXT_TIMER_BASE + (n << 3)) 391 #define IT8XXX2_EXT_PSRX(n) ECREG(IT8XXX2_EXT_TIMER_BASE + 0x01 + (n << 3)) 392 #define IT8XXX2_EXT_CNTX(n) ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x04 + \ 393 (n << 3)) 394 #define IT8XXX2_EXT_CNTOX(n) ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x38 + \ 395 (n << 2)) 396 397 /* Free run timer configurations */ 398 #define FREE_RUN_TIMER EXT_TIMER_4 399 #define FREE_RUN_TIMER_IRQ DT_IRQ_BY_IDX(DT_NODELABEL(timer), 1, irq) 400 /* Free run timer configurations */ 401 #define FREE_RUN_TIMER_FLAG DT_IRQ_BY_IDX(DT_NODELABEL(timer), 1, flags) 402 /* Free run timer max count is 36.4 hr (base on clock source 32768Hz) */ 403 #define FREE_RUN_TIMER_MAX_CNT 0xFFFFFFFFUL 404 405 #ifndef __ASSEMBLER__ 406 enum ext_clk_src_sel { 407 EXT_PSR_32P768K = 0, 408 EXT_PSR_1P024K, 409 EXT_PSR_32, 410 EXT_PSR_EC_CLK, 411 }; 412 /* 413 * 24-bit timers: external timer 3, 5, and 7 414 * 32-bit timers: external timer 4, 6, and 8 415 */ 416 enum ext_timer_idx { 417 EXT_TIMER_3 = 0, /* Event timer */ 418 EXT_TIMER_4, /* Free run timer */ 419 EXT_TIMER_5, /* Busy wait low timer */ 420 EXT_TIMER_6, /* Busy wait high timer */ 421 EXT_TIMER_7, 422 EXT_TIMER_8, 423 }; 424 #endif 425 426 427 /* 428 * 429 * (2Cxxh) Platform Environment Control Interface (PECI) 430 * 431 */ 432 #ifndef __ASSEMBLER__ 433 struct peci_it8xxx2_regs { 434 /* 0x00: Host Status */ 435 volatile uint8_t HOSTAR; 436 /* 0x01: Host Control */ 437 volatile uint8_t HOCTLR; 438 /* 0x02: Host Command */ 439 volatile uint8_t HOCMDR; 440 /* 0x03: Host Target Address */ 441 volatile uint8_t HOTRADDR; 442 /* 0x04: Host Write Length */ 443 volatile uint8_t HOWRLR; 444 /* 0x05: Host Read Length */ 445 volatile uint8_t HORDLR; 446 /* 0x06: Host Write Data */ 447 volatile uint8_t HOWRDR; 448 /* 0x07: Host Read Data */ 449 volatile uint8_t HORDDR; 450 /* 0x08: Host Control 2 */ 451 volatile uint8_t HOCTL2R; 452 /* 0x09: Received Write FCS value */ 453 volatile uint8_t RWFCSV; 454 /* 0x0A: Received Read FCS value */ 455 volatile uint8_t RRFCSV; 456 /* 0x0B: Write FCS Value */ 457 volatile uint8_t WFCSV; 458 /* 0x0C: Read FCS Value */ 459 volatile uint8_t RFCSV; 460 /* 0x0D: Assured Write FCS Value */ 461 volatile uint8_t AWFCSV; 462 /* 0x0E: Pad Control */ 463 volatile uint8_t PADCTLR; 464 }; 465 #endif /* !__ASSEMBLER__ */ 466 467 /** 468 * 469 * (2Fxxh) USB Device Controller (USBDC) Registers 470 * 471 */ 472 #define EP_EXT_REGS_9X 1 473 #define EP_EXT_REGS_BX 2 474 #define EP_EXT_REGS_DX 3 475 476 #ifndef __ASSEMBLER__ 477 478 /* EP0 to EP15 Enumeration */ 479 enum usb_dc_endpoints { 480 EP0, 481 EP1, 482 EP2, 483 EP3, 484 EP4, 485 EP5, 486 EP6, 487 EP7, 488 EP8, 489 EP9, 490 EP10, 491 EP11, 492 EP12, 493 EP13, 494 EP14, 495 EP15, 496 MAX_NUM_ENDPOINTS 497 }; 498 499 union ep_ctrl_reg { 500 volatile uint8_t value; 501 struct { 502 volatile uint8_t enable_bit: 1; 503 volatile uint8_t ready_bit: 1; 504 volatile uint8_t outdata_sequence_bit: 1; 505 volatile uint8_t send_stall_bit: 1; 506 volatile uint8_t iso_enable_bit: 1; 507 volatile uint8_t direction_bit: 1; 508 volatile uint8_t reserved: 2; 509 } __packed fields; 510 } __packed; 511 512 struct it82xx2_usb_ep_regs { 513 union ep_ctrl_reg ep_ctrl; 514 volatile uint8_t ep_status; 515 volatile uint8_t ep_transtype_sts; 516 volatile uint8_t ep_nak_transtype_sts; 517 }; 518 519 /* Reserved EP Extended Registers */ 520 struct ep_ext_regs_7x { 521 /* 0x75 Reserved */ 522 volatile uint8_t ep_ext_ctrl_75; 523 /* 0x76 Reserved */ 524 volatile uint8_t ep_ext_ctrl_76; 525 /* 0x77 Reserved */ 526 volatile uint8_t ep_ext_ctrl_77; 527 /* 0x78 Reserved */ 528 volatile uint8_t ep_ext_ctrl_78; 529 /* 0x79 Reserved */ 530 volatile uint8_t ep_ext_ctrl_79; 531 /* 0x7A Reserved */ 532 volatile uint8_t ep_ext_ctrl_7a; 533 /* 0x7B Reserved */ 534 volatile uint8_t ep_ext_ctrl_7b; 535 /* 0x7C Reserved */ 536 volatile uint8_t ep_ext_ctrl_7c; 537 /* 0x7D Reserved */ 538 volatile uint8_t ep_ext_ctrl_7d; 539 /* 0x7E Reserved */ 540 volatile uint8_t ep_ext_ctrl_7e; 541 /* 0x7F Reserved */ 542 volatile uint8_t ep_ext_ctrl_7f; 543 }; 544 545 /* From 98h to 9Dh, the EP45/67/89/1011/1213/1415 Extended Control Registers 546 * are defined, and their bits definitions are as follows: 547 * 548 * Bit Description 549 * 7 Reserved 550 * 6 EPPOINT5_ISO_ENABLE 551 * 5 EPPOINT5_SEND_STALL 552 * 4 EPPOINT5_OUT_DATA_SEQUENCE 553 * 3 Reserved 554 * 2 EPPOINT4_ISO_ENABLE 555 * 1 EPPOINT4_SEND_STALL 556 * 0 EPPOINT4_OUT_DATA_SEQUENCE 557 * 558 * Apparently, we can tell that the EP4 and EP5 share the same register, and 559 * the EP6 and EP7 share the same one, and the rest EPs are defined in the 560 * same way. 561 */ 562 union epn0n1_extend_ctrl_reg { 563 volatile uint8_t value; 564 struct { 565 volatile uint8_t epn0_outdata_sequence_bit: 1; 566 volatile uint8_t epn0_send_stall_bit: 1; 567 volatile uint8_t epn0_iso_enable_bit: 1; 568 volatile uint8_t reserved0: 1; 569 volatile uint8_t epn1_outdata_sequence_bit: 1; 570 volatile uint8_t epn1_send_stall_bit: 1; 571 volatile uint8_t epn1_iso_enable_bit: 1; 572 volatile uint8_t reserved1: 1; 573 } __packed fields; 574 } __packed; 575 576 struct ep_ext_regs_9x { 577 /* 0x95 Reserved */ 578 volatile uint8_t ep_ext_ctrl_95; 579 /* 0x96 Reserved */ 580 volatile uint8_t ep_ext_ctrl_96; 581 /* 0x97 Reserved */ 582 volatile uint8_t ep_ext_ctrl_97; 583 /* 0x98 ~ 0x9D EP45/67/89/1011/1213/1415 Extended Control Registers */ 584 union epn0n1_extend_ctrl_reg epn0n1_ext_ctrl[6]; 585 /* 0x9E Reserved */ 586 volatile uint8_t ep_ext_ctrl_9e; 587 /* 0x9F Reserved */ 588 volatile uint8_t ep_ext_ctrl_9f; 589 }; 590 591 /* From BXh to BDh are EP FIFO 1-3 Control 0/1 Registers, and their 592 * definitions as as follows: 593 * B8h: EP_FIFO1_CONTROL0_REG 594 * B9h: EP_FIFO1_CONTROL1_REG 595 * BAh: EP_FIFO2_CONTROL0_REG 596 * BBh: EP_FIFO2_CONTROL1_REG 597 * BCh: EP_FIFO3_CONTROL0_REG 598 * BDh: EP_FIFO3_CONTROL1_REG 599 * 600 * For each one, its bits definitions are as follows: 601 * (take EP_FIFO1_CONTROL1_REG as example, which controls from EP8 to EP15) 602 * 603 * Bit Description 604 * 605 * 7 EP15 select FIFO1 as data buffer 606 * 6 EP14 select FIFO1 as data buffer 607 * 5 EP13 select FIFO1 as data buffer 608 * 4 EP12 select FIFO1 as data buffer 609 * 3 EP11 select FIFO1 as data buffer 610 * 2 EP10 select FIFO1 as data buffer 611 * 1 EP9 select FIFO1 as data buffer 612 * 0 EP8 select FIFO1 as data buffer 613 * 614 * 1: Select 615 * 0: Not select 616 */ 617 struct ep_ext_regs_bx { 618 /* 0xB5 Reserved */ 619 volatile uint8_t ep_ext_ctrl_b5; 620 /* 0xB6 Reserved */ 621 volatile uint8_t ep_ext_ctrl_b6; 622 /* 0xB7 Reserved */ 623 volatile uint8_t ep_ext_ctrl_b7; 624 /* 0xB8 ~ 0xBD EP FIFO 1-3 Control 0/1 Registers */ 625 volatile uint8_t ep_fifo_ctrl[6]; 626 /* 0xBE Reserved */ 627 volatile uint8_t ep_ext_ctrl_be; 628 /* 0xBF Reserved */ 629 volatile uint8_t ep_ext_ctrl_bf; 630 }; 631 632 633 /* From D6h to DDh are EP Extended Control Registers, and their 634 * definitions as as follows: 635 * D6h: EP0_EXT_CTRL1 636 * D7h: EP0_EXT_CTRL2 637 * D8h: EP1_EXT_CTRL1 638 * D9h: EP1_EXT_CTRL2 639 * DAh: EP2_EXT_CTRL1 640 * DBh: EP2_EXT_CTRL2 641 * DCh: EP3_EXT_CTRL1 642 * DDh: EP3_EXT_CTRL2 643 * 644 * We classify them into 4 groups which each of them contains Control 1 and 2 645 * according to the EP number as follows: 646 */ 647 union epn_extend_ctrl1_reg { 648 volatile uint8_t value; 649 struct { 650 volatile uint8_t epn0_enable_bit: 1; 651 volatile uint8_t epn0_direction_bit: 1; 652 volatile uint8_t epn3_enable_bit: 1; 653 volatile uint8_t epn3_direction_bit: 1; 654 volatile uint8_t epn6_enable_bit: 1; 655 volatile uint8_t epn6_direction_bit: 1; 656 volatile uint8_t epn9_enable_bit: 1; 657 volatile uint8_t epn9_direction_bit: 1; 658 } __packed fields; 659 } __packed; 660 661 struct epn_ext_ctrl_regs { 662 /* 0xD6/0xD8/0xDA/0xDC EPN Extended Control1 Register */ 663 union epn_extend_ctrl1_reg epn_ext_ctrl1; 664 /* 0xD7/0xD9/0xDB/0xDD EPB Extended Control2 Register */ 665 volatile uint8_t epn_ext_ctrl2; 666 }; 667 668 struct ep_ext_regs_dx { 669 /* 0xD5 Reserved */ 670 volatile uint8_t ep_ext_ctrl_d5; 671 /* 0xD6 ~ 0xDD EPN Extended Control 1/2 Registers */ 672 struct epn_ext_ctrl_regs epn_ext_ctrl[4]; 673 /* 0xDE Reserved */ 674 volatile uint8_t ep_ext_ctrl_de; 675 /* 0xDF Reserved */ 676 volatile uint8_t ep_ext_ctrl_df; 677 }; 678 679 680 /* The USB EPx FIFO Registers Definitions 681 * EP0: 60h ~ 74h 682 * EP1: 80h ~ 94h 683 * EP2: A0h ~ B4h 684 * EP3: C0h ~ D4h (D6h to DDh will be defined as marcos for usage) 685 */ 686 struct it82xx2_usb_ep_fifo_regs { 687 /* 0x60 + ep * 0x20 : EP RX FIFO Data Register */ 688 volatile uint8_t ep_rx_fifo_data; 689 /* 0x61 + ep * 0x20 : EP RX FIFO DMA Count Register */ 690 volatile uint8_t ep_rx_fifo_dma_count; 691 /* 0x62 + ep * 0x20 : EP RX FIFO Data Count MSB */ 692 volatile uint8_t ep_rx_fifo_dcnt_msb; 693 /* 0x63 + ep * 0x20 : EP RX FIFO Data Count LSB */ 694 volatile uint8_t ep_rx_fifo_dcnt_lsb; 695 /* 0x64 + ep * 0x20 : EP RX FIFO Control Register */ 696 volatile uint8_t ep_rx_fifo_ctrl; 697 /* (0x65 ~ 0x6F) + ep * 0x20 */ 698 volatile uint8_t reserved_65_6f_add_20[11]; 699 /* 0x70 + ep * 0x20 : EP TX FIFO Data Register */ 700 volatile uint8_t ep_tx_fifo_data; 701 /* (0x71 ~ 0x73) + ep * 0x20 */ 702 volatile uint8_t reserved_71_73_add_20[3]; 703 /* 0x74 + ep * 0x20 : EP TX FIFO Control Register */ 704 volatile uint8_t ep_tx_fifo_ctrl; 705 /* (0x75 ~ 0x7F) + ep * 0x20 */ 706 union { 707 struct ep_ext_regs_7x ep_res; 708 struct ep_ext_regs_9x ext_4_15; 709 struct ep_ext_regs_bx fifo_ctrl; 710 struct ep_ext_regs_dx ext_0_3; 711 }; 712 713 }; 714 715 /* USB Control registers */ 716 #define USB_IT82XX2_REGS_BASE \ 717 ((struct usb_it82xx2_regs *)DT_REG_ADDR(DT_NODELABEL(usb0))) 718 719 /* Bit definitions of the register Port0/Port1 MISC Control: 0XE4/0xE8 */ 720 #define PULL_DOWN_EN BIT(4) 721 722 struct usb_it82xx2_regs { 723 /* 0x00: Host TX Contrl Register */ 724 volatile uint8_t host_tx_ctrl; 725 /* 0x01: Host TX Transaction Type Register */ 726 volatile uint8_t host_tx_trans_type; 727 /* 0x02: Host TX Line Control Register */ 728 volatile uint8_t host_tx_line_ctrl; 729 /* 0x03: Host TX SOF Enable Register */ 730 volatile uint8_t host_tx_sof_enable; 731 /* 0x04: Host TX Address Register */ 732 volatile uint8_t host_tx_addr; 733 /* 0x05: Host TX EP Number Register */ 734 volatile uint8_t host_tx_endp; 735 /* 0x06: Host Frame Number MSP Register */ 736 volatile uint8_t host_frame_num_msp; 737 /* 0x07: Host Frame Number LSP Register */ 738 volatile uint8_t host_frame_num_lsp; 739 /* 0x08: Host Interrupt Status Register */ 740 volatile uint8_t host_interrupt_status; 741 /* 0x09: Host Interrupt Mask Register */ 742 volatile uint8_t host_interrupt_mask; 743 /* 0x0A: Host RX Status Register */ 744 volatile uint8_t host_rx_status; 745 /* 0x0B: Host RX PID Register */ 746 volatile uint8_t host_rx_pid; 747 /* 0x0C: MISC Control Register */ 748 volatile uint8_t misc_control; 749 /* 0x0D: MISC Status Register */ 750 volatile uint8_t misc_status; 751 /* 0x0E: Host RX Connect State Register */ 752 volatile uint8_t host_rx_connect_state; 753 /* 0x0F: Host SOF Timer MSB Register */ 754 volatile uint8_t host_sof_timer_msb; 755 /* 0x10 ~ 0x1F: Reserved Registers 10h - 1Fh */ 756 volatile uint8_t reserved_10_1f[16]; 757 /* 0x20: Host RX FIFO Data Port Register */ 758 volatile uint8_t host_rx_fifo_data; 759 /* 0x21: Host RX FIFO DMA Input Data Count Register */ 760 volatile uint8_t host_rx_fifo_dma_data_count; 761 /* 0x22: Host TX FIFO Data Count MSB Register */ 762 volatile uint8_t host_rx_fifo_data_count_msb; 763 /* 0x23: Host TX FIFO Data Count LSB Register */ 764 volatile uint8_t host_rx_fifo_data_count_lsb; 765 /* 0x24: Host RX FIFO Data Port Register */ 766 volatile uint8_t host_rx_fifo_control; 767 /* 0x25 ~ 0x2F: Reserved Registers 25h - 2Fh */ 768 volatile uint8_t reserved_25_2f[11]; 769 /* 0x30: Host TX FIFO Data Port Register */ 770 volatile uint8_t host_tx_fifo_data; 771 /* 0x31 ~ 0x3F: Reserved Registers 31h - 3Fh */ 772 volatile uint8_t reserved_31_3f[15]; 773 /* 0x40 ~ 0x4F: Endpoint Registers 40h - 4Fh */ 774 struct it82xx2_usb_ep_regs usb_ep_regs[4]; 775 /* 0x50: Device Controller Control Register */ 776 volatile uint8_t dc_control; 777 /* 0x51: Device Controller LINE Status Register */ 778 volatile uint8_t dc_line_status; 779 /* 0x52: Device Controller Interrupt Status Register */ 780 volatile uint8_t dc_interrupt_status; 781 /* 0x53: Device Controller Interrupt Mask Register */ 782 volatile uint8_t dc_interrupt_mask; 783 /* 0x54: Device Controller Address Register */ 784 volatile uint8_t dc_address; 785 /* 0x55: Device Controller Frame Number MSP Register */ 786 volatile uint8_t dc_frame_num_msp; 787 /* 0x56: Device Controller Frame Number LSP Register */ 788 volatile uint8_t dc_frame_num_lsp; 789 /* 0x57 ~ 0x5F: Reserved Registers 57h - 5Fh */ 790 volatile uint8_t reserved_57_5f[9]; 791 /* 0x60 ~ 0xDF: EP FIFO Registers 60h - DFh */ 792 struct it82xx2_usb_ep_fifo_regs fifo_regs[4]; 793 /* 0xE0: Host/Device Control Register */ 794 volatile uint8_t host_device_control; 795 /* 0xE1 ~ 0xE3: Reserved Registers E1h - E3h */ 796 volatile uint8_t reserved_e1_e3[3]; 797 /* 0xE4: Port0 MISC Control Register */ 798 volatile uint8_t port0_misc_control; 799 /* 0xE5 ~ 0xE7: Reserved Registers E5h - E7h */ 800 volatile uint8_t reserved_e5_e7[3]; 801 /* 0xE8: Port1 MISC Control Register */ 802 volatile uint8_t port1_misc_control; 803 }; 804 #endif /* #ifndef __ASSEMBLER__ */ 805 806 /** 807 * 808 * (37xxh, 38xxh) USBPD Controller 809 * 810 */ 811 #ifndef __ASSEMBLER__ 812 struct usbpd_it8xxx2_regs { 813 /* 0x000~0x003: Reserved1 */ 814 volatile uint8_t Reserved1[4]; 815 /* 0x004: CC General Configuration */ 816 volatile uint8_t CCGCR; 817 /* 0x005: CC Channel Setting */ 818 volatile uint8_t CCCSR; 819 /* 0x006: CC Pad Setting */ 820 volatile uint8_t CCPSR; 821 }; 822 #endif /* !__ASSEMBLER__ */ 823 824 /* USBPD controller register fields */ 825 /* 0x004: CC General Configuration */ 826 #define IT8XXX2_USBPD_DISABLE_CC BIT(7) 827 #define IT8XXX2_USBPD_DISABLE_CC_VOL_DETECTOR BIT(6) 828 #define IT8XXX2_USBPD_CC_SELECT_RP_RESERVED (BIT(3) | BIT(2) | BIT(1)) 829 #define IT8XXX2_USBPD_CC_SELECT_RP_DEF (BIT(3) | BIT(2)) 830 #define IT8XXX2_USBPD_CC_SELECT_RP_1A5 BIT(3) 831 #define IT8XXX2_USBPD_CC_SELECT_RP_3A0 BIT(2) 832 #define IT8XXX2_USBPD_CC1_CC2_SELECTION BIT(0) 833 /* 0x005: CC Channel Setting */ 834 #define IT8XXX2_USBPD_CC2_DISCONNECT BIT(7) 835 #define IT8XXX2_USBPD_CC2_DISCONNECT_5_1K_TO_GND BIT(6) 836 #define IT8XXX2_USBPD_CC1_DISCONNECT BIT(3) 837 #define IT8XXX2_USBPD_CC1_DISCONNECT_5_1K_TO_GND BIT(2) 838 #define IT8XXX2_USBPD_CC1_CC2_RP_RD_SELECT (BIT(1) | BIT(5)) 839 /* 0x006: CC Pad Setting */ 840 #define IT8XXX2_USBPD_DISCONNECT_5_1K_CC2_DB BIT(6) 841 #define IT8XXX2_USBPD_DISCONNECT_POWER_CC2 BIT(5) 842 #define IT8XXX2_USBPD_DISCONNECT_5_1K_CC1_DB BIT(2) 843 #define IT8XXX2_USBPD_DISCONNECT_POWER_CC1 BIT(1) 844 845 846 /** 847 * 848 * (10xxh) Shared Memory Flash Interface Bridge (SMFI) registers 849 * 850 */ 851 #ifndef __ASSEMBLER__ 852 struct smfi_it8xxx2_regs { 853 volatile uint8_t reserved1[59]; 854 /* 0x3B: EC-Indirect memory address 0 */ 855 volatile uint8_t SMFI_ECINDAR0; 856 /* 0x3C: EC-Indirect memory address 1 */ 857 volatile uint8_t SMFI_ECINDAR1; 858 /* 0x3D: EC-Indirect memory address 2 */ 859 volatile uint8_t SMFI_ECINDAR2; 860 /* 0x3E: EC-Indirect memory address 3 */ 861 volatile uint8_t SMFI_ECINDAR3; 862 /* 0x3F: EC-Indirect memory data */ 863 volatile uint8_t SMFI_ECINDDR; 864 /* 0x40: Scratch SRAM 0 address low byte */ 865 volatile uint8_t SMFI_SCAR0L; 866 /* 0x41: Scratch SRAM 0 address middle byte */ 867 volatile uint8_t SMFI_SCAR0M; 868 /* 0x42: Scratch SRAM 0 address high byte */ 869 volatile uint8_t SMFI_SCAR0H; 870 volatile uint8_t reserved1_1[23]; 871 /* 0x5A: Host RAM Window Control */ 872 volatile uint8_t SMFI_HRAMWC; 873 /* 0x5B: Host RAM Window 0 Base Address [11:4] */ 874 volatile uint8_t SMFI_HRAMW0BA; 875 /* 0x5C: Host RAM Window 1 Base Address [11:4] */ 876 volatile uint8_t SMFI_HRAMW1BA; 877 /* 0x5D: Host RAM Window 0 Access Allow Size */ 878 volatile uint8_t SMFI_HRAMW0AAS; 879 /* 0x5E: Host RAM Window 1 Access Allow Size */ 880 volatile uint8_t SMFI_HRAMW1AAS; 881 volatile uint8_t reserved2[67]; 882 /* 0xA2: Flash control 6 */ 883 volatile uint8_t SMFI_FLHCTRL6R; 884 volatile uint8_t reserved3[46]; 885 }; 886 #endif /* !__ASSEMBLER__ */ 887 888 /* SMFI register fields */ 889 /* EC-Indirect read internal flash */ 890 #define EC_INDIRECT_READ_INTERNAL_FLASH BIT(6) 891 /* Enable EC-indirect page program command */ 892 #define IT8XXX2_SMFI_MASK_ECINDPP BIT(3) 893 /* Scratch SRAM 0 address(BIT(19)) */ 894 #define IT8XXX2_SMFI_SC0A19 BIT(7) 895 /* Scratch SRAM enable */ 896 #define IT8XXX2_SMFI_SCAR0H_ENABLE BIT(3) 897 898 /* H2RAM Path Select. 1b: H2RAM through LPC IO cycle. */ 899 #define SMFI_H2RAMPS BIT(4) 900 /* H2RAM Window 1 Enable */ 901 #define SMFI_H2RAMW1E BIT(1) 902 /* H2RAM Window 0 Enable */ 903 #define SMFI_H2RAMW0E BIT(0) 904 905 /* Host RAM Window x Write Protect Enable (All protected) */ 906 #define SMFI_HRAMWXWPE_ALL (BIT(5) | BIT(4)) 907 908 909 /** 910 * 911 * (16xxh) General Purpose I/O Port (GPIO) registers 912 * 913 */ 914 #define GPIO_IT8XXX2_REG_BASE \ 915 ((struct gpio_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gpiogcr))) 916 917 #ifndef __ASSEMBLER__ 918 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1 919 struct gpio_it8xxx2_regs { 920 /* 0x00: General Control */ 921 volatile uint8_t GPIO_GCR; 922 /* 0x01-D0: Reserved1 */ 923 volatile uint8_t reserved1[208]; 924 /* 0xD1: General Control 25 */ 925 volatile uint8_t GPIO_GCR25; 926 /* 0xD2: General Control 26 */ 927 volatile uint8_t GPIO_GCR26; 928 /* 0xD3: General Control 27 */ 929 volatile uint8_t GPIO_GCR27; 930 /* 0xD4: General Control 28 */ 931 volatile uint8_t GPIO_GCR28; 932 /* 0xD5: General Control 31 */ 933 volatile uint8_t GPIO_GCR31; 934 /* 0xD6: General Control 32 */ 935 volatile uint8_t GPIO_GCR32; 936 /* 0xD7: General Control 33 */ 937 volatile uint8_t GPIO_GCR33; 938 /* 0xD8-0xDF: Reserved2 */ 939 volatile uint8_t reserved2[8]; 940 /* 0xE0: General Control 16 */ 941 volatile uint8_t GPIO_GCR16; 942 /* 0xE1: General Control 17 */ 943 volatile uint8_t GPIO_GCR17; 944 /* 0xE2: General Control 18 */ 945 volatile uint8_t GPIO_GCR18; 946 /* 0xE3: Reserved3 */ 947 volatile uint8_t reserved3; 948 /* 0xE4: General Control 19 */ 949 volatile uint8_t GPIO_GCR19; 950 /* 0xE5: General Control 20 */ 951 volatile uint8_t GPIO_GCR20; 952 /* 0xE6: General Control 21 */ 953 volatile uint8_t GPIO_GCR21; 954 /* 0xE7: General Control 22 */ 955 volatile uint8_t GPIO_GCR22; 956 /* 0xE8: General Control 23 */ 957 volatile uint8_t GPIO_GCR23; 958 /* 0xE9: General Control 24 */ 959 volatile uint8_t GPIO_GCR24; 960 /* 0xEA-0xEC: Reserved4 */ 961 volatile uint8_t reserved4[3]; 962 /* 0xED: General Control 30 */ 963 volatile uint8_t GPIO_GCR30; 964 /* 0xEE: General Control 29 */ 965 volatile uint8_t GPIO_GCR29; 966 /* 0xEF: Reserved5 */ 967 volatile uint8_t reserved5; 968 /* 0xF0: General Control 1 */ 969 volatile uint8_t GPIO_GCR1; 970 /* 0xF1: General Control 2 */ 971 volatile uint8_t GPIO_GCR2; 972 /* 0xF2: General Control 3 */ 973 volatile uint8_t GPIO_GCR3; 974 /* 0xF3: General Control 4 */ 975 volatile uint8_t GPIO_GCR4; 976 /* 0xF4: General Control 5 */ 977 volatile uint8_t GPIO_GCR5; 978 /* 0xF5: General Control 6 */ 979 volatile uint8_t GPIO_GCR6; 980 /* 0xF6: General Control 7 */ 981 volatile uint8_t GPIO_GCR7; 982 /* 0xF7: General Control 8 */ 983 volatile uint8_t GPIO_GCR8; 984 /* 0xF8: General Control 9 */ 985 volatile uint8_t GPIO_GCR9; 986 /* 0xF9: General Control 10 */ 987 volatile uint8_t GPIO_GCR10; 988 /* 0xFA: General Control 11 */ 989 volatile uint8_t GPIO_GCR11; 990 /* 0xFB: General Control 12 */ 991 volatile uint8_t GPIO_GCR12; 992 /* 0xFC: General Control 13 */ 993 volatile uint8_t GPIO_GCR13; 994 /* 0xFD: General Control 14 */ 995 volatile uint8_t GPIO_GCR14; 996 /* 0xFE: General Control 15 */ 997 volatile uint8_t GPIO_GCR15; 998 /* 0xFF: Power Good Watch Control */ 999 volatile uint8_t GPIO_PGWCR; 1000 }; 1001 #elif CONFIG_SOC_IT8XXX2_REG_SET_V2 1002 struct gpio_it8xxx2_regs { 1003 /* 0x00: General Control */ 1004 volatile uint8_t GPIO_GCR; 1005 /* 0x01-0x0F: Reserved1 */ 1006 volatile uint8_t reserved1[15]; 1007 /* 0x10: General Control 1 */ 1008 volatile uint8_t GPIO_GCR1; 1009 /* 0x11: General Control 2 */ 1010 volatile uint8_t GPIO_GCR2; 1011 /* 0x12: General Control 3 */ 1012 volatile uint8_t GPIO_GCR3; 1013 /* 0x13: General Control 4 */ 1014 volatile uint8_t GPIO_GCR4; 1015 /* 0x14: General Control 5 */ 1016 volatile uint8_t GPIO_GCR5; 1017 /* 0x15: General Control 6 */ 1018 volatile uint8_t GPIO_GCR6; 1019 /* 0x16: General Control 7 */ 1020 volatile uint8_t GPIO_GCR7; 1021 /* 0x17: General Control 8 */ 1022 volatile uint8_t GPIO_GCR8; 1023 /* 0x18: General Control 9 */ 1024 volatile uint8_t GPIO_GCR9; 1025 /* 0x19: General Control 10 */ 1026 volatile uint8_t GPIO_GCR10; 1027 /* 0x1A: General Control 11 */ 1028 volatile uint8_t GPIO_GCR11; 1029 /* 0x1B: General Control 12 */ 1030 volatile uint8_t GPIO_GCR12; 1031 /* 0x1C: General Control 13 */ 1032 volatile uint8_t GPIO_GCR13; 1033 /* 0x1D: General Control 14 */ 1034 volatile uint8_t GPIO_GCR14; 1035 /* 0x1E: General Control 15 */ 1036 volatile uint8_t GPIO_GCR15; 1037 /* 0x1F: Power Good Watch Control */ 1038 volatile uint8_t GPIO_PGWCR; 1039 /* 0x20: General Control 16 */ 1040 volatile uint8_t GPIO_GCR16; 1041 /* 0x21: General Control 17 */ 1042 volatile uint8_t GPIO_GCR17; 1043 /* 0x22: General Control 18 */ 1044 volatile uint8_t GPIO_GCR18; 1045 /* 0x23: Reserved2 */ 1046 volatile uint8_t reserved2; 1047 /* 0x24: General Control 19 */ 1048 volatile uint8_t GPIO_GCR19; 1049 /* 0x25: Reserved3 */ 1050 volatile uint8_t reserved3; 1051 /* 0x26: General Control 21 */ 1052 volatile uint8_t GPIO_GCR21; 1053 /* 0x27-0x28: Reserved4 */ 1054 volatile uint8_t reserved4[2]; 1055 /* 0x29: General Control 24 */ 1056 volatile uint8_t GPIO_GCR24; 1057 /* 0x2A-0x2C: Reserved5 */ 1058 volatile uint8_t reserved5[3]; 1059 /* 0x2D: General Control 30 */ 1060 volatile uint8_t GPIO_GCR30; 1061 /* 0x2E: General Control 29 */ 1062 volatile uint8_t GPIO_GCR29; 1063 }; 1064 1065 /* GPIO register fields */ 1066 /* 0x16: General Control 7 */ 1067 #define IT8XXX2_GPIO_SMB2PS BIT(7) 1068 #define IT8XXX2_GPIO_SMB3PS BIT(6) 1069 #define IT8XXX2_GPIO_SMB5PS BIT(5) 1070 1071 #endif 1072 #endif /* !__ASSEMBLER__ */ 1073 1074 /* GPIO register fields */ 1075 /* 0x00: General Control */ 1076 #define IT8XXX2_GPIO_LPCRSTEN (BIT(2) | BIT(1)) 1077 #define IT8XXX2_GPIO_GCR_ESPI_RST_D2 0x2 1078 #define IT8XXX2_GPIO_GCR_ESPI_RST_POS 1 1079 #define IT8XXX2_GPIO_GCR_ESPI_RST_EN_MASK (0x3 << IT8XXX2_GPIO_GCR_ESPI_RST_POS) 1080 /* 0xF0: General Control 1 */ 1081 #define IT8XXX2_GPIO_U2CTRL_SIN1_SOUT1_EN BIT(2) 1082 #define IT8XXX2_GPIO_U1CTRL_SIN0_SOUT0_EN BIT(0) 1083 /* 0xE6: General Control 21 */ 1084 #define IT8XXX2_GPIO_GPH1VS BIT(1) 1085 #define IT8XXX2_GPIO_GPH2VS BIT(0) 1086 1087 #define KSIX_KSOX_KBS_GPIO_MODE BIT(7) 1088 #define KSIX_KSOX_GPIO_OUTPUT BIT(6) 1089 #define KSIX_KSOX_GPIO_PULLUP BIT(2) 1090 #define KSIX_KSOX_GPIO_PULLDOWN BIT(1) 1091 1092 #define GPCR_PORT_PIN_MODE_INPUT BIT(7) 1093 #define GPCR_PORT_PIN_MODE_OUTPUT BIT(6) 1094 #define GPCR_PORT_PIN_MODE_PULLUP BIT(2) 1095 #define GPCR_PORT_PIN_MODE_PULLDOWN BIT(1) 1096 1097 /* 1098 * If both PULLUP and PULLDOWN are set to 1b, the corresponding port would be 1099 * configured as tri-state. 1100 */ 1101 #define GPCR_PORT_PIN_MODE_TRISTATE (GPCR_PORT_PIN_MODE_INPUT | \ 1102 GPCR_PORT_PIN_MODE_PULLUP | \ 1103 GPCR_PORT_PIN_MODE_PULLDOWN) 1104 1105 /* --- GPIO --- */ 1106 #define IT8XXX2_GPIO_BASE 0x00F01600 1107 #define IT8XXX2_GPIO2_BASE 0x00F03E00 1108 1109 #define IT8XXX2_GPIO_GCRX(offset) ECREG(IT8XXX2_GPIO_BASE + (offset)) 1110 #define IT8XXX2_GPIO_GCR25_OFFSET 0xd1 1111 #define IT8XXX2_GPIO_GCR26_OFFSET 0xd2 1112 #define IT8XXX2_GPIO_GCR27_OFFSET 0xd3 1113 #define IT8XXX2_GPIO_GCR28_OFFSET 0xd4 1114 #define IT8XXX2_GPIO_GCR31_OFFSET 0xd5 1115 #define IT8XXX2_GPIO_GCR32_OFFSET 0xd6 1116 #define IT8XXX2_GPIO_GCR33_OFFSET 0xd7 1117 #define IT8XXX2_GPIO_GCR19_OFFSET 0xe4 1118 #define IT8XXX2_GPIO_GCR20_OFFSET 0xe5 1119 #define IT8XXX2_GPIO_GCR21_OFFSET 0xe6 1120 #define IT8XXX2_GPIO_GCR22_OFFSET 0xe7 1121 #define IT8XXX2_GPIO_GCR23_OFFSET 0xe8 1122 #define IT8XXX2_GPIO_GCR24_OFFSET 0xe9 1123 #define IT8XXX2_GPIO_GCR30_OFFSET 0xed 1124 #define IT8XXX2_GPIO_GCR29_OFFSET 0xee 1125 1126 /* 1127 * TODO: use pinctrl node instead of following register declarations 1128 * to fix in tcpm\it83xx_pd.h. 1129 */ 1130 #define IT8XXX2_GPIO_GPCRP0 ECREG(IT8XXX2_GPIO2_BASE + 0x18) 1131 #define IT8XXX2_GPIO_GPCRP1 ECREG(IT8XXX2_GPIO2_BASE + 0x19) 1132 1133 1134 /** 1135 * 1136 * (19xxh) Analog to Digital Converter (ADC) registers 1137 * 1138 */ 1139 #ifndef __ASSEMBLER__ 1140 1141 /* Data structure to define ADC channel 13-16 control registers. */ 1142 struct adc_vchs_ctrl_t { 1143 /* 0x60: Voltage Channel Control */ 1144 volatile uint8_t VCHCTL; 1145 /* 0x61: Voltage Channel Data Buffer MSB */ 1146 volatile uint8_t VCHDATM; 1147 /* 0x62: Voltage Channel Data Buffer LSB */ 1148 volatile uint8_t VCHDATL; 1149 }; 1150 1151 struct adc_it8xxx2_regs { 1152 /* 0x00: ADC Status */ 1153 volatile uint8_t ADCSTS; 1154 /* 0x01: ADC Configuration */ 1155 volatile uint8_t ADCCFG; 1156 /* 0x02: ADC Clock Control */ 1157 volatile uint8_t ADCCTL; 1158 /* 0x03: General Control */ 1159 volatile uint8_t ADCGCR; 1160 /* 0x04: Voltage Channel 0 Control */ 1161 volatile uint8_t VCH0CTL; 1162 /* 0x05: Calibration Data Control */ 1163 volatile uint8_t KDCTL; 1164 /* 0x06-0x17: Reserved1 */ 1165 volatile uint8_t reserved1[18]; 1166 /* 0x18: Voltage Channel 0 Data Buffer LSB */ 1167 volatile uint8_t VCH0DATL; 1168 /* 0x19: Voltage Channel 0 Data Buffer MSB */ 1169 volatile uint8_t VCH0DATM; 1170 /* 0x1a-0x43: Reserved2 */ 1171 volatile uint8_t reserved2[42]; 1172 /* 0x44: ADC Data Valid Status */ 1173 volatile uint8_t ADCDVSTS; 1174 /* 0x45-0x54: Reserved2-1 */ 1175 volatile uint8_t reserved2_1[16]; 1176 /* 0x55: ADC Input Voltage Mapping Full-Scale Code Selection 1 */ 1177 volatile uint8_t ADCIVMFSCS1; 1178 /* 0x56: ADC Input Voltage Mapping Full-Scale Code Selection 2 */ 1179 volatile uint8_t ADCIVMFSCS2; 1180 /* 0x57: ADC Input Voltage Mapping Full-Scale Code Selection 3 */ 1181 volatile uint8_t ADCIVMFSCS3; 1182 /* 0x58-0x5f: Reserved3 */ 1183 volatile uint8_t reserved3[8]; 1184 /* 0x60-0x6b: ADC channel 13~16 controller */ 1185 struct adc_vchs_ctrl_t adc_vchs_ctrl[4]; 1186 /* 0x6c: ADC Data Valid Status 2 */ 1187 volatile uint8_t ADCDVSTS2; 1188 /* 0x6d-0xef: Reserved4 */ 1189 volatile uint8_t reserved4[131]; 1190 /* 0xf0: ADC Clock Control Register 1 */ 1191 volatile uint8_t ADCCTL1; 1192 }; 1193 #endif /* !__ASSEMBLER__ */ 1194 1195 /* ADC conversion time select 1 */ 1196 #define IT8XXX2_ADC_ADCCTS1 BIT(7) 1197 /* Analog accuracy initialization */ 1198 #define IT8XXX2_ADC_AINITB BIT(3) 1199 /* ADC conversion time select 0 */ 1200 #define IT8XXX2_ADC_ADCCTS0 BIT(5) 1201 /* ADC module enable */ 1202 #define IT8XXX2_ADC_ADCEN BIT(0) 1203 /* ADC data buffer keep enable */ 1204 #define IT8XXX2_ADC_DBKEN BIT(7) 1205 /* W/C data valid flag */ 1206 #define IT8XXX2_ADC_DATVAL BIT(7) 1207 /* Data valid interrupt of adc */ 1208 #define IT8XXX2_ADC_INTDVEN BIT(5) 1209 /* Voltage channel enable (Channel 4~7 and 13~16) */ 1210 #define IT8XXX2_ADC_VCHEN BIT(4) 1211 /* Automatic hardware calibration enable */ 1212 #define IT8XXX2_ADC_AHCE BIT(7) 1213 /* 0x046, 0x049, 0x04c, 0x06e, 0x071, 0x074: Voltage comparator x control */ 1214 #define IT8XXX2_VCMP_CMPEN BIT(7) 1215 #define IT8XXX2_VCMP_CMPINTEN BIT(6) 1216 #define IT8XXX2_VCMP_GREATER_THRESHOLD BIT(5) 1217 #define IT8XXX2_VCMP_EDGE_TRIGGER BIT(4) 1218 #define IT8XXX2_VCMP_GPIO_ACTIVE_LOW BIT(3) 1219 /* 0x077~0x07c: Voltage comparator x channel select MSB */ 1220 #define IT8XXX2_VCMP_VCMPXCSELM BIT(0) 1221 1222 /** 1223 * 1224 * (1Exxh) Clock and Power Management (ECPM) registers 1225 * 1226 */ 1227 #define IT8XXX2_ECPM_BASE 0x00F01E00 1228 1229 #ifndef __ASSEMBLER__ 1230 enum chip_pll_mode { 1231 CHIP_PLL_DOZE = 0, 1232 CHIP_PLL_SLEEP = 1, 1233 CHIP_PLL_DEEP_DOZE = 3, 1234 }; 1235 #endif 1236 /* 1237 * TODO: use ecpm_it8xxx2_regs instead of following register declarations 1238 * to fix in soc.c. 1239 */ 1240 #define IT8XXX2_ECPM_PLLCTRL ECREG(IT8XXX2_ECPM_BASE + 0x03) 1241 #define IT8XXX2_ECPM_AUTOCG ECREG(IT8XXX2_ECPM_BASE + 0x04) 1242 #define IT8XXX2_ECPM_CGCTRL3R ECREG(IT8XXX2_ECPM_BASE + 0x05) 1243 #define IT8XXX2_ECPM_PLLFREQR ECREG(IT8XXX2_ECPM_BASE + 0x06) 1244 #define IT8XXX2_ECPM_PLLCSS ECREG(IT8XXX2_ECPM_BASE + 0x08) 1245 #define IT8XXX2_ECPM_SCDCR0 ECREG(IT8XXX2_ECPM_BASE + 0x0c) 1246 #define IT8XXX2_ECPM_SCDCR1 ECREG(IT8XXX2_ECPM_BASE + 0x0d) 1247 #define IT8XXX2_ECPM_SCDCR2 ECREG(IT8XXX2_ECPM_BASE + 0x0e) 1248 #define IT8XXX2_ECPM_SCDCR3 ECREG(IT8XXX2_ECPM_BASE + 0x0f) 1249 #define IT8XXX2_ECPM_SCDCR4 ECREG(IT8XXX2_ECPM_BASE + 0x10) 1250 1251 /* 1252 * The count number of the counter for 25 ms register. 1253 * The 25 ms register is calculated by (count number *1.024 kHz). 1254 */ 1255 1256 #define I2C_CLK_LOW_TIMEOUT 255 /* ~=249 ms */ 1257 1258 /** 1259 * 1260 * (1Cxxh) SMBus Interface (SMB) registers 1261 * 1262 */ 1263 #define IT8XXX2_SMB_BASE 0x00F01C00 1264 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1 1265 #define IT8XXX2_SMB_4P7USL ECREG(IT8XXX2_SMB_BASE + 0x00) 1266 #define IT8XXX2_SMB_4P0USL ECREG(IT8XXX2_SMB_BASE + 0x01) 1267 #define IT8XXX2_SMB_300NS ECREG(IT8XXX2_SMB_BASE + 0x02) 1268 #define IT8XXX2_SMB_250NS ECREG(IT8XXX2_SMB_BASE + 0x03) 1269 #define IT8XXX2_SMB_25MS ECREG(IT8XXX2_SMB_BASE + 0x04) 1270 #define IT8XXX2_SMB_45P3USL ECREG(IT8XXX2_SMB_BASE + 0x05) 1271 #define IT8XXX2_SMB_45P3USH ECREG(IT8XXX2_SMB_BASE + 0x06) 1272 #define IT8XXX2_SMB_4P7A4P0H ECREG(IT8XXX2_SMB_BASE + 0x07) 1273 #define IT8XXX2_SMB_SLVISELR ECREG(IT8XXX2_SMB_BASE + 0x08) 1274 #define IT8XXX2_SMB_SCLKTS(ch) ECREG(IT8XXX2_SMB_BASE + 0x09 + ch) 1275 #define IT8XXX2_SMB_MSTFCTRL1 ECREG(IT8XXX2_SMB_BASE + 0x0D) 1276 #define IT8XXX2_SMB_MSTFSTS1 ECREG(IT8XXX2_SMB_BASE + 0x0E) 1277 #define IT8XXX2_SMB_MSTFCTRL2 ECREG(IT8XXX2_SMB_BASE + 0x0F) 1278 #define IT8XXX2_SMB_MSTFSTS2 ECREG(IT8XXX2_SMB_BASE + 0x10) 1279 #define IT8XXX2_SMB_SMB45CHS ECREG(IT8XXX2_SMB_BASE + 0x11) 1280 #define IT8XXX2_SMB_I2CW2RF ECREG(IT8XXX2_SMB_BASE + 0x12) 1281 #define IT8XXX2_SMB_IWRFISTA ECREG(IT8XXX2_SMB_BASE + 0x13) 1282 #define IT8XXX2_SMB_SMB01CHS ECREG(IT8XXX2_SMB_BASE + 0x20) 1283 #define IT8XXX2_SMB_SMB23CHS ECREG(IT8XXX2_SMB_BASE + 0x21) 1284 #define IT8XXX2_SMB_SFFCTL ECREG(IT8XXX2_SMB_BASE + 0x55) 1285 #define IT8XXX2_SMB_HOSTA(base) ECREG(base + 0x00) 1286 #define IT8XXX2_SMB_HOCTL(base) ECREG(base + 0x01) 1287 #define IT8XXX2_SMB_HOCMD(base) ECREG(base + 0x02) 1288 #define IT8XXX2_SMB_TRASLA(base) ECREG(base + 0x03) 1289 #define IT8XXX2_SMB_D0REG(base) ECREG(base + 0x04) 1290 #define IT8XXX2_SMB_D1REG(base) ECREG(base + 0x05) 1291 #define IT8XXX2_SMB_HOBDB(base) ECREG(base + 0x06) 1292 #define IT8XXX2_SMB_PECERC(base) ECREG(base + 0x07) 1293 #define IT8XXX2_SMB_SMBPCTL(base) ECREG(base + 0x0A) 1294 #define IT8XXX2_SMB_HOCTL2(base) ECREG(base + 0x10) 1295 #elif CONFIG_SOC_IT8XXX2_REG_SET_V2 1296 #define IT8XXX2_SMB_SLVISEL ECREG(IT8XXX2_SMB_BASE + 0x08) 1297 #define IT8XXX2_SMB_SMB01CHS ECREG(IT8XXX2_SMB_BASE + 0x09) 1298 #define IT8XXX2_SMB_SMB23CHS ECREG(IT8XXX2_SMB_BASE + 0x0A) 1299 #define IT8XXX2_SMB_SMB45CHS ECREG(IT8XXX2_SMB_BASE + 0x0B) 1300 #define IT8XXX2_SMB_SCLKTS_BRGS ECREG(IT8XXX2_SMB_BASE + 0x80) 1301 #define IT8XXX2_SMB_SCLKTS_BRGM ECREG(IT8XXX2_SMB_BASE + 0x81) 1302 #define IT8XXX2_SMB_CHSBRG ECREG(IT8XXX2_SMB_BASE + 0x82) 1303 #define IT8XXX2_SMB_CHSMOT ECREG(IT8XXX2_SMB_BASE + 0x83) 1304 1305 /* SMBus register fields */ 1306 /* 0x80: SMCLK Timing Setting Register Bridge Slave */ 1307 #define IT8XXX2_SMB_PREDEN BIT(7) 1308 #endif 1309 1310 /** 1311 * Enhanced SMBus/I2C Interface 1312 * Ch_D: 0x00F03680, Ch_E: 0x00F03500, Ch_F: 0x00F03580 1313 * Ch_D: ch = 0x03, Ch_E: ch = 0x00, Ch_F: ch = 0x01 1314 */ 1315 #define IT8XXX2_I2C_DRR(base) ECREG(base + 0x00) 1316 #define IT8XXX2_I2C_PSR(base) ECREG(base + 0x01) 1317 #define IT8XXX2_I2C_HSPR(base) ECREG(base + 0x02) 1318 #define IT8XXX2_I2C_STR(base) ECREG(base + 0x03) 1319 #define IT8XXX2_I2C_DHTR(base) ECREG(base + 0x04) 1320 #define IT8XXX2_I2C_TOR(base) ECREG(base + 0x05) 1321 #define IT8XXX2_I2C_DTR(base) ECREG(base + 0x08) 1322 #define IT8XXX2_I2C_CTR(base) ECREG(base + 0x09) 1323 #define IT8XXX2_I2C_CTR1(base) ECREG(base + 0x0A) 1324 #define IT8XXX2_I2C_BYTE_CNT_H(base) ECREG(base + 0x0B) 1325 #define IT8XXX2_I2C_BYTE_CNT_L(base) ECREG(base + 0x0C) 1326 #define IT8XXX2_I2C_IRQ_ST(base) ECREG(base + 0x0D) 1327 #define IT8XXX2_I2C_IDR(base) ECREG(base + 0x06) 1328 #define IT8XXX2_I2C_TOS(base) ECREG(base + 0x07) 1329 #define IT8XXX2_I2C_SLV_NUM_H(base) ECREG(base + 0x10) 1330 #define IT8XXX2_I2C_SLV_NUM_L(base) ECREG(base + 0x11) 1331 #define IT8XXX2_I2C_STR2(base) ECREG(base + 0x12) 1332 #define IT8XXX2_I2C_NST(base) ECREG(base + 0x13) 1333 #define IT8XXX2_I2C_TO_ARB_ST(base) ECREG(base + 0x18) 1334 #define IT8XXX2_I2C_ERR_ST(base) ECREG(base + 0x19) 1335 #define IT8XXX2_I2C_FST(base) ECREG(base + 0x1B) 1336 #define IT8XXX2_I2C_EM(base) ECREG(base + 0x1C) 1337 #define IT8XXX2_I2C_MODE_SEL(base) ECREG(base + 0x1D) 1338 #define IT8XXX2_I2C_IDR2(base) ECREG(base + 0x1F) 1339 #define IT8XXX2_I2C_CTR2(base) ECREG(base + 0x20) 1340 #define IT8XXX2_I2C_RAMHA(base) ECREG(base + 0x23) 1341 #define IT8XXX2_I2C_RAMLA(base) ECREG(base + 0x24) 1342 #define IT8XXX2_I2C_RAMHA2(base) ECREG(base + 0x2C) 1343 #define IT8XXX2_I2C_RAMLA2(base) ECREG(base + 0x2D) 1344 #define IT8XXX2_I2C_CMD_ADDH(base) ECREG(base + 0x25) 1345 #define IT8XXX2_I2C_CMD_ADDL(base) ECREG(base + 0x26) 1346 #define IT8XXX2_I2C_RAMH2A(base) ECREG(base + 0x50) 1347 #define IT8XXX2_I2C_CMD_ADDH2(base) ECREG(base + 0x52) 1348 1349 /* SMBus/I2C register fields */ 1350 /* 0x09-0xB: SMCLK Timing Setting */ 1351 #define IT8XXX2_SMB_SMCLKS_1M 4 1352 #define IT8XXX2_SMB_SMCLKS_400K 3 1353 #define IT8XXX2_SMB_SMCLKS_100K 2 1354 #define IT8XXX2_SMB_SMCLKS_50K 1 1355 1356 /* 0x0E: SMBus FIFO Status 1 */ 1357 #define IT8XXX2_SMB_FIFO1_EMPTY BIT(7) 1358 #define IT8XXX2_SMB_FIFO1_FULL BIT(6) 1359 /* 0x0D: SMBus FIFO Control 1 */ 1360 /* 0x0F: SMBus FIFO Control 2 */ 1361 #define IT8XXX2_SMB_BLKDS BIT(4) 1362 #define IT8XXX2_SMB_FFEN BIT(3) 1363 #define IT8XXX2_SMB_FFCHSEL2_B 0 1364 #define IT8XXX2_SMB_FFCHSEL2_C BIT(0) 1365 /* 0x10: SMBus FIFO Status 2 */ 1366 #define IT8XXX2_SMB_FIFO2_EMPTY BIT(7) 1367 #define IT8XXX2_SMB_FIFO2_FULL BIT(6) 1368 /* 0x12: I2C Wr To Rd FIFO */ 1369 #define IT8XXX2_SMB_MAIF BIT(7) 1370 #define IT8XXX2_SMB_MBCIF BIT(6) 1371 #define IT8XXX2_SMB_MCIFI BIT(2) 1372 #define IT8XXX2_SMB_MBIFI BIT(1) 1373 #define IT8XXX2_SMB_MAIFI BIT(0) 1374 /* 0x13: I2C Wr To Rd FIFO Interrupt Status */ 1375 #define IT8XXX2_SMB_MCIFID BIT(2) 1376 #define IT8XXX2_SMB_MAIFID BIT(0) 1377 /* 0x41 0x81 0xC1: Host Control */ 1378 #define IT8XXX2_SMB_SRT BIT(6) 1379 #define IT8XXX2_SMB_LABY BIT(5) 1380 #define IT8XXX2_SMB_SMCD_EXTND BIT(4) | BIT(3) | BIT(2) 1381 #define IT8XXX2_SMB_KILL BIT(1) 1382 #define IT8XXX2_SMB_INTREN BIT(0) 1383 /* 0x43 0x83 0xC3: Transmit Slave Address */ 1384 #define IT8XXX2_SMB_DIR BIT(0) 1385 /* 0x4A 0x8A 0xCA: SMBus Pin Control */ 1386 #define IT8XXX2_SMB_SMBDCS BIT(1) 1387 #define IT8XXX2_SMB_SMBCS BIT(0) 1388 /* 0x50 0x90 0xD0: Host Control 2 */ 1389 #define IT8XXX2_SMB_SMD_TO_EN BIT(4) 1390 #define IT8XXX2_SMB_I2C_SW_EN BIT(3) 1391 #define IT8XXX2_SMB_I2C_SW_WAIT BIT(2) 1392 #define IT8XXX2_SMB_I2C_EN BIT(1) 1393 #define IT8XXX2_SMB_SMHEN BIT(0) 1394 /* 0x55: Slave A FIFO Control */ 1395 #define IT8XXX2_SMB_HSAPE BIT(1) 1396 /* 0x03: Status Register */ 1397 #define IT8XXX2_I2C_BYTE_DONE BIT(7) 1398 #define IT8XXX2_I2C_RW BIT(2) 1399 #define IT8XXX2_I2C_INT_PEND BIT(1) 1400 /* 0x04: Data Hold Time */ 1401 #define IT8XXX2_I2C_SOFT_RST BIT(7) 1402 /* 0x07: Time Out Status */ 1403 #define IT8XXX2_I2C_CLK_STRETCH BIT(7) 1404 #define IT8XXX2_I2C_SCL_IN BIT(2) 1405 #define IT8XXX2_I2C_SDA_IN BIT(0) 1406 /* 0x09: Control Register */ 1407 #define IT8XXX2_I2C_INT_EN BIT(6) 1408 #define IT8XXX2_I2C_ACK BIT(3) 1409 #define IT8XXX2_I2C_HALT BIT(0) 1410 /* 0x0A: Control 1 */ 1411 #define IT8XXX2_I2C_COMQ_EN BIT(7) 1412 #define IT8XXX2_I2C_MDL_EN BIT(1) 1413 /* 0x0C: Byte count */ 1414 #define IT8XXX2_I2C_DMA_ADDR_RELOAD BIT(5) 1415 #define IT8XXX2_I2C_BYTE_CNT_ENABLE BIT(3) 1416 /* 0x0D: Interrupt Status */ 1417 #define IT8XXX2_I2C_CNT_HOLD BIT(4) 1418 #define IT8XXX2_I2C_IDW_CLR BIT(3) 1419 #define IT8XXX2_I2C_IDR_CLR BIT(2) 1420 #define IT8XXX2_I2C_SLVDATAFLG BIT(1) 1421 #define IT8XXX2_I2C_P_CLR BIT(0) 1422 /* 0x13: Nack Status */ 1423 #define IT8XXX2_I2C_NST_CNS BIT(7) 1424 #define IT8XXX2_I2C_NST_ID_NACK BIT(3) 1425 /* 0x18: Timeout and Arbiter Status */ 1426 #define IT8XXX2_I2C_SCL_TIMEOUT_EN BIT(7) 1427 #define IT8XXX2_I2C_SDA_TIMEOUT_EN BIT(6) 1428 /* 0x19: Error Status */ 1429 #define IT8XXX2_I2C_ERR_ST_DEV1_EIRQ BIT(0) 1430 /* 0x1B: Finish Status */ 1431 #define IT8XXX2_I2C_FST_DEV1_IRQ BIT(4) 1432 /* 0x1C: Error Mask */ 1433 #define IT8XXX2_I2C_EM_DEV1_IRQ BIT(4) 1434 1435 /* 1436 * TODO: use gctrl_it8xxx2_regs instead of following register declarations 1437 * to fix in cros_flash_it8xxx2.c, cros_shi_it8xxx2.c and tcpm\it8xxx2.c. 1438 */ 1439 /* --- General Control (GCTRL) --- */ 1440 #define IT83XX_GCTRL_BASE 0x00F02000 1441 1442 #define IT83XX_GCTRL_CHIPID1 ECREG(IT83XX_GCTRL_BASE + 0x85) 1443 #define IT83XX_GCTRL_CHIPID2 ECREG(IT83XX_GCTRL_BASE + 0x86) 1444 #define IT83XX_GCTRL_CHIPVER ECREG(IT83XX_GCTRL_BASE + 0x02) 1445 #define IT83XX_GCTRL_MCCR3 ECREG(IT83XX_GCTRL_BASE + 0x20) 1446 #define IT83XX_GCTRL_SPISLVPFE BIT(6) 1447 #define IT83XX_GCTRL_EWPR0PFH(i) ECREG(IT83XX_GCTRL_BASE + 0x60 + i) 1448 #define IT83XX_GCTRL_EWPR0PFD(i) ECREG(IT83XX_GCTRL_BASE + 0xA0 + i) 1449 #define IT83XX_GCTRL_EWPR0PFEC(i) ECREG(IT83XX_GCTRL_BASE + 0xC0 + i) 1450 1451 /* 1452 * TODO: use spisc_it8xxx2_regs instead of following register declarations 1453 * to fix in cros_shi_it8xxx2.c. 1454 */ 1455 /* Serial Peripheral Interface (SPI) */ 1456 #define IT83XX_SPI_BASE 0x00F03A00 1457 1458 #define IT83XX_SPI_SPISGCR ECREG(IT83XX_SPI_BASE + 0x00) 1459 #define IT83XX_SPI_SPISCEN BIT(0) 1460 #define IT83XX_SPI_TXRXFAR ECREG(IT83XX_SPI_BASE + 0x01) 1461 #define IT83XX_SPI_CPURXF2A BIT(4) 1462 #define IT83XX_SPI_CPURXF1A BIT(3) 1463 #define IT83XX_SPI_CPUTFA BIT(1) 1464 #define IT83XX_SPI_TXFCR ECREG(IT83XX_SPI_BASE + 0x02) 1465 #define IT83XX_SPI_TXFCMR BIT(2) 1466 #define IT83XX_SPI_TXFR BIT(1) 1467 #define IT83XX_SPI_TXFS BIT(0) 1468 #define IT83XX_SPI_GCR2 ECREG(IT83XX_SPI_BASE + 0x03) 1469 #define IT83XX_SPI_RXF2OC BIT(4) 1470 #define IT83XX_SPI_RXF1OC BIT(3) 1471 #define IT83XX_SPI_RXFAR BIT(0) 1472 #define IT83XX_SPI_IMR ECREG(IT83XX_SPI_BASE + 0x04) 1473 #define IT83XX_SPI_RX_FIFO_FULL BIT(7) 1474 #define IT83XX_SPI_RX_REACH BIT(5) 1475 #define IT83XX_SPI_EDIM BIT(2) 1476 #define IT83XX_SPI_ISR ECREG(IT83XX_SPI_BASE + 0x05) 1477 #define IT83XX_SPI_TXFSR ECREG(IT83XX_SPI_BASE + 0x06) 1478 #define IT83XX_SPI_ENDDETECTINT BIT(2) 1479 #define IT83XX_SPI_RXFSR ECREG(IT83XX_SPI_BASE + 0x07) 1480 #define IT83XX_SPI_RXFFSM (BIT(4) | BIT(3)) 1481 #define IT83XX_SPI_RXF2FS BIT(2) 1482 #define IT83XX_SPI_RXF1FS BIT(1) 1483 #ifdef CHIP_VARIANT_IT83202BX 1484 #define IT83XX_SPI_SPISRDR ECREG(IT83XX_SPI_BASE + 0x08) 1485 #else 1486 #define IT83XX_SPI_SPISRDR ECREG(IT83XX_SPI_BASE + 0x0b) 1487 #endif 1488 #define IT83XX_SPI_CPUWTFDB0 ECREG_u32(IT83XX_SPI_BASE + 0x08) 1489 #define IT83XX_SPI_FCR ECREG(IT83XX_SPI_BASE + 0x09) 1490 #define IT83XX_SPI_SPISRTXF BIT(2) 1491 #define IT83XX_SPI_RXFR BIT(1) 1492 #define IT83XX_SPI_RXFCMR BIT(0) 1493 #define IT83XX_SPI_RXFRDRB0 ECREG_u32(IT83XX_SPI_BASE + 0x0C) 1494 #define IT83XX_SPI_FTCB0R ECREG(IT83XX_SPI_BASE + 0x18) 1495 #define IT83XX_SPI_FTCB1R ECREG(IT83XX_SPI_BASE + 0x19) 1496 #define IT83XX_SPI_TCCB0 ECREG(IT83XX_SPI_BASE + 0x1A) 1497 #define IT83XX_SPI_TCCB1 ECREG(IT83XX_SPI_BASE + 0x1B) 1498 #define IT83XX_SPI_HPR2 ECREG(IT83XX_SPI_BASE + 0x1E) 1499 #define IT83XX_SPI_EMMCBMR ECREG(IT83XX_SPI_BASE + 0x21) 1500 #define IT83XX_SPI_EMMCABM BIT(1) /* eMMC Alternative Boot Mode */ 1501 #define IT83XX_SPI_RX_VLISMR ECREG(IT83XX_SPI_BASE + 0x26) 1502 #define IT83XX_SPI_RVLIM BIT(0) 1503 #define IT83XX_SPI_RX_VLISR ECREG(IT83XX_SPI_BASE + 0x27) 1504 #define IT83XX_SPI_RVLI BIT(0) 1505 1506 /** 1507 * 1508 * (20xxh) General Control (GCTRL) registers 1509 * 1510 */ 1511 #define GCTRL_IT8XXX2_REGS_BASE \ 1512 ((struct gctrl_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gctrl))) 1513 1514 #ifndef __ASSEMBLER__ 1515 struct gctrl_it8xxx2_regs { 1516 /* 0x00-0x01: Reserved_00_01 */ 1517 volatile uint8_t reserved_00_01[2]; 1518 /* 0x02: Chip Version */ 1519 volatile uint8_t GCTRL_ECHIPVER; 1520 /* 0x03-0x05: Reserved_03_05 */ 1521 volatile uint8_t reserved_03_05[3]; 1522 /* 0x06: Reset Status */ 1523 volatile uint8_t GCTRL_RSTS; 1524 /* 0x07-0x09: Reserved_07_09 */ 1525 volatile uint8_t reserved_07_09[3]; 1526 /* 0x0A: Base Address Select */ 1527 volatile uint8_t GCTRL_BADRSEL; 1528 /* 0x0B: Wait Next Clock Rising */ 1529 volatile uint8_t GCTRL_WNCKR; 1530 /* 0x0C: reserved_0c */ 1531 volatile uint8_t reserved_0c; 1532 /* 0x0D: Special Control 1 */ 1533 volatile uint8_t GCTRL_SPCTRL1; 1534 /* 0x0E-0x0F: reserved_0e_0f */ 1535 volatile uint8_t reserved_0e_0f[2]; 1536 /* 0x10: Reset Control DMM */ 1537 volatile uint8_t GCTRL_RSTDMMC; 1538 /* 0x11: Reset Control 4 */ 1539 volatile uint8_t GCTRL_RSTC4; 1540 /* 0x12-0x1B: reserved_12_1b */ 1541 volatile uint8_t reserved_12_1b[10]; 1542 /* 0x1C: Special Control 4 */ 1543 volatile uint8_t GCTRL_SPCTRL4; 1544 /* 0x1D-0x1F: reserved_1d_1f */ 1545 volatile uint8_t reserved_1d_1f[3]; 1546 /* 0x20: Memory Controller Configuration 3 */ 1547 volatile uint8_t GCTRL_MCCR3; 1548 /* 0x21: Reset Control 5 */ 1549 volatile uint8_t GCTRL_RSTC5; 1550 /* 0x22-0x2F: reserved_22_2f */ 1551 volatile uint8_t reserved_22_2f[14]; 1552 /* 0x30: Memory Controller Configuration */ 1553 volatile uint8_t GCTRL_MCCR; 1554 /* 0x31: Externel ILM/DLM Size */ 1555 volatile uint8_t GCTRL_EIDSR; 1556 /* 0x32: Reserved_32 */ 1557 volatile uint8_t reserved_32; 1558 /* 0x33: Pin Multi-function Enable 2 */ 1559 volatile uint8_t gctrl_pmer2; 1560 /* 0x34-0x36: Reserved_34_36 */ 1561 volatile uint8_t reserved_34_36[3]; 1562 /* 0x37: Eflash Protect Lock */ 1563 volatile uint8_t GCTRL_EPLR; 1564 /* 0x38-0x40: Reserved_38_40 */ 1565 volatile uint8_t reserved_38_40[9]; 1566 /* 0x41: Interrupt Vector Table Base Address */ 1567 volatile uint8_t GCTRL_IVTBAR; 1568 /* 0x42-0x43: Reserved_42_43 */ 1569 volatile uint8_t reserved_42_43[2]; 1570 /* 0x44: Memory Controller Configuration 2 */ 1571 volatile uint8_t GCTRL_MCCR2; 1572 /* 0x45: Reserved_45 */ 1573 volatile uint8_t reserved_45; 1574 /* 0x46: Pin Multi-function Enable 3 */ 1575 volatile uint8_t GCTRL_PMER3; 1576 /* 0x47-0x4A: reserved_47_4a */ 1577 volatile uint8_t reserved_47_4a[4]; 1578 /* 0x4B: ETWD and UART Control */ 1579 volatile uint8_t GCTRL_ETWDUARTCR; 1580 /* 0x4C: Wakeup MCU Control */ 1581 volatile uint8_t GCTRL_WMCR; 1582 /* 0x4D-0x4F: reserved_4d_4f */ 1583 volatile uint8_t reserved_4d_4f[3]; 1584 /* 0x50: Port 80h/81h Status Register */ 1585 volatile uint8_t GCTRL_P80H81HSR; 1586 /* 0x51: Port 80h Data Register */ 1587 volatile uint8_t GCTRL_P80HDR; 1588 /* 0x52: Port 81h Data Register */ 1589 volatile uint8_t GCTRL_P81HDR; 1590 /* 0x53: H2RAM Offset Register */ 1591 volatile uint8_t GCTRL_H2ROFSR; 1592 /* 0x54-0x5C: reserved_54_5c */ 1593 volatile uint8_t reserved_54_5c[9]; 1594 /* 0x5D: RISCV ILM Configuration 0 */ 1595 volatile uint8_t GCTRL_RVILMCR0; 1596 /* 0x5E-0x84: reserved_5e_84 */ 1597 volatile uint8_t reserved_5e_84[39]; 1598 /* 0x85: Chip ID Byte 1 */ 1599 volatile uint8_t GCTRL_ECHIPID1; 1600 /* 0x86: Chip ID Byte 2 */ 1601 volatile uint8_t GCTRL_ECHIPID2; 1602 /* 0x87: Chip ID Byte 3 */ 1603 volatile uint8_t GCTRL_ECHIPID3; 1604 }; 1605 #endif /* !__ASSEMBLER__ */ 1606 1607 /* GCTRL register fields */ 1608 /* 0x06: Reset Status */ 1609 #define IT8XXX2_GCTRL_LRS (BIT(1) | BIT(0)) 1610 #define IT8XXX2_GCTRL_IWDTR BIT(1) 1611 /* 0x10: Reset Control DMM */ 1612 #define IT8XXX2_GCTRL_UART1SD BIT(3) 1613 #define IT8XXX2_GCTRL_UART2SD BIT(2) 1614 /* 0x11: Reset Control 4 */ 1615 #define IT8XXX2_GCTRL_RPECI BIT(4) 1616 #define IT8XXX2_GCTRL_RUART2 BIT(2) 1617 #define IT8XXX2_GCTRL_RUART1 BIT(1) 1618 /* 0x1C: Special Control 4 */ 1619 #define IT8XXX2_GCTRL_LRSIWR BIT(2) 1620 #define IT8XXX2_GCTRL_LRSIPWRSWTR BIT(1) 1621 #define IT8XXX2_GCTRL_LRSIPGWR BIT(0) 1622 /* 0x20: Memory Controller Configuration 3 */ 1623 #define IT8XXX2_GCTRL_SPISLVPFE BIT(6) 1624 /* 0x30: Memory Controller Configuration */ 1625 #define IT8XXX2_GCTRL_ICACHE_RESET BIT(4) 1626 /* 0x37: Eflash Protect Lock */ 1627 #define IT8XXX2_GCTRL_EPLR_ENABLE BIT(0) 1628 /* 0x46: Pin Multi-function Enable 3 */ 1629 #define IT8XXX2_GCTRL_SMB3PSEL BIT(6) 1630 /* 0x4B: ETWD and UART Control */ 1631 #define IT8XXX2_GCTRL_ETWD_HW_RST_EN BIT(0) 1632 /* 0x5D: RISCV ILM Configuration 0 */ 1633 #define IT8XXX2_GCTRL_ILM0_ENABLE BIT(0) 1634 /* Accept Port 80h Cycle */ 1635 #define IT8XXX2_GCTRL_ACP80 BIT(6) 1636 /* USB Debug Enable */ 1637 #define IT8XXX2_GCTRL_MCCR_USB_EN BIT(7) 1638 /* USB Pad Power-On Enable */ 1639 #define IT8XXX2_GCTRL_PMER2_USB_PAD_EN BIT(7) 1640 1641 /* 1642 * VCC Detector Option. 1643 * bit[7-6] = 1: The VCC power status is treated as power-on. 1644 * The VCC supply of eSPI and related functions (EC2I, KBC, PMC and 1645 * PECI). It means VCC should be logic high before using these 1646 * functions, or firmware treats VCC logic high. 1647 */ 1648 #define IT8XXX2_GCTRL_VCCDO_MASK (BIT(6) | BIT(7)) 1649 #define IT8XXX2_GCTRL_VCCDO_VCC_ON BIT(6) 1650 /* 1651 * bit[3] = 0: The reset source of PNPCFG is RSTPNP bit in RSTCH 1652 * register and WRST#. 1653 */ 1654 #define IT8XXX2_GCTRL_HGRST BIT(3) 1655 /* bit[2] = 1: Enable global reset. */ 1656 #define IT8XXX2_GCTRL_GRST BIT(2) 1657 1658 /** 1659 * 1660 * (22xxh) Battery-backed SRAM (BRAM) registers 1661 * 1662 */ 1663 #ifndef __ASSEMBLER__ 1664 /* Battery backed RAM indices. */ 1665 #define BRAM_MAGIC_FIELD_OFFSET 0xbc 1666 enum bram_indices { 1667 1668 /* This field is used to indicate BRAM is valid or not. */ 1669 BRAM_IDX_VALID_FLAGS0 = BRAM_MAGIC_FIELD_OFFSET, 1670 BRAM_IDX_VALID_FLAGS1, 1671 BRAM_IDX_VALID_FLAGS2, 1672 BRAM_IDX_VALID_FLAGS3 1673 }; 1674 #endif /* !__ASSEMBLER__ */ 1675 1676 #ifndef __ASSEMBLER__ 1677 /* 1678 * EC2I bridge registers 1679 */ 1680 struct ec2i_regs { 1681 /* 0x00: Indirect Host I/O Address Register */ 1682 volatile uint8_t IHIOA; 1683 /* 0x01: Indirect Host Data Register */ 1684 volatile uint8_t IHD; 1685 /* 0x02: Lock Super I/O Host Access Register */ 1686 volatile uint8_t LSIOHA; 1687 /* 0x03: Super I/O Access Lock Violation Register */ 1688 volatile uint8_t SIOLV; 1689 /* 0x04: EC to I-Bus Modules Access Enable Register */ 1690 volatile uint8_t IBMAE; 1691 /* 0x05: I-Bus Control Register */ 1692 volatile uint8_t IBCTL; 1693 }; 1694 1695 /* Index list of the host interface registers of PNPCFG */ 1696 enum host_pnpcfg_index { 1697 /* Logical Device Number */ 1698 HOST_INDEX_LDN = 0x07, 1699 /* Chip ID Byte 1 */ 1700 HOST_INDEX_CHIPID1 = 0x20, 1701 /* Chip ID Byte 2 */ 1702 HOST_INDEX_CHIPID2 = 0x21, 1703 /* Chip Version */ 1704 HOST_INDEX_CHIPVER = 0x22, 1705 /* Super I/O Control */ 1706 HOST_INDEX_SIOCTRL = 0x23, 1707 /* Super I/O IRQ Configuration */ 1708 HOST_INDEX_SIOIRQ = 0x25, 1709 /* Super I/O General Purpose */ 1710 HOST_INDEX_SIOGP = 0x26, 1711 /* Super I/O Power Mode */ 1712 HOST_INDEX_SIOPWR = 0x2D, 1713 /* Depth 2 I/O Address */ 1714 HOST_INDEX_D2ADR = 0x2E, 1715 /* Depth 2 I/O Data */ 1716 HOST_INDEX_D2DAT = 0x2F, 1717 /* Logical Device Activate Register */ 1718 HOST_INDEX_LDA = 0x30, 1719 /* I/O Port Base Address Bits [15:8] for Descriptor 0 */ 1720 HOST_INDEX_IOBAD0_MSB = 0x60, 1721 /* I/O Port Base Address Bits [7:0] for Descriptor 0 */ 1722 HOST_INDEX_IOBAD0_LSB = 0x61, 1723 /* I/O Port Base Address Bits [15:8] for Descriptor 1 */ 1724 HOST_INDEX_IOBAD1_MSB = 0x62, 1725 /* I/O Port Base Address Bits [7:0] for Descriptor 1 */ 1726 HOST_INDEX_IOBAD1_LSB = 0x63, 1727 /* Interrupt Request Number and Wake-Up on IRQ Enabled */ 1728 HOST_INDEX_IRQNUMX = 0x70, 1729 /* Interrupt Request Type Select */ 1730 HOST_INDEX_IRQTP = 0x71, 1731 /* DMA Channel Select 0 */ 1732 HOST_INDEX_DMAS0 = 0x74, 1733 /* DMA Channel Select 1 */ 1734 HOST_INDEX_DMAS1 = 0x75, 1735 /* Device Specific Logical Device Configuration 1 to 10 */ 1736 HOST_INDEX_DSLDC1 = 0xF0, 1737 HOST_INDEX_DSLDC2 = 0xF1, 1738 HOST_INDEX_DSLDC3 = 0xF2, 1739 HOST_INDEX_DSLDC4 = 0xF3, 1740 HOST_INDEX_DSLDC5 = 0xF4, 1741 HOST_INDEX_DSLDC6 = 0xF5, 1742 HOST_INDEX_DSLDC7 = 0xF6, 1743 HOST_INDEX_DSLDC8 = 0xF7, 1744 HOST_INDEX_DSLDC9 = 0xF8, 1745 HOST_INDEX_DSLDC10 = 0xF9, 1746 }; 1747 1748 /* List of logical device number (LDN) assignments */ 1749 enum logical_device_number { 1750 /* Serial Port 1 */ 1751 LDN_UART1 = 0x01, 1752 /* Serial Port 2 */ 1753 LDN_UART2 = 0x02, 1754 /* System Wake-Up Control */ 1755 LDN_SWUC = 0x04, 1756 /* KBC/Mouse Interface */ 1757 LDN_KBC_MOUSE = 0x05, 1758 /* KBC/Keyboard Interface */ 1759 LDN_KBC_KEYBOARD = 0x06, 1760 /* Consumer IR */ 1761 LDN_CIR = 0x0A, 1762 /* Shared Memory/Flash Interface */ 1763 LDN_SMFI = 0x0F, 1764 /* RTC-like Timer */ 1765 LDN_RTCT = 0x10, 1766 /* Power Management I/F Channel 1 */ 1767 LDN_PMC1 = 0x11, 1768 /* Power Management I/F Channel 2 */ 1769 LDN_PMC2 = 0x12, 1770 /* Serial Peripheral Interface */ 1771 LDN_SSPI = 0x13, 1772 /* Platform Environment Control Interface */ 1773 LDN_PECI = 0x14, 1774 /* Power Management I/F Channel 3 */ 1775 LDN_PMC3 = 0x17, 1776 /* Power Management I/F Channel 4 */ 1777 LDN_PMC4 = 0x18, 1778 /* Power Management I/F Channel 5 */ 1779 LDN_PMC5 = 0x19, 1780 }; 1781 1782 /* Structure for initializing PNPCFG via ec2i. */ 1783 struct ec2i_t { 1784 /* index port */ 1785 enum host_pnpcfg_index index_port; 1786 /* data port */ 1787 uint8_t data_port; 1788 }; 1789 1790 /* EC2I access index/data port */ 1791 enum ec2i_access { 1792 /* index port */ 1793 EC2I_ACCESS_INDEX = 0, 1794 /* data port */ 1795 EC2I_ACCESS_DATA = 1, 1796 }; 1797 1798 /* EC to I-Bus Access Enabled */ 1799 #define EC2I_IBCTL_CSAE BIT(0) 1800 /* EC Read from I-Bus */ 1801 #define EC2I_IBCTL_CRIB BIT(1) 1802 /* EC Write to I-Bus */ 1803 #define EC2I_IBCTL_CWIB BIT(2) 1804 #define EC2I_IBCTL_CRWIB (EC2I_IBCTL_CRIB | EC2I_IBCTL_CWIB) 1805 1806 /* PNPCFG Register EC Access Enable */ 1807 #define EC2I_IBMAE_CFGAE BIT(0) 1808 1809 /* 1810 * KBC registers 1811 */ 1812 struct kbc_regs { 1813 /* 0x00: KBC Host Interface Control Register */ 1814 volatile uint8_t KBHICR; 1815 /* 0x01: Reserved1 */ 1816 volatile uint8_t reserved1; 1817 /* 0x02: KBC Interrupt Control Register */ 1818 volatile uint8_t KBIRQR; 1819 /* 0x03: Reserved2 */ 1820 volatile uint8_t reserved2; 1821 /* 0x04: KBC Host Interface Keyboard/Mouse Status Register */ 1822 volatile uint8_t KBHISR; 1823 /* 0x05: Reserved3 */ 1824 volatile uint8_t reserved3; 1825 /* 0x06: KBC Host Interface Keyboard Data Output Register */ 1826 volatile uint8_t KBHIKDOR; 1827 /* 0x07: Reserved4 */ 1828 volatile uint8_t reserved4; 1829 /* 0x08: KBC Host Interface Mouse Data Output Register */ 1830 volatile uint8_t KBHIMDOR; 1831 /* 0x09: Reserved5 */ 1832 volatile uint8_t reserved5; 1833 /* 0x0a: KBC Host Interface Keyboard/Mouse Data Input Register */ 1834 volatile uint8_t KBHIDIR; 1835 }; 1836 1837 /* Output Buffer Full */ 1838 #define KBC_KBHISR_OBF BIT(0) 1839 /* Input Buffer Full */ 1840 #define KBC_KBHISR_IBF BIT(1) 1841 /* A2 Address (A2) */ 1842 #define KBC_KBHISR_A2_ADDR BIT(3) 1843 #define KBC_KBHISR_STS_MASK (KBC_KBHISR_OBF | KBC_KBHISR_IBF \ 1844 | KBC_KBHISR_A2_ADDR) 1845 1846 /* Clear Output Buffer Full */ 1847 #define KBC_KBHICR_COBF BIT(6) 1848 /* IBF/OBF Clear Mode Enable */ 1849 #define KBC_KBHICR_IBFOBFCME BIT(5) 1850 /* Input Buffer Full CPU Interrupt Enable */ 1851 #define KBC_KBHICR_IBFCIE BIT(3) 1852 /* Output Buffer Empty CPU Interrupt Enable */ 1853 #define KBC_KBHICR_OBECIE BIT(2) 1854 /* Output Buffer Full Mouse Interrupt Enable */ 1855 #define KBC_KBHICR_OBFMIE BIT(1) 1856 /* Output Buffer Full Keyboard Interrupt Enable */ 1857 #define KBC_KBHICR_OBFKIE BIT(0) 1858 1859 /* 1860 * PMC registers 1861 */ 1862 struct pmc_regs { 1863 /* 0x00: Host Interface PM Channel 1 Status */ 1864 volatile uint8_t PM1STS; 1865 /* 0x01: Host Interface PM Channel 1 Data Out Port */ 1866 volatile uint8_t PM1DO; 1867 /* 0x02: Host Interface PM Channel 1 Data Out Port with SCI# */ 1868 volatile uint8_t PM1DOSCI; 1869 /* 0x03: Host Interface PM Channel 1 Data Out Port with SMI# */ 1870 volatile uint8_t PM1DOSMI; 1871 /* 0x04: Host Interface PM Channel 1 Data In Port */ 1872 volatile uint8_t PM1DI; 1873 /* 0x05: Host Interface PM Channel 1 Data In Port with SCI# */ 1874 volatile uint8_t PM1DISCI; 1875 /* 0x06: Host Interface PM Channel 1 Control */ 1876 volatile uint8_t PM1CTL; 1877 /* 0x07: Host Interface PM Channel 1 Interrupt Control */ 1878 volatile uint8_t PM1IC; 1879 /* 0x08: Host Interface PM Channel 1 Interrupt Enable */ 1880 volatile uint8_t PM1IE; 1881 /* 0x09-0x0f: Reserved1 */ 1882 volatile uint8_t reserved1[7]; 1883 /* 0x10: Host Interface PM Channel 2 Status */ 1884 volatile uint8_t PM2STS; 1885 /* 0x11: Host Interface PM Channel 2 Data Out Port */ 1886 volatile uint8_t PM2DO; 1887 /* 0x12: Host Interface PM Channel 2 Data Out Port with SCI# */ 1888 volatile uint8_t PM2DOSCI; 1889 /* 0x13: Host Interface PM Channel 2 Data Out Port with SMI# */ 1890 volatile uint8_t PM2DOSMI; 1891 /* 0x14: Host Interface PM Channel 2 Data In Port */ 1892 volatile uint8_t PM2DI; 1893 /* 0x15: Host Interface PM Channel 2 Data In Port with SCI# */ 1894 volatile uint8_t PM2DISCI; 1895 /* 0x16: Host Interface PM Channel 2 Control */ 1896 volatile uint8_t PM2CTL; 1897 /* 0x17: Host Interface PM Channel 2 Interrupt Control */ 1898 volatile uint8_t PM2IC; 1899 /* 0x18: Host Interface PM Channel 2 Interrupt Enable */ 1900 volatile uint8_t PM2IE; 1901 /* 0x19: Mailbox Control */ 1902 volatile uint8_t MBXCTRL; 1903 /* 0x1a-0x1f: Reserved2 */ 1904 volatile uint8_t reserved2[6]; 1905 /* 0x20-0xff: Reserved3 */ 1906 volatile uint8_t reserved3[0xe0]; 1907 }; 1908 1909 /* Input Buffer Full Interrupt Enable */ 1910 #define PMC_PM1CTL_IBFIE BIT(0) 1911 /* Output Buffer Full */ 1912 #define PMC_PM1STS_OBF BIT(0) 1913 /* Input Buffer Full */ 1914 #define PMC_PM1STS_IBF BIT(1) 1915 /* General Purpose Flag */ 1916 #define PMC_PM1STS_GPF BIT(2) 1917 /* A2 Address (A2) */ 1918 #define PMC_PM1STS_A2_ADDR BIT(3) 1919 1920 /* PMC2 Input Buffer Full Interrupt Enable */ 1921 #define PMC_PM2CTL_IBFIE BIT(0) 1922 /* General Purpose Flag */ 1923 #define PMC_PM2STS_GPF BIT(2) 1924 1925 /* 1926 * Dedicated Interrupt 1927 * 0b: 1928 * INT3: PMC Output Buffer Empty Int 1929 * INT25: PMC Input Buffer Full Int 1930 * 1b: 1931 * INT3: PMC1 Output Buffer Empty Int 1932 * INT25: PMC1 Input Buffer Full Int 1933 * INT26: PMC2 Output Buffer Empty Int 1934 * INT27: PMC2 Input Buffer Full Int 1935 */ 1936 #define PMC_MBXCTRL_DINT BIT(5) 1937 1938 /* 1939 * eSPI slave registers 1940 */ 1941 struct espi_slave_regs { 1942 /* 0x00-0x03: Reserved1 */ 1943 volatile uint8_t reserved1[4]; 1944 1945 /* 0x04: General Capabilities and Configuration 0 */ 1946 volatile uint8_t GCAPCFG0; 1947 /* 0x05: General Capabilities and Configuration 1 */ 1948 volatile uint8_t GCAPCFG1; 1949 /* 0x06: General Capabilities and Configuration 2 */ 1950 volatile uint8_t GCAPCFG2; 1951 /* 0x07: General Capabilities and Configuration 3 */ 1952 volatile uint8_t GCAPCFG3; 1953 1954 /* Channel 0 (Peripheral Channel) Capabilities and Configurations */ 1955 /* 0x08: Channel 0 Capabilities and Configuration 0 */ 1956 volatile uint8_t CH_PC_CAPCFG0; 1957 /* 0x09: Channel 0 Capabilities and Configuration 1 */ 1958 volatile uint8_t CH_PC_CAPCFG1; 1959 /* 0x0A: Channel 0 Capabilities and Configuration 2 */ 1960 volatile uint8_t CH_PC_CAPCFG2; 1961 /* 0x0B: Channel 0 Capabilities and Configuration 3 */ 1962 volatile uint8_t CH_PC_CAPCFG3; 1963 1964 /* Channel 1 (Virtual Wire Channel) Capabilities and Configurations */ 1965 /* 0x0C: Channel 1 Capabilities and Configuration 0 */ 1966 volatile uint8_t CH_VW_CAPCFG0; 1967 /* 0x0D: Channel 1 Capabilities and Configuration 1 */ 1968 volatile uint8_t CH_VW_CAPCFG1; 1969 /* 0x0E: Channel 1 Capabilities and Configuration 2 */ 1970 volatile uint8_t CH_VW_CAPCFG2; 1971 /* 0x0F: Channel 1 Capabilities and Configuration 3 */ 1972 volatile uint8_t CH_VW_CAPCFG3; 1973 1974 /* Channel 2 (OOB Message Channel) Capabilities and Configurations */ 1975 /* 0x10: Channel 2 Capabilities and Configuration 0 */ 1976 volatile uint8_t CH_OOB_CAPCFG0; 1977 /* 0x11: Channel 2 Capabilities and Configuration 1 */ 1978 volatile uint8_t CH_OOB_CAPCFG1; 1979 /* 0x12: Channel 2 Capabilities and Configuration 2 */ 1980 volatile uint8_t CH_OOB_CAPCFG2; 1981 /* 0x13: Channel 2 Capabilities and Configuration 3 */ 1982 volatile uint8_t CH_OOB_CAPCFG3; 1983 1984 /* Channel 3 (Flash Access Channel) Capabilities and Configurations */ 1985 /* 0x14: Channel 3 Capabilities and Configuration 0 */ 1986 volatile uint8_t CH_FLASH_CAPCFG0; 1987 /* 0x15: Channel 3 Capabilities and Configuration 1 */ 1988 volatile uint8_t CH_FLASH_CAPCFG1; 1989 /* 0x16: Channel 3 Capabilities and Configuration 2 */ 1990 volatile uint8_t CH_FLASH_CAPCFG2; 1991 /* 0x17: Channel 3 Capabilities and Configuration 3 */ 1992 volatile uint8_t CH_FLASH_CAPCFG3; 1993 /* Channel 3 Capabilities and Configurations 2 */ 1994 /* 0x18: Channel 3 Capabilities and Configuration 2-0 */ 1995 volatile uint8_t CH_FLASH_CAPCFG2_0; 1996 /* 0x19: Channel 3 Capabilities and Configuration 2-1 */ 1997 volatile uint8_t CH_FLASH_CAPCFG2_1; 1998 /* 0x1A: Channel 3 Capabilities and Configuration 2-2 */ 1999 volatile uint8_t CH_FLASH_CAPCFG2_2; 2000 /* 0x1B: Channel 3 Capabilities and Configuration 2-3 */ 2001 volatile uint8_t CH_FLASH_CAPCFG2_3; 2002 2003 /* 0x1c-0x1f: Reserved2 */ 2004 volatile uint8_t reserved2[4]; 2005 /* 0x20-0x8f: Reserved3 */ 2006 volatile uint8_t reserved3[0x70]; 2007 2008 /* 0x90: eSPI PC Control 0 */ 2009 volatile uint8_t ESPCTRL0; 2010 /* 0x91: eSPI PC Control 1 */ 2011 volatile uint8_t ESPCTRL1; 2012 /* 0x92: eSPI PC Control 2 */ 2013 volatile uint8_t ESPCTRL2; 2014 /* 0x93: eSPI PC Control 3 */ 2015 volatile uint8_t ESPCTRL3; 2016 /* 0x94: eSPI PC Control 4 */ 2017 volatile uint8_t ESPCTRL4; 2018 /* 0x95: eSPI PC Control 5 */ 2019 volatile uint8_t ESPCTRL5; 2020 /* 0x96: eSPI PC Control 6 */ 2021 volatile uint8_t ESPCTRL6; 2022 /* 0x97: eSPI PC Control 7 */ 2023 volatile uint8_t ESPCTRL7; 2024 /* 0x98-0x9f: Reserved4 */ 2025 volatile uint8_t reserved4[8]; 2026 2027 /* 0xa0: eSPI General Control 0 */ 2028 volatile uint8_t ESGCTRL0; 2029 /* 0xa1: eSPI General Control 1 */ 2030 volatile uint8_t ESGCTRL1; 2031 /* 0xa2: eSPI General Control 2 */ 2032 volatile uint8_t ESGCTRL2; 2033 /* 0xa3: eSPI General Control 3 */ 2034 volatile uint8_t ESGCTRL3; 2035 /* 0xa4-0xaf: Reserved5 */ 2036 volatile uint8_t reserved5[12]; 2037 2038 /* 0xb0: eSPI Upstream Control 0 */ 2039 volatile uint8_t ESUCTRL0; 2040 /* 0xb1: eSPI Upstream Control 1 */ 2041 volatile uint8_t ESUCTRL1; 2042 /* 0xb2: eSPI Upstream Control 2 */ 2043 volatile uint8_t ESUCTRL2; 2044 /* 0xb3: eSPI Upstream Control 3 */ 2045 volatile uint8_t ESUCTRL3; 2046 /* 0xb4-0xb5: Reserved6 */ 2047 volatile uint8_t reserved6[2]; 2048 /* 0xb6: eSPI Upstream Control 6 */ 2049 volatile uint8_t ESUCTRL6; 2050 /* 0xb7: eSPI Upstream Control 7 */ 2051 volatile uint8_t ESUCTRL7; 2052 /* 0xb8: eSPI Upstream Control 8 */ 2053 volatile uint8_t ESUCTRL8; 2054 /* 0xb9-0xbf: Reserved7 */ 2055 volatile uint8_t reserved7[7]; 2056 2057 /* 0xc0: eSPI OOB Control 0 */ 2058 volatile uint8_t ESOCTRL0; 2059 /* 0xc1: eSPI OOB Control 1 */ 2060 volatile uint8_t ESOCTRL1; 2061 /* 0xc2-0xc3: Reserved8 */ 2062 volatile uint8_t reserved8[2]; 2063 /* 0xc4: eSPI OOB Control 4 */ 2064 volatile uint8_t ESOCTRL4; 2065 /* 0xc5-0xcf: Reserved9 */ 2066 volatile uint8_t reserved9[11]; 2067 2068 /* 0xd0: eSPI SAFS Control 0 */ 2069 volatile uint8_t ESPISAFSC0; 2070 /* 0xd1: eSPI SAFS Control 1 */ 2071 volatile uint8_t ESPISAFSC1; 2072 /* 0xd2: eSPI SAFS Control 2 */ 2073 volatile uint8_t ESPISAFSC2; 2074 /* 0xd3: eSPI SAFS Control 3 */ 2075 volatile uint8_t ESPISAFSC3; 2076 /* 0xd4: eSPI SAFS Control 4 */ 2077 volatile uint8_t ESPISAFSC4; 2078 /* 0xd5: eSPI SAFS Control 5 */ 2079 volatile uint8_t ESPISAFSC5; 2080 /* 0xd6: eSPI SAFS Control 6 */ 2081 volatile uint8_t ESPISAFSC6; 2082 /* 0xd7: eSPI SAFS Control 7 */ 2083 volatile uint8_t ESPISAFSC7; 2084 }; 2085 2086 /* 2087 * eSPI VW registers 2088 */ 2089 struct espi_vw_regs { 2090 /* 0x00-0x7f: VW index */ 2091 volatile uint8_t VW_INDEX[0x80]; 2092 /* 0x80-0x8f: Reserved1 */ 2093 volatile uint8_t reserved1[0x10]; 2094 /* 0x90: VW Contrl 0 */ 2095 volatile uint8_t VWCTRL0; 2096 /* 0x91: VW Contrl 1 */ 2097 volatile uint8_t VWCTRL1; 2098 /* 0x92: VW Contrl 2 */ 2099 volatile uint8_t VWCTRL2; 2100 /* 0x93: VW Contrl 3 */ 2101 volatile uint8_t VWCTRL3; 2102 /* 0x94: Reserved2 */ 2103 volatile uint8_t reserved2; 2104 /* 0x95: VW Contrl 5 */ 2105 volatile uint8_t VWCTRL5; 2106 /* 0x96: VW Contrl 6 */ 2107 volatile uint8_t VWCTRL6; 2108 /* 0x97: VW Contrl 7 */ 2109 volatile uint8_t VWCTRL7; 2110 /* 0x98-0x99: Reserved3 */ 2111 volatile uint8_t reserved3[2]; 2112 }; 2113 2114 #define ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE 80 2115 /* 2116 * eSPI Queue 0 registers 2117 */ 2118 struct espi_queue0_regs { 2119 /* 0x00-0x3f: PUT_PC Data Byte 0-63 */ 2120 volatile uint8_t PUT_PC_DATA[0x40]; 2121 /* 0x40-0x7f: Reserved1 */ 2122 volatile uint8_t reserved1[0x40]; 2123 /* 0x80-0xcf: PUT_OOB Data Byte 0-79 */ 2124 volatile uint8_t PUT_OOB_DATA[ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE]; 2125 }; 2126 2127 /* 2128 * eSPI Queue 1 registers 2129 */ 2130 struct espi_queue1_regs { 2131 /* 0x00-0x4f: Upstream Data Byte 0-79 */ 2132 volatile uint8_t UPSTREAM_DATA[ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE]; 2133 /* 0x50-0x7f: Reserved1 */ 2134 volatile uint8_t reserved1[0x30]; 2135 /* 0x80-0xbf: PUT_FLASH_NP Data Byte 0-63 */ 2136 volatile uint8_t PUT_FLASH_NP_DATA[0x40]; 2137 }; 2138 2139 #endif /* !__ASSEMBLER__ */ 2140 2141 2142 /** 2143 * 2144 * (3Axxh) SPI Slave Controller (SPISC) registers 2145 * 2146 */ 2147 #ifndef __ASSEMBLER__ 2148 struct spisc_it8xxx2_regs { 2149 /* 0x00: SPI Slave General Control */ 2150 volatile uint8_t SPISC_SPISGCR; 2151 /* 0x01: Tx/Rx FIFO Access */ 2152 volatile uint8_t SPISC_TXRXFAR; 2153 /* 0x02: Tx FIFO Control */ 2154 volatile uint8_t SPISC_TXFCR; 2155 /* 0x03: SPI Slave General Control 2 */ 2156 volatile uint8_t SPISC_SPISGCR2; 2157 /* 0x04: Interrupt Mask */ 2158 volatile uint8_t SPISC_IMR; 2159 /* 0x05: Interrupt Status */ 2160 volatile uint8_t SPISC_ISR; 2161 /* 0x06: Tx FIFO Status */ 2162 volatile uint8_t SPISC_TXFSR; 2163 /* 0x07: Rx FIFO Status */ 2164 volatile uint8_t SPISC_RXFSR; 2165 /* 0x08: CPU Write Tx FIFO Data Byte0 */ 2166 volatile uint8_t SPISC_CPUWTXFDB0R; 2167 /* 0x09: FIFO Control / CPU Write Tx FIFO Data Byte1 */ 2168 volatile uint8_t SPISC_FCR; 2169 /* 0x0A: CPU Write Tx FIFO Data Byte2 */ 2170 volatile uint8_t SPISC_CPUWTXFDB2R; 2171 /* 0x0B: SPI Slave Response Data / CPU Write Tx FIFO Data Byte3 */ 2172 volatile uint8_t SPISC_SPISRDR; 2173 /* 0x0C: Rx FIFO Readout Data Byte0 */ 2174 volatile uint8_t SPISC_RXFRDRB0; 2175 /* 0x0D: Rx FIFO Readout Data Byte1 */ 2176 volatile uint8_t SPISC_RXFRDRB1; 2177 /* 0x0E: Rx FIFO Readout Data Byte2 */ 2178 volatile uint8_t SPISC_RXFRDRB2; 2179 /* 0x0F: Rx FIFO Readout Data Byte3 */ 2180 volatile uint8_t SPISC_RXFRDRB3; 2181 /* 0x10-0x17: Reserved1 */ 2182 volatile uint8_t reserved1[8]; 2183 /* 0x18: FIFO Target Count Byte0 */ 2184 volatile uint8_t SPISC_FTCB0R; 2185 /* 0x19: FIFO Target Count Byte1 */ 2186 volatile uint8_t SPISC_FTCB1R; 2187 /* 0x1A: Target Count Capture Byte0 */ 2188 volatile uint8_t SPISC_TCCB0; 2189 /* 0x1B: Target Count Capture Byte1 */ 2190 volatile uint8_t SPISC_TCCB1; 2191 /* 0x1C-0x1D: Reserved2 */ 2192 volatile uint8_t reserved2[2]; 2193 /* 0x1E: Hardware Parsing 2 */ 2194 volatile uint8_t SPISC_HPR2; 2195 /* 0x1F-0x25: Reserved3 */ 2196 volatile uint8_t reserved3[7]; 2197 /* 0x26: Rx Valid Length Interrupt Status Mask */ 2198 volatile uint8_t SPISC_RXVLISMR; 2199 /* 0x27: Rx Valid Length Interrupt Status */ 2200 volatile uint8_t SPISC_RXVLISR; 2201 }; 2202 #endif /* !__ASSEMBLER__ */ 2203 2204 /* SPISC register fields */ 2205 /* 0x00: SPI Slave General Control */ 2206 #define IT8XXX2_SPISC_SPISCEN BIT(0) 2207 /* 0x01: Tx/Rx FIFO Access */ 2208 #define IT8XXX2_SPISC_CPURXF1A BIT(3) 2209 #define IT8XXX2_SPISC_CPUTFA BIT(1) 2210 /* 0x02: Tx FIFO Control */ 2211 #define IT8XXX2_SPISC_TXFCMR BIT(2) 2212 #define IT8XXX2_SPISC_TXFR BIT(1) 2213 #define IT8XXX2_SPISC_TXFS BIT(0) 2214 /* 0x03: SPI Slave General Control 2 */ 2215 #define IT8XXX2_SPISC_RXF2OC BIT(4) 2216 #define IT8XXX2_SPISC_RXF1OC BIT(3) 2217 #define IT8XXX2_SPISC_RXFAR BIT(0) 2218 /* 0x04: Interrupt Mask */ 2219 #define IT8XXX2_SPISC_EDIM BIT(2) 2220 /* 0x06: Tx FIFO Status */ 2221 #define IT8XXX2_SPISC_ENDDETECTINT BIT(2) 2222 /* 0x09: FIFO Control */ 2223 #define IT8XXX2_SPISC_SPISRTXF BIT(2) 2224 #define IT8XXX2_SPISC_RXFR BIT(1) 2225 #define IT8XXX2_SPISC_RXFCMR BIT(0) 2226 /* 0x26: Rx Valid Length Interrupt Status Mask */ 2227 #define IT8XXX2_SPISC_RVLIM BIT(0) 2228 /* 0x27: Rx Valid Length Interrupt Status */ 2229 #define IT8XXX2_SPISC_RVLI BIT(0) 2230 2231 #endif /* CHIP_CHIPREGS_H */ 2232
