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Searched refs:DT_PROP_OR (Results 1 – 25 of 62) sorted by relevance

123

/Zephyr-Core-3.6.0/include/zephyr/drivers/
Dregulator.h189 .min_uv = DT_PROP_OR(node_id, regulator_min_microvolt, \
191 .max_uv = DT_PROP_OR(node_id, regulator_max_microvolt, \
193 .init_uv = DT_PROP_OR(node_id, regulator_init_microvolt, \
195 .min_ua = DT_PROP_OR(node_id, regulator_min_microamp, \
197 .max_ua = DT_PROP_OR(node_id, regulator_max_microamp, \
199 .init_ua = DT_PROP_OR(node_id, regulator_init_microamp, \
201 .startup_delay_us = DT_PROP_OR(node_id, startup_delay_us, 0), \
202 .off_on_delay_us = DT_PROP_OR(node_id, off_on_delay_us, 0), \
204 DT_PROP_OR(node_id, regulator_allowed_modes, {}), \
207 .initial_mode = DT_PROP_OR(node_id, regulator_initial_mode, \
[all …]
Dadc.h232 .input_positive = DT_PROP_OR(node_id, zephyr_input_positive, 0), \
233 .input_negative = DT_PROP_OR(node_id, zephyr_input_negative, 0),)) \
238 .current_source_pin = DT_PROP_OR(node_id, zephyr_current_source_pin, {0}),)) \
313 .vref_mv = DT_PROP_OR(node_id, zephyr_vref_mv, 0), \
314 .resolution = DT_PROP_OR(node_id, zephyr_resolution, 0), \
315 .oversampling = DT_PROP_OR(node_id, zephyr_oversampling, 0),))
/Zephyr-Core-3.6.0/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/
Dradio_nrf5_fem_generic.h35 DT_PROP_OR(FEM_NODE, ctx_settle_time_us, 0)
46 DT_PROP_OR(FEM_NODE, crx_settle_time_us, 0)
Dradio_df.h12 #define PDU_ANTENNA DT_PROP_OR(RADIO_NODE, dfe_pdu_antenna, 0)
/Zephyr-Core-3.6.0/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h67 #define STM32_AHB5_PRESCALER DT_PROP_OR(DT_NODELABEL(rcc), ahb5_prescaler, 1)
141 #define STM32_PLL_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_p, 1)
143 #define STM32_PLL_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_q, 1)
145 #define STM32_PLL_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_r, 1)
147 #define STM32_PLL_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll), fracn, 1)
155 #define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1)
163 #define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1)
172 #define STM32_PLL2_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_p, 1)
174 #define STM32_PLL2_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_q, 1)
176 #define STM32_PLL2_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_r, 1)
[all …]
/Zephyr-Core-3.6.0/include/zephyr/pm/
Dstate.h209 .substate_id = DT_PROP_OR(node_id, substate_id, 0), \
210 .min_residency_us = DT_PROP_OR(node_id, min_residency_us, 0), \
211 .exit_latency_us = DT_PROP_OR(node_id, exit_latency_us, 0), \
/Zephyr-Core-3.6.0/drivers/sensor/pcnt_esp32/
Dpcnt_esp32.c370 .filter = DT_PROP_OR(node_id, filter, 0) > 1024 ? 1024 \
371 : DT_PROP_OR(node_id, filter, 0), \
374 .sig_pos_mode = DT_PROP_OR(DT_CHILD(node_id, channela_0), \
376 .sig_neg_mode = DT_PROP_OR(DT_CHILD(node_id, channela_0), \
379 DT_PROP_OR(DT_CHILD(node_id, channela_0), ctrl_l_mode, 0), \
381 DT_PROP_OR(DT_CHILD(node_id, channela_0), ctrl_h_mode, 0), \
385 .sig_pos_mode = DT_PROP_OR(DT_CHILD(node_id, channelb_0), \
387 .sig_neg_mode = DT_PROP_OR(DT_CHILD(node_id, channelb_0), \
390 DT_PROP_OR(DT_CHILD(node_id, channelb_0), ctrl_l_mode, 0), \
392 DT_PROP_OR(DT_CHILD(node_id, channelb_0), ctrl_h_mode, 0), \
/Zephyr-Core-3.6.0/modules/trusted-firmware-m/nordic_nrf/include/
Ddevice_cfg.h24 #define DEFAULT_UART_BAUDRATE DT_PROP_OR(DT_NODELABEL(TFM_UART), current_speed, 115200)
/Zephyr-Core-3.6.0/include/zephyr/drivers/pcie/
Dpcie.h74 #define PCIE_DT_ID(node_id) PCIE_ID(DT_PROP_OR(node_id, vendor_id, 0xffff), \
75 DT_PROP_OR(node_id, device_id, 0xffff))
100 .class_rev = DT_PROP_OR(node_id, class_rev, 0), \
101 .class_rev_mask = DT_PROP_OR(node_id, class_rev_mask, 0), \
/Zephyr-Core-3.6.0/drivers/gpio/
Dgpio_hogs.c39 DT_PROP_OR(node_id, gpio_controller, 0)
43 IF_ENABLED(DT_PROP_OR(node_id, gpio_hog, 0), 1)
/Zephyr-Core-3.6.0/include/zephyr/devicetree/
Dcan.h66 MIN(DT_PROP_OR(DT_CHILD(node_id, can_transceiver), max_bitrate, max), max))
/Zephyr-Core-3.6.0/include/zephyr/drivers/adc/
Dvoltage_divider.h31 .full_ohms = DT_PROP_OR(node_id, full_ohms, 0), \
/Zephyr-Core-3.6.0/drivers/dma/
Ddmamux_stm32.c341 #define DMA_1_BEGIN_DMAMUX_CHANNEL DT_PROP_OR(DT_NODELABEL(dma1), dma_offset, 0)
343 DT_PROP_OR(DT_NODELABEL(dma1), dma_requests, 0))
347 #define DMA_2_BEGIN_DMAMUX_CHANNEL DT_PROP_OR(DT_NODELABEL(dma2), dma_offset, 0)
349 DT_PROP_OR(DT_NODELABEL(dma2), dma_requests, 0))
353 #define BDMA_1_BEGIN_DMAMUX_CHANNEL DT_PROP_OR(DT_NODELABEL(bdma1), dma_offset, 0)
355 DT_PROP_OR(DT_NODELABEL(bdma1), dma_requests, 0))
/Zephyr-Core-3.6.0/soc/arm/nxp_imx/rt5xx/
Dpower.c17 DT_PROP_OR(NODE_ID, deep_sleep_config, {}))
/Zephyr-Core-3.6.0/subsys/storage/flash_map/
Dflash_map_default.c21 .fa_label = DT_PROP_OR(part, label, NULL), },
/Zephyr-Core-3.6.0/soc/xtensa/intel_adsp/common/include/
Dmem_window.h21 #define WIN_OFFSET(n) (DT_PROP_OR(MEM_WINDOW_NODE(n), offset, (WIN##n##_OFFSET)))
/Zephyr-Core-3.6.0/include/zephyr/
Dcache.h414 return DT_PROP_OR(_CPU, d_cache_line_size, 0); in sys_cache_data_line_size_get()
441 return DT_PROP_OR(_CPU, i_cache_line_size, 0); in sys_cache_instr_line_size_get()
/Zephyr-Core-3.6.0/include/zephyr/drivers/can/
Dcan_sja1000.h132 .phase_seg1 = DT_PROP_OR(node_id, phase_seg1, 0), \
133 .phase_seg2 = DT_PROP_OR(node_id, phase_seg2, 0), \
Dcan_mcan.h1310 .prop_ts1 = DT_PROP_OR(node_id, prop_seg, 0) + DT_PROP_OR(node_id, phase_seg1, 0), \
1311 .ts2 = DT_PROP_OR(node_id, phase_seg2, 0), \
1313 .prop_ts1_data = DT_PROP_OR(node_id, prop_seg_data, 0) + \
1314 DT_PROP_OR(node_id, phase_seg1_data, 0), \
1315 .ts2_data = DT_PROP_OR(node_id, phase_seg2_data, 0), \
1329 .prop_ts1 = DT_PROP_OR(node_id, prop_seg, 0) + DT_PROP_OR(node_id, phase_seg1, 0), \
1330 .ts2 = DT_PROP_OR(node_id, phase_seg2, 0), \
/Zephyr-Core-3.6.0/drivers/fuel_gauge/sbs_gauge/
Demul_sbs_gauge.c370 .cutoff_support = DT_PROP_OR(DT_DRV_INST(n), battery_cutoff_support, false), \
371 .cutoff_reg_addr = DT_PROP_OR(DT_DRV_INST(n), battery_cutoff_reg_addr, 0), \
372 .cutoff_payload = DT_PROP_OR(DT_DRV_INST(n), battery_cutoff_payload, {}), \
/Zephyr-Core-3.6.0/soc/arm/quicklogic_eos_s3/
Dpinctrl_soc.h40 .drive_strength = DT_PROP_OR(node_id, drive_strength, 4), \
/Zephyr-Core-3.6.0/drivers/adc/
Dadc_max1125x.c789 .self_calibration = DT_PROP_OR(DT_INST_MAX1125X(n, t), self_calibration, 0), \
790 .gpio.gpio0_enable = DT_PROP_OR(DT_INST_MAX1125X(n, t), gpio0_enable, 1), \
791 .gpio.gpio1_enable = DT_PROP_OR(DT_INST_MAX1125X(n, t), gpio1_enable, 0), \
792 .gpio.gpio0_direction = DT_PROP_OR(DT_INST_MAX1125X(n, t), gpio0_direction, 0), \
793 .gpio.gpio1_direction = DT_PROP_OR(DT_INST_MAX1125X(n, t), gpio1_direction, 0), \
794 .gpo.gpo0_enable = DT_PROP_OR(DT_INST_MAX1125X(n, t), gpo1_enable, 0), \
795 .gpo.gpo1_enable = DT_PROP_OR(DT_INST_MAX1125X(n, t), gpo1_enable, 0), \
/Zephyr-Core-3.6.0/soc/arm/nxp_kinetis/kwx/
Dsoc_kw4xz.c22 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
/Zephyr-Core-3.6.0/soc/arm/nxp_kinetis/kl2x/
Dsoc.c21 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
/Zephyr-Core-3.6.0/soc/arm/nxp_kinetis/k2x/
Dsoc.c34 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1

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