1 /* 2 * Copyright 2022 Meta Platforms, Inc. and its affiliates. 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #ifndef ZEPHYR_DRIVERS_SERIAL_UART_CDNS_H_ 7 #define ZEPHYR_DRIVERS_SERIAL_UART_CDNS_H_ 8 9 #include <zephyr/arch/cpu.h> 10 #include <zephyr/drivers/uart.h> 11 #include <zephyr/kernel.h> 12 13 enum csr_parity_val { 14 EVEN_PARITY_VAL, 15 ODD_PARITY_VAL, 16 SPACE_PARITY_VAL, 17 MARK_PARITY_VAL, 18 NO_PARITY_VAL 19 }; 20 21 /* @brief Control(CTRL) Registers offset 0x00 */ 22 #define CTRL_STPBRK_MASK (1 << 8) 23 #define CTRL_STPBRK_SHIFT (8) 24 #define CTRL_STTBRK_MASK (1 << 7) 25 #define CTRL_STTBRK_SHIFT (7) 26 #define CTRL_RSTTO_MASK (1 << 6) 27 #define CTRL_RSTTO_SHIFT (6) 28 #define CTRL_TXDIS_MASK (1 << 5) 29 #define CTRL_TXDIS_SHIFT (5) 30 #define CTRL_TXEN_MASK (1 << 4) 31 #define CTRL_TXEN_SHIFT (4) 32 #define CTRL_RXDIS_MASK (1 << 3) 33 #define CTRL_RXDIS_SHIFT (3) 34 #define CTRL_RXEN_MASK (1 << 2) 35 #define CTRL_RXEN_SHIFT (2) 36 #define CTRL_TXRES_MASK (1 << 1) 37 #define CTRL_TXRES_SHIFT (1) 38 #define CTRL_RXRES_MASK (1 << 0) 39 #define CTRL_RXRES_SHIFT (0) 40 41 /* @brief Mode Registers offset 0x04 */ 42 #define MODE_WSIZE_MASK (0x3 << 12) 43 #define MODE_WSIZE_SHIFT (12) 44 #define MODE_WSIZE_SIZE (2) 45 #define MODE_IRMODE_MASK (1 << 11) 46 #define MODE_IRMODE_SHIFT (11) 47 #define MODE_UCLKEN_MASK (1 << 10) 48 #define MODE_UCLKEN_SHIFT (10) 49 #define MODE_CHMOD_MASK (0x3 << 8) 50 #define MODE_CHMOD_SHIFT (8) 51 #define MODE_CHMOD_SIZE (2) 52 #define MODE_NBSTOP_MASK (0x3 << 6) 53 #define MODE_NBSTOP_SHIFT (6) 54 #define MODE_NBSTOP_SIZE (2) 55 #define MODE_PAR_MASK (0x7 << 3) 56 #define MODE_PAR_SHIFT (3) 57 #define MODE_PAR_SIZE (3) 58 #define MODE_CHRL_MASK (0x3 << 1) 59 #define MODE_CHRL_SHIFT (2) 60 #define MODE_CHRL_SIZE (2) 61 #define MODE_CLKS_MASK (1 << 0) 62 #define MODE_CLKS_SHIFT (0) 63 64 /* @brief IER, IDR, IMR and CSIR Registers offset 0x08, 0xC, 0x10 and 0x14 */ 65 #define CSR_RBRK_MASK (1 << 13) 66 #define CSR_RBRK_SHIFT (13) 67 #define CSR_TOVR_MASK (1 << 12) 68 #define CSR_TOVR_SHIFT (12) 69 #define CSR_TNFUL_MASK (1 << 11) 70 #define CSR_TNFUL_SHIFT (11) 71 #define CSR_TTRIG_MASK (1 << 10) 72 #define CSR_TTRIG_SHIFT (10) 73 #define CSR_DMSI_MASK (1 << 9) 74 #define CSR_DMSI_SHIFT (9) 75 #define CSR_TOUT_MASK (1 << 8) 76 #define CSR_TOUT_SHIFT (8) 77 #define CSR_PARE_MASK (1 << 7) 78 #define CSR_PARE_SHIFT (7) 79 #define CSR_FRAME_MASK (1 << 6) 80 #define CSR_FRAME_SHIFT (6) 81 #define CSR_ROVR_MASK (1 << 5) 82 #define CSR_ROVR_SHIFT (5) 83 #define CSR_TFUL_MASK (1 << 4) 84 #define CSR_TFUL_SHIFT (4) 85 #define CSR_TEMPTY_MASK (1 << 3) 86 #define CSR_TEMPTY_SHIFT (3) 87 #define CSR_RFUL_MASK (1 << 2) 88 #define CSR_RFUL_SHIFT (2) 89 #define CSR_REMPTY_MASK (1 << 1) 90 #define CSR_REMPTY_SHIFT (1) 91 #define CSR_RTRIG_MASK (1 << 0) 92 #define CSR_RTRIG_SHIFT (0) 93 94 #define RXDATA_MASK 0xFF /* Receive Data Mask */ 95 #define MAX_FIFO_SIZE (64) 96 97 #define DEFAULT_RTO_PERIODS_FACTOR 8 98 99 #define SET_VAL32(name, val) (((uint32_t)(val) << name##_SHIFT) & name##_MASK) 100 101 #define CDNS_PARTITY_MAP(parity) \ 102 (parity == UART_CFG_PARITY_NONE) ? NO_PARITY_VAL \ 103 : (parity == UART_CFG_PARITY_ODD) ? ODD_PARITY_VAL \ 104 : (parity == UART_CFG_PARITY_MARK) ? MARK_PARITY_VAL \ 105 : (parity == UART_CFG_PARITY_SPACE) ? SPACE_PARITY_VAL \ 106 : EVEN_PARITY_VAL 107 struct uart_cdns_regs { 108 volatile uint32_t ctrl; /* Control Register */ 109 volatile uint32_t mode; /* Mode Register */ 110 volatile uint32_t intr_enable; /* Interrupt Enable Register */ 111 volatile uint32_t intr_disable; /* Interrupt Disable Register */ 112 volatile uint32_t intr_mask; /* Interrupt Mask Register */ 113 volatile uint32_t channel_intr_status; /* Channel Interrupt Status Register */ 114 volatile uint32_t baud_rate_gen; /* Baud Rate Generator Register */ 115 volatile uint32_t rx_timeout; /* Receiver Timeout Register */ 116 volatile uint32_t rx_fifo_trigger_level; /* Receiver FIFO Trigger Level Register */ 117 volatile uint32_t modem_control; /* Modem Control Register */ 118 volatile uint32_t modem_status; /* Modem Status Register */ 119 volatile uint32_t channel_status; /* Channel status */ 120 volatile uint32_t rx_tx_fifo; /* RX TX FIFO Register */ 121 volatile uint32_t baud_rate_div; /* Baud Rate Divider Register */ 122 volatile uint32_t flow_ctrl_delay; /* Flow Control Delay Register */ 123 volatile uint32_t rpwr; /* IR Minimum Received Pulse Register */ 124 volatile uint32_t tpwr; /* IR TRansmitted Pulse Width Register */ 125 volatile uint32_t tx_fifo_trigger_level; /* Transmitter FIFO trigger level */ 126 volatile uint32_t rbrs; /* RX FIFO Byte Status Register */ 127 }; 128 129 struct uart_cdns_device_config { 130 uint32_t port; 131 uint32_t bdiv; 132 uint32_t sys_clk_freq; 133 uint32_t baud_rate; 134 uint8_t parity; 135 void (*cfg_func)(void); 136 }; 137 138 struct uart_cdns_data { 139 #ifdef CONFIG_UART_INTERRUPT_DRIVEN 140 uart_irq_callback_user_data_t callback; 141 void *cb_data; 142 #endif 143 }; 144 145 #endif /* ZEPHYR_DRIVERS_SERIAL_UART_CDNS_H_ */ 146
