Searched refs:CORE_CLK (Results 1 – 5 of 5) sorted by relevance
89 *rate = CORE_CLK/(AHB6DIV_VAL + 1); in npcx_clock_control_get_subsys_rate()92 *rate = CORE_CLK/(FIUDIV_VAL + 1); in npcx_clock_control_get_subsys_rate()96 *rate = CORE_CLK/(FIU1DIV_VAL + 1); in npcx_clock_control_get_subsys_rate()100 *rate = CORE_CLK; in npcx_clock_control_get_subsys_rate()155 BUILD_ASSERT(CORE_CLK <= MAX_OFMCLK && CORE_CLK >= MHZ(4) &&156 OFMCLK % CORE_CLK == 0 &&157 OFMCLK / CORE_CLK <= 10,159 BUILD_ASSERT(CORE_CLK / (FIUDIV_VAL + 1) <= (MAX_OFMCLK / 2) &&160 CORE_CLK / (FIUDIV_VAL + 1) >= MHZ(4),163 BUILD_ASSERT(CORE_CLK / (FIU1DIV_VAL + 1) <= (MAX_OFMCLK / 2) &&[all …]
72 #define CORE_CLK (OFMCLK / DT_PROP(DT_NODELABEL(pcc), core_prescaler)) macro87 #if (CORE_CLK > (MAX_OFMCLK / 2))94 #if (CORE_CLK > (MAX_OFMCLK / 2))101 #if (CORE_CLK > (MAX_OFMCLK / 2))
94 core-prescaler = <6>; /* CORE_CLK runs at 15MHz */
113 core-prescaler = <6>; /* CORE_CLK runs at 15MHz */
114 core-prescaler = <8>; /* CORE_CLK runs at 15MHz */
