CLKMGR_PERPLL_PLLC0 (reference) in projects: Zephyr-Core-3.6.0

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Searched refs:CLKMGR_PERPLL_PLLC0 (Results 1 – 4 of 4) sorted by relevance

/Zephyr-Core-3.6.0/drivers/clock_control/
D	clock_control_agilex5_ll.h	`51 #define CLKMGR_PERPLL_PLLC0 0x34 macro`
D	clock_agilex_ll.c	`101 CLKMGR_PERPLL_PLLC0); in get_mpu_clk()`
D	clock_control_agilex5_ll.c	`131 mpu_clk = get_clk_freq(CLKMGR_MAINPLL_MPUCLK, CLKMGR_MAINPLL_PLLC0, CLKMGR_PERPLL_PLLC0); in get_mpu_clk()`
/Zephyr-Core-3.6.0/include/zephyr/drivers/clock_control/
D	clock_agilex_ll.h	`48 #define CLKMGR_PERPLL_PLLC0 0x30 macro`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
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babblesim_ext_2G4_modem_magic-3.6.0-3.5.0-3.4.0
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babblesim_ext_libCryptov1-3.7.0-3.6.0-3.5.0-3.4.0
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