1 /*
2 * Copyright (c) 2021 ITE Corporation. All Rights Reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT ite_it8xxx2_adc
8
9 #define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
10 #include <zephyr/logging/log.h>
11 LOG_MODULE_REGISTER(adc_ite_it8xxx2);
12
13 #include <zephyr/drivers/adc.h>
14 #include <zephyr/drivers/pinctrl.h>
15 #include <soc.h>
16 #include <soc_dt.h>
17 #include <errno.h>
18 #include <assert.h>
19 #include <zephyr/irq.h>
20
21 #define ADC_CONTEXT_USES_KERNEL_TIMER
22 #include "adc_context.h"
23
24 /* ADC internal reference voltage (Unit:mV) */
25 #ifdef CONFIG_ADC_IT8XXX2_VOL_FULL_SCALE
26 #define IT8XXX2_ADC_VREF_VOL 3300
27 #else
28 #define IT8XXX2_ADC_VREF_VOL 3000
29 #endif
30 /* ADC channels disabled */
31 #define IT8XXX2_ADC_CHANNEL_DISABLED 0x1F
32 /* ADC sample time delay (Unit:us) */
33 #define IT8XXX2_ADC_SAMPLE_TIME_US 500
34 /* Wait next clock rising (Clock source 32.768K) */
35 #define IT8XXX2_WAIT_NEXT_CLOCK_TIME_US 31
36 /* ADC channels offset */
37 #define ADC_CHANNEL_SHIFT 5
38 #define ADC_CHANNEL_OFFSET(ch) ((ch)-CHIP_ADC_CH13-ADC_CHANNEL_SHIFT)
39
40 #ifdef CONFIG_ADC_IT8XXX2_VOL_FULL_SCALE
41 #define ADC_0_7_FULL_SCALE_MASK GENMASK(7, 0)
42 #define ADC_8_10_FULL_SCALE_MASK GENMASK(2, 0)
43 #define ADC_13_16_FULL_SCALE_MASK GENMASK(3, 0)
44 #endif
45
46 #ifdef CONFIG_SOC_IT8XXX2_EC_BUS_24MHZ
47 /* Select analog clock division factor */
48 #define ADC_SACLKDIV_MASK GENMASK(6, 4)
49 #define ADC_SACLKDIV(div) FIELD_PREP(ADC_SACLKDIV_MASK, div)
50 #endif
51
52 /* List of ADC channels. */
53 enum chip_adc_channel {
54 CHIP_ADC_CH0 = 0,
55 CHIP_ADC_CH1,
56 CHIP_ADC_CH2,
57 CHIP_ADC_CH3,
58 CHIP_ADC_CH4,
59 CHIP_ADC_CH5,
60 CHIP_ADC_CH6,
61 CHIP_ADC_CH7,
62 CHIP_ADC_CH13,
63 CHIP_ADC_CH14,
64 CHIP_ADC_CH15,
65 CHIP_ADC_CH16,
66 CHIP_ADC_COUNT,
67 };
68
69 struct adc_it8xxx2_data {
70 struct adc_context ctx;
71 struct k_sem sem;
72 /* Channel ID */
73 uint32_t ch;
74 /* Save ADC result to the buffer. */
75 uint16_t *buffer;
76 /*
77 * The sample buffer pointer should be prepared
78 * for writing of next sampling results.
79 */
80 uint16_t *repeat_buffer;
81 };
82
83 /*
84 * Structure adc_it8xxx2_cfg is about the setting of adc
85 * this config will be used at initial time
86 */
87 struct adc_it8xxx2_cfg {
88 /* ADC alternate configuration */
89 const struct pinctrl_dev_config *pcfg;
90 };
91
92 #define ADC_IT8XXX2_REG_BASE \
93 ((struct adc_it8xxx2_regs *)(DT_INST_REG_ADDR(0)))
94
adc_it8xxx2_channel_setup(const struct device * dev,const struct adc_channel_cfg * channel_cfg)95 static int adc_it8xxx2_channel_setup(const struct device *dev,
96 const struct adc_channel_cfg *channel_cfg)
97 {
98 uint8_t channel_id = channel_cfg->channel_id;
99
100 if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
101 LOG_ERR("Selected ADC acquisition time is not valid");
102 return -EINVAL;
103 }
104
105 /* Support channels 0~7 and 13~16 */
106 if (!((channel_id >= 0 && channel_id <= 7) ||
107 (channel_id >= 13 && channel_id <= 16))) {
108 LOG_ERR("Channel %d is not valid", channel_id);
109 return -EINVAL;
110 }
111
112 /* Channels 13~16 should be shifted by 5 */
113 if (channel_id > CHIP_ADC_CH7) {
114 channel_id -= ADC_CHANNEL_SHIFT;
115 }
116
117 if (channel_cfg->gain != ADC_GAIN_1) {
118 LOG_ERR("Invalid channel gain");
119 return -EINVAL;
120 }
121
122 if (channel_cfg->reference != ADC_REF_INTERNAL) {
123 LOG_ERR("Invalid channel reference");
124 return -EINVAL;
125 }
126
127 LOG_DBG("Channel setup succeeded!");
128 return 0;
129 }
130
adc_disable_measurement(uint32_t ch)131 static void adc_disable_measurement(uint32_t ch)
132 {
133 struct adc_it8xxx2_regs *const adc_regs = ADC_IT8XXX2_REG_BASE;
134
135 if (ch <= CHIP_ADC_CH7) {
136 /*
137 * Disable measurement.
138 * bit(4:0) = 0x1f : channel disable
139 */
140 adc_regs->VCH0CTL = IT8XXX2_ADC_DATVAL |
141 IT8XXX2_ADC_CHANNEL_DISABLED;
142 } else {
143 /*
144 * Channels 13~16 controller setting.
145 * bit7 = 1: End of conversion. New data is available in
146 * VCHDATL/VCHDATM.
147 */
148 adc_regs->adc_vchs_ctrl[ADC_CHANNEL_OFFSET(ch)].VCHCTL =
149 IT8XXX2_ADC_DATVAL;
150 }
151
152 /* ADC module disable */
153 adc_regs->ADCCFG &= ~IT8XXX2_ADC_ADCEN;
154
155 /* disable adc interrupt */
156 irq_disable(DT_INST_IRQN(0));
157 }
158
adc_data_valid(const struct device * dev)159 static int adc_data_valid(const struct device *dev)
160 {
161 struct adc_it8xxx2_regs *const adc_regs = ADC_IT8XXX2_REG_BASE;
162 struct adc_it8xxx2_data *data = dev->data;
163
164 return (data->ch <= CHIP_ADC_CH7) ?
165 (adc_regs->VCH0CTL & IT8XXX2_ADC_DATVAL) :
166 (adc_regs->ADCDVSTS2 & BIT(ADC_CHANNEL_OFFSET(data->ch)));
167 }
168
169 /* Get result for each ADC selected channel. */
adc_it8xxx2_get_sample(const struct device * dev)170 static void adc_it8xxx2_get_sample(const struct device *dev)
171 {
172 struct adc_it8xxx2_data *data = dev->data;
173 struct adc_it8xxx2_regs *const adc_regs = ADC_IT8XXX2_REG_BASE;
174
175 if (adc_data_valid(dev)) {
176 if (data->ch <= CHIP_ADC_CH7) {
177 /* Read adc raw data of msb and lsb */
178 *data->buffer++ = adc_regs->VCH0DATM << 8 |
179 adc_regs->VCH0DATL;
180 } else {
181 /* Read adc channels 13~16 raw data of msb and lsb */
182 *data->buffer++ =
183 adc_regs->adc_vchs_ctrl[ADC_CHANNEL_OFFSET(data->ch)].VCHDATM << 8 |
184 adc_regs->adc_vchs_ctrl[ADC_CHANNEL_OFFSET(data->ch)].VCHDATL;
185 }
186 } else {
187 LOG_WRN("ADC failed to read (regs=%x, ch=%d)",
188 adc_regs->ADCDVSTS, data->ch);
189 }
190
191 adc_disable_measurement(data->ch);
192 }
193
adc_poll_valid_data(void)194 static void adc_poll_valid_data(void)
195 {
196 const struct device *const dev = DEVICE_DT_INST_GET(0);
197 int valid = 0;
198
199 /*
200 * If the polling waits for a valid data longer than
201 * the sampling time limit, the program will return.
202 */
203 for (int i = 0U; i < (IT8XXX2_ADC_SAMPLE_TIME_US /
204 IT8XXX2_WAIT_NEXT_CLOCK_TIME_US); i++) {
205 /* Wait next clock time (1/32.768K~=30.5us) */
206 k_busy_wait(IT8XXX2_WAIT_NEXT_CLOCK_TIME_US);
207
208 if (adc_data_valid(dev)) {
209 valid = 1;
210 break;
211 }
212 }
213
214 if (valid) {
215 adc_it8xxx2_get_sample(dev);
216 } else {
217 LOG_ERR("Sampling timeout.");
218 return;
219 }
220 }
221
adc_enable_measurement(uint32_t ch)222 static void adc_enable_measurement(uint32_t ch)
223 {
224 struct adc_it8xxx2_regs *const adc_regs = ADC_IT8XXX2_REG_BASE;
225 const struct device *const dev = DEVICE_DT_INST_GET(0);
226 struct adc_it8xxx2_data *data = dev->data;
227
228 if (ch <= CHIP_ADC_CH7) {
229 /* Select and enable a voltage channel input for measurement */
230 adc_regs->VCH0CTL = (IT8XXX2_ADC_DATVAL | IT8XXX2_ADC_INTDVEN) + ch;
231 } else {
232 /* Channels 13~16 controller setting */
233 adc_regs->adc_vchs_ctrl[ADC_CHANNEL_OFFSET(ch)].VCHCTL =
234 IT8XXX2_ADC_DATVAL | IT8XXX2_ADC_INTDVEN | IT8XXX2_ADC_VCHEN;
235 }
236
237 /* ADC module enable */
238 adc_regs->ADCCFG |= IT8XXX2_ADC_ADCEN;
239
240 /*
241 * In the sampling process, it is possible to read multiple channels
242 * at a time. The ADC sampling of it8xxx2 needs to read each channel
243 * in sequence, so it needs to wait for an interrupt to read data in
244 * the loop through k_sem_take(). But k_timer_start() is used in the
245 * interval test in test_adc.c, so we need to use polling wait instead
246 * of k_sem_take() to wait, otherwise it will cause kernel panic.
247 *
248 * k_is_in_isr() can determine whether to use polling or k_sem_take()
249 * at present.
250 */
251 if (k_is_in_isr()) {
252 /* polling wait for a valid data */
253 adc_poll_valid_data();
254 } else {
255 /* Enable adc interrupt */
256 irq_enable(DT_INST_IRQN(0));
257 /* Wait for an interrupt to read valid data. */
258 k_sem_take(&data->sem, K_FOREVER);
259 }
260 }
261
check_buffer_size(const struct adc_sequence * sequence,uint8_t active_channels)262 static int check_buffer_size(const struct adc_sequence *sequence,
263 uint8_t active_channels)
264 {
265 size_t needed_buffer_size;
266
267 needed_buffer_size = active_channels * sizeof(uint16_t);
268 if (sequence->options) {
269 needed_buffer_size *= (1 + sequence->options->extra_samplings);
270 }
271
272 if (sequence->buffer_size < needed_buffer_size) {
273 LOG_ERR("Provided buffer is too small (%u/%u)",
274 sequence->buffer_size, needed_buffer_size);
275 return -ENOMEM;
276 }
277
278 return 0;
279 }
280
adc_it8xxx2_start_read(const struct device * dev,const struct adc_sequence * sequence)281 static int adc_it8xxx2_start_read(const struct device *dev,
282 const struct adc_sequence *sequence)
283 {
284 struct adc_it8xxx2_data *data = dev->data;
285 uint32_t channel_mask = sequence->channels;
286
287 /* Channels 13~16 should be shifted to the right by 5 */
288 if (channel_mask > BIT(CHIP_ADC_CH7)) {
289 channel_mask >>= ADC_CHANNEL_SHIFT;
290 }
291
292 if (!channel_mask || channel_mask & ~BIT_MASK(CHIP_ADC_COUNT)) {
293 LOG_ERR("Invalid selection of channels");
294 return -EINVAL;
295 }
296
297 if (!sequence->resolution) {
298 LOG_ERR("ADC resolution is not valid");
299 return -EINVAL;
300 }
301 LOG_DBG("Configure resolution=%d", sequence->resolution);
302
303 data->buffer = sequence->buffer;
304
305 adc_context_start_read(&data->ctx, sequence);
306
307 return adc_context_wait_for_completion(&data->ctx);
308 }
309
adc_context_start_sampling(struct adc_context * ctx)310 static void adc_context_start_sampling(struct adc_context *ctx)
311 {
312 struct adc_it8xxx2_data *data =
313 CONTAINER_OF(ctx, struct adc_it8xxx2_data, ctx);
314 uint32_t channels = ctx->sequence.channels;
315 uint8_t channel_count = 0;
316
317 data->repeat_buffer = data->buffer;
318
319 /*
320 * The ADC sampling of it8xxx2 needs to read each channel
321 * in sequence.
322 */
323 while (channels) {
324 data->ch = find_lsb_set(channels) - 1;
325 channels &= ~BIT(data->ch);
326
327 adc_enable_measurement(data->ch);
328
329 channel_count++;
330 }
331
332 if (check_buffer_size(&ctx->sequence, channel_count)) {
333 return;
334 }
335
336 adc_context_on_sampling_done(&data->ctx, DEVICE_DT_INST_GET(0));
337 }
338
adc_it8xxx2_read(const struct device * dev,const struct adc_sequence * sequence)339 static int adc_it8xxx2_read(const struct device *dev,
340 const struct adc_sequence *sequence)
341 {
342 struct adc_it8xxx2_data *data = dev->data;
343 int err;
344
345 adc_context_lock(&data->ctx, false, NULL);
346 err = adc_it8xxx2_start_read(dev, sequence);
347 adc_context_release(&data->ctx, err);
348
349 return err;
350 }
351
352 #ifdef CONFIG_ADC_ASYNC
adc_it8xxx2_read_async(const struct device * dev,const struct adc_sequence * sequence,struct k_poll_signal * async)353 static int adc_it8xxx2_read_async(const struct device *dev,
354 const struct adc_sequence *sequence,
355 struct k_poll_signal *async)
356 {
357 struct adc_it8xxx2_data *data = dev->data;
358 int err;
359
360 adc_context_lock(&data->ctx, true, async);
361 err = adc_it8xxx2_start_read(dev, sequence);
362 adc_context_release(&data->ctx, err);
363
364 return err;
365 }
366 #endif /* CONFIG_ADC_ASYNC */
367
adc_context_update_buffer_pointer(struct adc_context * ctx,bool repeat_sampling)368 static void adc_context_update_buffer_pointer(struct adc_context *ctx,
369 bool repeat_sampling)
370 {
371 struct adc_it8xxx2_data *data =
372 CONTAINER_OF(ctx, struct adc_it8xxx2_data, ctx);
373
374 if (repeat_sampling) {
375 data->buffer = data->repeat_buffer;
376 }
377 }
378
adc_it8xxx2_isr(const struct device * dev)379 static void adc_it8xxx2_isr(const struct device *dev)
380 {
381 struct adc_it8xxx2_data *data = dev->data;
382
383 LOG_DBG("ADC ISR triggered.");
384
385 adc_it8xxx2_get_sample(dev);
386
387 k_sem_give(&data->sem);
388 }
389
390 static const struct adc_driver_api api_it8xxx2_driver_api = {
391 .channel_setup = adc_it8xxx2_channel_setup,
392 .read = adc_it8xxx2_read,
393 #ifdef CONFIG_ADC_ASYNC
394 .read_async = adc_it8xxx2_read_async,
395 #endif
396 .ref_internal = IT8XXX2_ADC_VREF_VOL,
397 };
398
399 /*
400 * ADC analog accuracy initialization (only once after VSTBY power on)
401 *
402 * Write 1 to this bit and write 0 to this bit immediately once and
403 * only once during the firmware initialization and do not write 1 again
404 * after initialization since IT83xx takes much power consumption
405 * if this bit is set as 1
406 */
adc_accuracy_initialization(void)407 static void adc_accuracy_initialization(void)
408 {
409 struct adc_it8xxx2_regs *const adc_regs = ADC_IT8XXX2_REG_BASE;
410
411 /* Start adc accuracy initialization */
412 adc_regs->ADCSTS |= IT8XXX2_ADC_AINITB;
413 /* Enable automatic HW calibration. */
414 adc_regs->KDCTL |= IT8XXX2_ADC_AHCE;
415 /* Stop adc accuracy initialization */
416 adc_regs->ADCSTS &= ~IT8XXX2_ADC_AINITB;
417 }
418
adc_it8xxx2_init(const struct device * dev)419 static int adc_it8xxx2_init(const struct device *dev)
420 {
421 const struct adc_it8xxx2_cfg *config = dev->config;
422 struct adc_it8xxx2_data *data = dev->data;
423 struct adc_it8xxx2_regs *const adc_regs = ADC_IT8XXX2_REG_BASE;
424 int status;
425
426 #ifdef CONFIG_ADC_IT8XXX2_VOL_FULL_SCALE
427 /* ADC input voltage 0V ~ AVCC (3.3V) is mapped into 0h-3FFh */
428 adc_regs->ADCIVMFSCS1 = ADC_0_7_FULL_SCALE_MASK;
429 adc_regs->ADCIVMFSCS2 = ADC_8_10_FULL_SCALE_MASK;
430 adc_regs->ADCIVMFSCS3 = ADC_13_16_FULL_SCALE_MASK;
431 #endif
432 /* ADC analog accuracy initialization */
433 adc_accuracy_initialization();
434
435 /* Set the pin to ADC alternate function. */
436 status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
437 if (status < 0) {
438 LOG_ERR("Failed to configure ADC pins");
439 return status;
440 }
441
442 /*
443 * The ADC channel conversion time is 30.8*(SCLKDIV+1) us.
444 * (Current setting is 61.6us)
445 *
446 * NOTE: A sample time delay (60us) also need to be included in
447 * conversion time.
448 * In addition, the ADC has a waiting time of 202.8us for
449 * voltage stabilization.
450 *
451 * So the final ADC sample time result is ~= 324.4us.
452 */
453 adc_regs->ADCSTS &= ~IT8XXX2_ADC_ADCCTS1;
454 adc_regs->ADCCFG &= ~IT8XXX2_ADC_ADCCTS0;
455 /*
456 * bit[5-0]@ADCCTL : SCLKDIV
457 * SCLKDIV has to be equal to or greater than 1h;
458 */
459 adc_regs->ADCCTL = 1;
460
461 #ifdef CONFIG_SOC_IT8XXX2_EC_BUS_24MHZ
462 adc_regs->ADCCTL1 =
463 (adc_regs->ADCCTL1 & ~ADC_SACLKDIV_MASK) | ADC_SACLKDIV(2);
464 #endif
465 /*
466 * Enable this bit, and data of VCHxDATL/VCHxDATM will be
467 * kept until data valid is cleared.
468 */
469 adc_regs->ADCGCR |= IT8XXX2_ADC_DBKEN;
470
471 IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
472 adc_it8xxx2_isr, DEVICE_DT_INST_GET(0), 0);
473
474 k_sem_init(&data->sem, 0, 1);
475 adc_context_unlock_unconditionally(&data->ctx);
476
477 return 0;
478 }
479
480 static struct adc_it8xxx2_data adc_it8xxx2_data_0 = {
481 ADC_CONTEXT_INIT_TIMER(adc_it8xxx2_data_0, ctx),
482 ADC_CONTEXT_INIT_LOCK(adc_it8xxx2_data_0, ctx),
483 ADC_CONTEXT_INIT_SYNC(adc_it8xxx2_data_0, ctx),
484 };
485
486 PINCTRL_DT_INST_DEFINE(0);
487
488 static const struct adc_it8xxx2_cfg adc_it8xxx2_cfg_0 = {
489 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
490 };
491
492 DEVICE_DT_INST_DEFINE(0, adc_it8xxx2_init,
493 NULL,
494 &adc_it8xxx2_data_0,
495 &adc_it8xxx2_cfg_0, PRE_KERNEL_1,
496 CONFIG_ADC_INIT_PRIORITY,
497 &api_it8xxx2_driver_api);
498
