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Searched refs:CCIPR_REG (Results 1 – 7 of 7) sorted by relevance

/Zephyr-Core-3.6.0/include/zephyr/dt-bindings/clock/
Dstm32g4_clock.h71 #define CCIPR_REG 0x88 macro
79 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
80 #define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG)
81 #define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR_REG)
82 #define USART4_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR_REG)
83 #define USART5_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG)
84 #define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG)
85 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG)
86 #define I2C2_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG)
87 #define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG)
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Dstm32l4_clock.h69 #define CCIPR_REG 0x88 macro
77 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
78 #define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG)
79 #define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR_REG)
80 #define UART4_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR_REG)
81 #define UART5_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG)
82 #define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG)
83 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG)
84 #define I2C2_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG)
85 #define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG)
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Dstm32wl_clock.h69 #define CCIPR_REG 0x88 macro
76 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
77 #define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG)
78 #define SPI2_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG)
79 #define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG)
80 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG)
81 #define I2C2_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG)
82 #define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG)
83 #define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG)
84 #define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR_REG)
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Dstm32g0_clock.h67 #define CCIPR_REG 0x54 macro
75 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
76 #define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG)
77 #define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR_REG)
78 #define CEC_SEL(val) STM32_CLOCK(val, 1, 6, CCIPR_REG)
79 #define LPUART2_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG)
80 #define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG)
81 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG)
82 #define I2C2_I2S1_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG)
83 #define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG)
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Dstm32wb_clock.h70 #define CCIPR_REG 0x88 macro
80 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
81 #define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG)
82 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG)
83 #define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG)
84 #define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG)
85 #define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR_REG)
86 #define SAI1_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR_REG)
87 #define CLK48_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR_REG)
88 #define ADC_SEL(val) STM32_CLOCK(val, 3, 28, CCIPR_REG)
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Dstm32l0_clock.h63 #define CCIPR_REG 0x4C macro
70 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
71 #define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG)
72 #define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG)
73 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG)
74 #define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG)
75 #define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG)
76 #define HSI48_SEL(val) STM32_CLOCK(val, 1, 26, CCIPR_REG)
Dstm32c0_clock.h61 #define CCIPR_REG 0x54 macro
68 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
69 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG)
70 #define I2C2_I2S1_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG)
71 #define ADC_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR_REG)