Searched refs:C1 (Results 1 – 6 of 6) sorted by relevance
64 int C1, C2, C3; in base64_encode() local89 C1 = *src++; in base64_encode()93 *p++ = base64_enc_map[(C1 >> 2) & 0x3F]; in base64_encode()94 *p++ = base64_enc_map[(((C1 & 3) << 4) + (C2 >> 4)) & 0x3F]; in base64_encode()100 C1 = *src++; in base64_encode()103 *p++ = base64_enc_map[(C1 >> 2) & 0x3F]; in base64_encode()104 *p++ = base64_enc_map[(((C1 & 3) << 4) + (C2 >> 4)) & 0x3F]; in base64_encode()
53 #define IPCC_ReadReg(hipcc, reg) READ_REG(hipcc->C1##reg)
328 00000000 EE F1 FE A6 A8 41 5F CC A6 3A 73 A7 C1 33 B4 78 .....A_..:s..3.x
190 | C1 | gpio[16] | uart1_txd | spi1_cs[2] | i2c1_scl | gpio[16] |
193 | C1 | gpio[16] | uart1_txd | spi1_cs[2] | i2c1_scl | gpio[16] |
91 The above figure illustrates some states, from (a) to (d), for channels from ``C1`` to ``C5``,
