1 /* STELLARIS Ethernet Controller 2 * 3 * Copyright (c) 2018 Zilogic Systems 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 #ifndef ETH_STELLARIS_PRIV_H_ 9 #define ETH_STELLARIS_PRIV_H_ 10 11 #define REG_BASE(dev) \ 12 ((const struct eth_stellaris_config *const)(dev)->config)->mac_base 13 /* 14 * Register mapping 15 */ 16 /* Registers for ethernet system, mac_base + offset */ 17 #define REG_MACRIS (REG_BASE(dev) + 0x000) 18 #define REG_MACIM (REG_BASE(dev) + 0x004) 19 #define REG_MACRCTL (REG_BASE(dev) + 0x008) 20 #define REG_MACTCTL (REG_BASE(dev) + 0x00C) 21 #define REG_MACDATA (REG_BASE(dev) + 0x010) 22 #define REG_MACIA0 (REG_BASE(dev) + 0x014) 23 #define REG_MACIA1 (REG_BASE(dev) + 0x018) 24 #define REG_MACNP (REG_BASE(dev) + 0x034) 25 #define REG_MACTR (REG_BASE(dev) + 0x038) 26 27 /* ETH MAC Receive Control bit fields set value */ 28 #define BIT_MACRCTL_RSTFIFO 0x10 29 #define BIT_MACRCTL_BADCRC 0x8 30 #define BIT_MACRCTL_RXEN 0x1 31 #define BIT_MACRCTL_PRMS 0x4 32 33 /* ETH MAC Transmit Control bit fields set value */ 34 #define BIT_MACTCTL_DUPLEX 0x10 35 #define BIT_MACTCTL_CRC 0x4 36 #define BIT_MACTCTL_PADEN 0x2 37 #define BIT_MACTCTL_TXEN 0x1 38 39 /* ETH MAC Txn req bit fields set value */ 40 #define BIT_MACTR_NEWTX 0x1 41 42 /* Ethernet MAC RAW Interrupt Status/Ack bit set values */ 43 #define BIT_MACRIS_RXINT 0x1 44 #define BIT_MACRIS_TXER 0x2 45 #define BIT_MACRIS_TXEMP 0x4 46 #define BIT_MACRIS_FOV 0x8 47 #define BIT_MACRIS_RXER 0x10 48 49 struct eth_stellaris_runtime { 50 struct net_if *iface; 51 uint8_t mac_addr[6]; 52 struct k_sem tx_sem; 53 bool tx_err; 54 uint32_t tx_word; 55 int tx_pos; 56 #if defined(CONFIG_NET_STATISTICS_ETHERNET) 57 struct net_stats_eth stats; 58 #endif 59 }; 60 61 typedef void (*eth_stellaris_config_irq_t)(const struct device *dev); 62 63 struct eth_stellaris_config { 64 uint32_t mac_base; 65 uint32_t sys_ctrl_base; 66 uint32_t irq_num; 67 eth_stellaris_config_irq_t config_func; 68 }; 69 70 #endif /* ETH_STELLARIS_PRIV_H_ */ 71
