1 /*
2  * Copyright (c) 2019 Intel Corporation.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef ZEPHYR_DRIVERS_AUDIO_TLV320DAC310X_H_
8 #define ZEPHYR_DRIVERS_AUDIO_TLV320DAC310X_H_
9 
10 #ifdef __cplusplus
11 extern "C" {
12 #endif
13 
14 /* Register addresses */
15 #define PAGE_CONTROL_ADDR	0
16 
17 /* Register addresses {page, address} and fields */
18 #define SOFT_RESET_ADDR		(struct reg_addr){0, 1}
19 #define SOFT_RESET_ASSERT	(1)
20 
21 #define NDAC_DIV_ADDR		(struct reg_addr){0, 11}
22 #define NDAC_POWER_UP		BIT(7)
23 #define NDAC_POWER_UP_MASK	BIT(7)
24 #define NDAC_DIV_MASK		BIT_MASK(7)
25 #define NDAC_DIV(val)		((val) & NDAC_DIV_MASK)
26 
27 #define MDAC_DIV_ADDR		(struct reg_addr){0, 12}
28 #define MDAC_POWER_UP		BIT(7)
29 #define MDAC_POWER_UP_MASK	BIT(7)
30 #define MDAC_DIV_MASK		BIT_MASK(7)
31 #define MDAC_DIV(val)		((val) & MDAC_DIV_MASK)
32 
33 #define DAC_PROC_CLK_FREQ_MAX	49152000	/* 49.152 MHz */
34 
35 #define OSR_MSB_ADDR		(struct reg_addr){0, 13}
36 #define OSR_MSB_MASK		BIT_MASK(2)
37 
38 #define OSR_LSB_ADDR		(struct reg_addr){0, 14}
39 #define OSR_LSB_MASK		BIT_MASK(8)
40 
41 #define DAC_MOD_CLK_FREQ_MIN	2800000	/* 2.8 MHz */
42 #define DAC_MOD_CLK_FREQ_MAX	6200000 /* 6.2 MHz */
43 
44 #define IF_CTRL1_ADDR		(struct reg_addr){0, 27}
45 #define IF_CTRL_IFTYPE_MASK	BIT_MASK(2)
46 #define IF_CTRL_IFTYPE_I2S	0
47 #define IF_CTRL_IFTYPE_DSP	1
48 #define IF_CTRL_IFTYPE_RJF	2
49 #define IF_CTRL_IFTYPE_LJF	3
50 #define IF_CTRL_IFTYPE(val)	(((val) & IF_CTRL_IFTYPE_MASK) << 6)
51 #define IF_CTRL_WLEN_MASK	BIT_MASK(2)
52 #define IF_CTRL_WLEN(val)	(((val) & IF_CTRL_WLEN_MASK) << 4)
53 #define IF_CTRL_WLEN_16		0
54 #define IF_CTRL_WLEN_20		1
55 #define IF_CTRL_WLEN_24		2
56 #define IF_CTRL_WLEN_32		3
57 #define IF_CTRL_BCLK_OUT	BIT(3)
58 #define IF_CTRL_WCLK_OUT	BIT(2)
59 
60 #define BCLK_DIV_ADDR		(struct reg_addr){0, 30}
61 #define BCLK_DIV_POWER_UP	BIT(7)
62 #define BCLK_DIV_POWER_UP_MASK	BIT(7)
63 #define BCLK_DIV_MASK		BIT_MASK(7)
64 #define BCLK_DIV(val)		((val) & MDAC_DIV_MASK)
65 
66 #define OVF_FLAG_ADDR		(struct reg_addr){0, 39}
67 
68 #define PROC_BLK_SEL_ADDR	(struct reg_addr){0, 60}
69 #define	PROC_BLK_SEL_MASK	BIT_MASK(5)
70 #define	PROC_BLK_SEL(val)	((val) & PROC_BLK_SEL_MASK)
71 
72 #define DATA_PATH_SETUP_ADDR	(struct reg_addr){0, 63}
73 #define DAC_LR_POWERUP_DEFAULT	(BIT(7) | BIT(6) | BIT(4) | BIT(2))
74 #define DAC_LR_POWERDN_DEFAULT	(BIT(4) | BIT(2))
75 
76 #define VOL_CTRL_ADDR		(struct reg_addr){0, 64}
77 #define VOL_CTRL_UNMUTE_DEFAULT	(0)
78 #define VOL_CTRL_MUTE_DEFAULT	(BIT(3) | BIT(2))
79 
80 #define L_DIG_VOL_CTRL_ADDR	(struct reg_addr){0, 65}
81 #define DRC_CTRL1_ADDR		(struct reg_addr){0, 68}
82 #define L_BEEP_GEN_ADDR		(struct reg_addr){0, 71}
83 #define BEEP_GEN_EN_BEEP	(BIT(7))
84 #define R_BEEP_GEN_ADDR		(struct reg_addr){0, 72}
85 #define BEEP_LEN_MSB_ADDR	(struct reg_addr){0, 73}
86 #define BEEP_LEN_MIB_ADDR	(struct reg_addr){0, 74}
87 #define BEEP_LEN_LSB_ADDR	(struct reg_addr){0, 75}
88 
89 /* Page 1 registers */
90 #define HEADPHONE_DRV_ADDR	(struct reg_addr){1, 31}
91 #define HEADPHONE_DRV_POWERUP	(BIT(7) | BIT(6))
92 #define HEADPHONE_DRV_CM_MASK	(BIT_MASK(2) << 3)
93 #define HEADPHONE_DRV_CM(val)	(((val) << 3) & HEADPHONE_DRV_CM_MASK)
94 #define HEADPHONE_DRV_RESERVED	(BIT(2))
95 
96 #define HP_OUT_POP_RM_ADDR	(struct reg_addr){1, 33}
97 #define HP_OUT_POP_RM_ENABLE	(BIT(7))
98 
99 #define OUTPUT_ROUTING_ADDR	(struct reg_addr){1, 35}
100 #define OUTPUT_ROUTING_HPL	(2 << 6)
101 #define OUTPUT_ROUTING_HPR	(2 << 2)
102 
103 #define HPL_ANA_VOL_CTRL_ADDR	(struct reg_addr){1, 36}
104 #define HPR_ANA_VOL_CTRL_ADDR	(struct reg_addr){1, 37}
105 #define HPX_ANA_VOL_ENABLE	(BIT(7))
106 #define HPX_ANA_VOL_MASK	(BIT_MASK(7))
107 #define HPX_ANA_VOL(val)	(((val) & HPX_ANA_VOL_MASK) |	\
108 		HPX_ANA_VOL_ENABLE)
109 #define HPX_ANA_VOL_MAX		(0)
110 #define HPX_ANA_VOL_DEFAULT	(64)
111 #define HPX_ANA_VOL_MIN		(127)
112 #define HPX_ANA_VOL_MUTE	(HPX_ANA_VOL_MIN | ~HPX_ANA_VOL_ENABLE)
113 #define HPX_ANA_VOL_LOW_THRESH	(105)
114 #define HPX_ANA_VOL_FLOOR	(144)
115 
116 #define HPL_DRV_GAIN_CTRL_ADDR	(struct reg_addr){1, 40}
117 #define HPR_DRV_GAIN_CTRL_ADDR	(struct reg_addr){1, 41}
118 #define	HPX_DRV_UNMUTE		(BIT(2))
119 
120 #define HEADPHONE_DRV_CTRL_ADDR	(struct reg_addr){1, 44}
121 #define HEADPHONE_DRV_LINEOUT	(BIT(1) | BIT(2))
122 
123 /* Page 3 registers */
124 #define TIMER_MCLK_DIV_ADDR	(struct reg_addr){3, 16}
125 #define TIMER_MCLK_DIV_EN_EXT	(BIT(7))
126 #define TIMER_MCLK_DIV_MASK	(BIT_MASK(7))
127 #define TIMER_MCLK_DIV_VAL(val)	((val) & TIMER_MCLK_DIV_MASK)
128 
129 struct reg_addr {
130 	uint8_t page; 		/* page number */
131 	uint8_t reg_addr; 		/* register address */
132 };
133 
134 enum proc_block {
135 	/* highest performance class with each decimation filter */
136 	PRB_P25_DECIMATION_A = 25,
137 	PRB_P10_DECIMATION_B = 10,
138 	PRB_P18_DECIMATION_C = 18,
139 };
140 
141 enum osr_multiple {
142 	OSR_MULTIPLE_8 = 8,
143 	OSR_MULTIPLE_4 = 4,
144 	OSR_MULTIPLE_2 = 2,
145 };
146 
147 enum cm_voltage {
148 	CM_VOLTAGE_1P35 = 0,
149 	CM_VOLTAGE_1P5 = 1,
150 	CM_VOLTAGE_1P65 = 2,
151 	CM_VOLTAGE_1P8 = 3,
152 };
153 
154 #ifdef __cplusplus
155 }
156 #endif
157 
158 #endif /* ZEPHYR_DRIVERS_AUDIO_TLV320DAC310X_H_ */
159