1 /*
2 * Copyright (c) 2022 Andrei-Edward Popa
3 * Copyright (c) 2023 TOKITA Hiroshi
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT raspberrypi_pico_clock_controller
9
10 #include <zephyr/drivers/clock_control.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <zephyr/drivers/reset.h>
13 #include <zephyr/dt-bindings/clock/rpi_pico_clock.h>
14
15 #include <hardware/clocks.h>
16 #include <hardware/xosc.h>
17 #include <hardware/structs/rosc.h>
18 #include <hardware/pll.h>
19 #include <hardware/watchdog.h>
20 #include <hardware/resets.h>
21
22 /* Undefine to prevent conflicts with header definitions */
23 #undef pll_sys
24 #undef pll_usb
25
26 #define CTRL_SRC_LSB CLOCKS_CLK_REF_CTRL_SRC_LSB
27 #define CTRL_SRC_BITS CLOCKS_CLK_REF_CTRL_SRC_BITS
28 #define CTRL_AUXSRC_LSB CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB
29 #define CTRL_AUXSRC_BITS CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_BITS
30 #define CTRL_ENABLE_BITS CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS
31 #define DIV_FRAC_BITS CLOCKS_CLK_GPOUT0_DIV_FRAC_BITS
32 #define DIV_INT_BITS CLOCKS_CLK_GPOUT0_DIV_INT_BITS
33 #define DIV_INT_LSB CLOCKS_CLK_GPOUT0_DIV_INT_LSB
34
35 #define PLL_VCO_FREQ_MIN 750000000
36 #define PLL_VCO_FREQ_MAX 1600000000
37 #define PLL_FB_DIV_MIN 16
38 #define PLL_FB_DIV_MAX 320
39 #define PLL_POST_DIV_MIN 1
40 #define PLL_POST_DIV_MAX 7
41
42 #define ROSC_PHASE_PASSWD_VALUE_PASS _u(0xAA)
43
44 #define STAGE_DS(n) \
45 (COND_CODE_1( \
46 DT_PROP_HAS_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc), stage_drive_strength, n), \
47 (DT_PROP_BY_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc), stage_drive_strength, n) & \
48 ROSC_FREQA_DS0_BITS), \
49 (0)) \
50 << (n * 3))
51
52 #define CLK_SRC_IS(clk, src) \
53 DT_SAME_NODE(DT_CLOCKS_CTLR_BY_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk), 0), \
54 DT_INST_CLOCKS_CTLR_BY_NAME(0, src))
55
56 #define REF_DIV(pll) DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll), clock_div)
57 #define FB_DIV(pll) DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll), fb_div)
58 #define POST_DIV1(pll) DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll), post_div1)
59 #define POST_DIV2(pll) DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll), post_div2)
60 #define VCO_FREQ(pll) ((CLOCK_FREQ_xosc / REF_DIV(pll)) * FB_DIV(pll))
61
62 /*
63 * Using the 'clock-names[0]' for expanding macro to frequency value.
64 * The 'clock-names[0]' is set same as label value that given to the node itself.
65 * Use it for traverse clock tree to find root of clock source.
66 */
67 #define CLOCK_FREQ(clk) _CONCAT(CLOCK_FREQ_, clk)
68 #define SRC_CLOCK(clk) DT_STRING_TOKEN_BY_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk), \
69 clock_names, 0)
70 #define SRC_CLOCK_FREQ(clk) _CONCAT(CLOCK_FREQ_, SRC_CLOCK(clk))
71
72 #define PLL_FREQ(pll) \
73 (DT_PROP(DT_CLOCKS_CTLR_BY_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll), 0), clock_frequency) / \
74 REF_DIV(pll) * FB_DIV(pll) / POST_DIV1(pll) / POST_DIV2(pll))
75
76 #define CLOCK_FREQ_clk_gpout0 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_gpout0), clock_frequency)
77 #define CLOCK_FREQ_clk_gpout1 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_gpout1), clock_frequency)
78 #define CLOCK_FREQ_clk_gpout2 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_gpout2), clock_frequency)
79 #define CLOCK_FREQ_clk_gpout3 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_gpout3), clock_frequency)
80 #define CLOCK_FREQ_clk_ref DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_ref), clock_frequency)
81 #define CLOCK_FREQ_clk_sys DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_sys), clock_frequency)
82 #define CLOCK_FREQ_clk_usb DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_usb), clock_frequency)
83 #define CLOCK_FREQ_clk_adc DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_adc), clock_frequency)
84 #define CLOCK_FREQ_clk_rtc DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_rtc), clock_frequency)
85 #define CLOCK_FREQ_clk_peri DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_peri), clock_frequency)
86 #define CLOCK_FREQ_xosc DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, xosc), clock_frequency)
87 #define CLOCK_FREQ_rosc DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc), clock_frequency)
88 #define CLOCK_FREQ_rosc_ph DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc), clock_frequency)
89 #define CLOCK_FREQ_gpin0 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, gpin0), clock_frequency)
90 #define CLOCK_FREQ_gpin1 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, gpin1), clock_frequency)
91 #define CLOCK_FREQ_pll_sys PLL_FREQ(pll_sys)
92 #define CLOCK_FREQ_pll_usb PLL_FREQ(pll_usb)
93
94 #define CLOCK_AUX_SOURCE(clk) _CONCAT(_CONCAT(AUXSTEM_, clk), _CONCAT(AUXSRC_, SRC_CLOCK(clk)))
95
96 #define AUXSRC_xosc XOSC_CLKSRC
97 #define AUXSRC_rosc ROSC_CLKSRC
98 #define AUXSRC_rosc_ph ROSC_CLKSRC_PH
99 #define AUXSRC_pll_sys CLKSRC_PLL_SYS
100 #define AUXSRC_pll_usb CLKSRC_PLL_USB
101 #define AUXSRC_clk_ref CLK_REF
102 #define AUXSRC_clk_sys CLK_SYS
103 #define AUXSRC_clk_usb CLK_USB
104 #define AUXSRC_clk_adc CLK_ADC
105 #define AUXSRC_clk_rtc CLK_RTC
106 #define AUXSRC_clk_gpin0 CLKSRC_GPIN0
107 #define AUXSRC_clk_gpin1 CLKSRC_GPIN1
108
109 #define AUXSTEM_clk_gpout0 CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_
110 #define AUXSTEM_clk_gpout1 CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_
111 #define AUXSTEM_clk_gpout2 CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_
112 #define AUXSTEM_clk_gpout3 CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_
113 #define AUXSTEM_clk_ref CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_
114 #define AUXSTEM_clk_sys CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_
115 #define AUXSTEM_clk_usb CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_
116 #define AUXSTEM_clk_adc CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_
117 #define AUXSTEM_clk_rtc CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_
118 #define AUXSTEM_clk_peri CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_
119
120 #define TUPLE_ENTRY(n, p, i) \
121 { \
122 _CONCAT(RPI_PICO_CLKID_, DT_INST_STRING_UPPER_TOKEN_BY_IDX(0, clock_names, i)), \
123 COND_CODE_1( \
124 DT_PROP_HAS_IDX(DT_CLOCKS_CTLR_BY_IDX(DT_NODELABEL(clocks), i), \
125 clocks, 0), \
126 (_CONCAT(RPI_PICO_CLKID_, \
127 DT_STRING_UPPER_TOKEN_BY_IDX( \
128 DT_CLOCKS_CTLR_BY_IDX(DT_NODELABEL(clocks), i), \
129 clock_names, 0))), \
130 (-1)) \
131 }
132
133 enum rpi_pico_clkid {
134 rpi_pico_clkid_none = -1,
135 rpi_pico_clkid_clk_gpout0 = RPI_PICO_CLKID_CLK_GPOUT0,
136 rpi_pico_clkid_clk_gpout1 = RPI_PICO_CLKID_CLK_GPOUT1,
137 rpi_pico_clkid_clk_gpout2 = RPI_PICO_CLKID_CLK_GPOUT2,
138 rpi_pico_clkid_clk_gpout3 = RPI_PICO_CLKID_CLK_GPOUT3,
139 rpi_pico_clkid_clk_ref = RPI_PICO_CLKID_CLK_REF,
140 rpi_pico_clkid_clk_sys = RPI_PICO_CLKID_CLK_SYS,
141 rpi_pico_clkid_clk_peri = RPI_PICO_CLKID_CLK_PERI,
142 rpi_pico_clkid_clk_usb = RPI_PICO_CLKID_CLK_USB,
143 rpi_pico_clkid_clk_adc = RPI_PICO_CLKID_CLK_ADC,
144 rpi_pico_clkid_clk_rtc = RPI_PICO_CLKID_CLK_RTC,
145 rpi_pico_clkid_pll_sys = RPI_PICO_CLKID_PLL_SYS,
146 rpi_pico_clkid_pll_usb = RPI_PICO_CLKID_PLL_USB,
147 rpi_pico_clkid_xosc = RPI_PICO_CLKID_XOSC,
148 rpi_pico_clkid_rosc = RPI_PICO_CLKID_ROSC,
149 rpi_pico_clkid_rosc_ph = RPI_PICO_CLKID_ROSC_PH,
150 rpi_pico_clkid_gpin0 = RPI_PICO_CLKID_GPIN0,
151 rpi_pico_clkid_gpin1 = RPI_PICO_CLKID_GPIN1,
152 END_OF_RPI_PICO_CLKID,
153 };
154
155 struct rpi_pico_clkid_tuple {
156 enum rpi_pico_clkid clk;
157 enum rpi_pico_clkid parent;
158 };
159
160 struct rpi_pico_clk_config {
161 uint32_t source;
162 uint32_t aux_source;
163 uint32_t rate;
164 uint32_t source_rate;
165 };
166
167 struct rpi_pico_pll_config {
168 uint32_t ref_div;
169 uint32_t fb_div;
170 uint32_t post_div1;
171 uint32_t post_div2;
172 };
173
174 struct rpi_pico_rosc_config {
175 uint32_t phase;
176 uint32_t range;
177 uint32_t div;
178 uint32_t code;
179 };
180
181 struct rpi_pico_gpin_config {
182 uint32_t frequency;
183 };
184
185 struct clock_control_rpi_pico_config {
186 clocks_hw_t *const clocks_regs;
187 xosc_hw_t *const xosc_regs;
188 pll_hw_t *const pll_sys_regs;
189 pll_hw_t *const pll_usb_regs;
190 rosc_hw_t *const rosc_regs;
191 const struct pinctrl_dev_config *pcfg;
192 struct rpi_pico_pll_config plls_data[RPI_PICO_PLL_COUNT];
193 struct rpi_pico_clk_config clocks_data[RPI_PICO_CLOCK_COUNT];
194 struct rpi_pico_rosc_config rosc_data;
195 struct rpi_pico_gpin_config gpin_data[RPI_PICO_GPIN_COUNT];
196 };
197
198 struct clock_control_rpi_pico_data {
199 uint32_t rosc_freq;
200 uint32_t rosc_ph_freq;
201 };
202
rpi_pico_frequency_count(const struct device * dev,clock_control_subsys_t sys)203 uint64_t rpi_pico_frequency_count(const struct device *dev, clock_control_subsys_t sys)
204 {
205 const struct clock_control_rpi_pico_config *config = dev->config;
206 enum rpi_pico_clkid clkid = (enum rpi_pico_clkid)sys;
207 fc_hw_t *fc0 = &config->clocks_regs->fc0;
208 uint32_t fc0_id;
209
210 switch (clkid) {
211 case rpi_pico_clkid_clk_ref:
212 fc0_id = CLOCKS_FC0_SRC_VALUE_CLK_REF;
213 break;
214 case rpi_pico_clkid_clk_sys:
215 fc0_id = CLOCKS_FC0_SRC_VALUE_CLK_SYS;
216 break;
217 case rpi_pico_clkid_clk_peri:
218 fc0_id = CLOCKS_FC0_SRC_VALUE_CLK_PERI;
219 break;
220 case rpi_pico_clkid_clk_usb:
221 fc0_id = CLOCKS_FC0_SRC_VALUE_CLK_USB;
222 break;
223 case rpi_pico_clkid_clk_adc:
224 fc0_id = CLOCKS_FC0_SRC_VALUE_CLK_ADC;
225 break;
226 case rpi_pico_clkid_clk_rtc:
227 fc0_id = CLOCKS_FC0_SRC_VALUE_CLK_RTC;
228 break;
229 case rpi_pico_clkid_pll_sys:
230 fc0_id = CLOCKS_FC0_SRC_VALUE_PLL_SYS_CLKSRC_PRIMARY;
231 break;
232 case rpi_pico_clkid_pll_usb:
233 fc0_id = CLOCKS_FC0_SRC_VALUE_PLL_USB_CLKSRC_PRIMARY;
234 break;
235 case rpi_pico_clkid_xosc:
236 fc0_id = CLOCKS_FC0_SRC_VALUE_XOSC_CLKSRC;
237 break;
238 case rpi_pico_clkid_rosc:
239 fc0_id = CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC;
240 break;
241 case rpi_pico_clkid_rosc_ph:
242 fc0_id = CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC_PH;
243 break;
244 case rpi_pico_clkid_gpin0:
245 fc0_id = CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN0;
246 break;
247 case rpi_pico_clkid_gpin1:
248 fc0_id = CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN0;
249 break;
250 default:
251 return -1;
252 }
253
254 (void)frequency_count_khz(fc0_id);
255
256 return ((fc0->result >> CLOCKS_FC0_RESULT_KHZ_LSB) * 1000) +
257 ((fc0->result & CLOCKS_FC0_RESULT_FRAC_BITS) * 1000 / CLOCKS_FC0_RESULT_FRAC_BITS);
258 }
259
rpi_pico_rosc_write(const struct device * dev,io_rw_32 * addr,uint32_t value)260 static int rpi_pico_rosc_write(const struct device *dev, io_rw_32 *addr, uint32_t value)
261 {
262 hw_clear_bits(&rosc_hw->status, ROSC_STATUS_BADWRITE_BITS);
263
264 if (rosc_hw->status & ROSC_STATUS_BADWRITE_BITS) {
265 return -EINVAL;
266 }
267
268 *addr = value;
269
270 if (rosc_hw->status & ROSC_STATUS_BADWRITE_BITS) {
271 return -EINVAL;
272 }
273
274 return 0;
275 }
276
277 /**
278 * Get source clock id of this clock
279 *
280 * @param dev pointer to clock device
281 * @param id id of this clock
282 * @return parent clock id
283 */
rpi_pico_get_clock_src(const struct device * dev,enum rpi_pico_clkid id)284 static enum rpi_pico_clkid rpi_pico_get_clock_src(const struct device *dev, enum rpi_pico_clkid id)
285 {
286 const struct clock_control_rpi_pico_config *config = dev->config;
287 enum rpi_pico_clkid srcid = rpi_pico_clkid_none;
288
289 if (id == rpi_pico_clkid_clk_gpout0 || id == rpi_pico_clkid_clk_gpout1 ||
290 id == rpi_pico_clkid_clk_gpout2 || id == rpi_pico_clkid_clk_gpout3) {
291 const static enum rpi_pico_clkid table[] = {
292 rpi_pico_clkid_pll_sys,
293 rpi_pico_clkid_gpin0,
294 rpi_pico_clkid_gpin1,
295 rpi_pico_clkid_pll_usb,
296 rpi_pico_clkid_rosc_ph,
297 rpi_pico_clkid_xosc,
298 rpi_pico_clkid_clk_sys,
299 rpi_pico_clkid_clk_usb,
300 rpi_pico_clkid_clk_adc,
301 rpi_pico_clkid_clk_rtc,
302 rpi_pico_clkid_clk_ref,
303 };
304
305 clock_hw_t *clock_hw = &config->clocks_regs->clk[id];
306 uint32_t aux = ((clock_hw->ctrl & CTRL_AUXSRC_BITS) >> CTRL_AUXSRC_LSB);
307
308 srcid = table[aux];
309 } else if (id == rpi_pico_clkid_clk_ref) {
310 const static enum rpi_pico_clkid table[] = {
311 rpi_pico_clkid_pll_usb,
312 rpi_pico_clkid_gpin0,
313 rpi_pico_clkid_gpin1,
314 };
315
316 clock_hw_t *clock_hw = &clocks_hw->clk[id];
317 uint32_t aux = ((clock_hw->ctrl & CTRL_AUXSRC_BITS) >> CTRL_AUXSRC_LSB);
318 uint32_t src = ((clock_hw->ctrl >> CTRL_SRC_LSB) & CTRL_SRC_BITS);
319
320 if (src == CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH) {
321 srcid = rpi_pico_clkid_rosc_ph;
322 } else if (src == CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC) {
323 srcid = rpi_pico_clkid_xosc;
324 } else {
325 srcid = table[aux];
326 }
327 } else if (id == rpi_pico_clkid_clk_sys) {
328 const static enum rpi_pico_clkid table[] = {
329 rpi_pico_clkid_pll_sys,
330 rpi_pico_clkid_pll_usb,
331 rpi_pico_clkid_rosc,
332 rpi_pico_clkid_xosc,
333 rpi_pico_clkid_gpin0,
334 rpi_pico_clkid_gpin1,
335 };
336
337 clock_hw_t *clock_hw = &clocks_hw->clk[id];
338 uint32_t aux = ((clock_hw->ctrl & CTRL_AUXSRC_BITS) >> CTRL_AUXSRC_LSB);
339 uint32_t src = ((clock_hw->ctrl >> CTRL_SRC_LSB) & CTRL_SRC_BITS);
340
341 if (src == CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF) {
342 srcid = rpi_pico_clkid_clk_ref;
343 } else {
344 srcid = table[aux];
345 }
346 } else if (id == rpi_pico_clkid_clk_peri) {
347 const static enum rpi_pico_clkid table[] = {
348 rpi_pico_clkid_clk_sys,
349 rpi_pico_clkid_pll_sys,
350 rpi_pico_clkid_pll_usb,
351 rpi_pico_clkid_rosc_ph,
352 rpi_pico_clkid_xosc,
353 rpi_pico_clkid_gpin0,
354 rpi_pico_clkid_gpin1,
355 };
356
357 clock_hw_t *clock_hw = &clocks_hw->clk[id];
358 uint32_t aux = ((clock_hw->ctrl & CTRL_AUXSRC_BITS) >> CTRL_AUXSRC_LSB);
359
360 srcid = table[aux];
361 } else if (id == rpi_pico_clkid_clk_usb || id == rpi_pico_clkid_clk_adc ||
362 id == rpi_pico_clkid_clk_rtc) {
363 const static enum rpi_pico_clkid table[] = {
364 rpi_pico_clkid_pll_usb,
365 rpi_pico_clkid_pll_sys,
366 rpi_pico_clkid_rosc_ph,
367 rpi_pico_clkid_xosc,
368 rpi_pico_clkid_gpin0,
369 rpi_pico_clkid_gpin1,
370 };
371
372 clock_hw_t *clock_hw = &clocks_hw->clk[id];
373 uint32_t aux = ((clock_hw->ctrl & CTRL_AUXSRC_BITS) >> CTRL_AUXSRC_LSB);
374
375 srcid = table[aux];
376 } else if (id == rpi_pico_clkid_pll_sys || id == rpi_pico_clkid_pll_usb) {
377 srcid = rpi_pico_clkid_xosc;
378 }
379
380 return srcid;
381 }
382
383 /**
384 * Query clock is enabled or not
385 *
386 * @param dev pointer to clock device
387 * @param id id of clock
388 * @return true if the clock enabled, otherwith false
389 */
rpi_pico_is_clock_enabled(const struct device * dev,enum rpi_pico_clkid id)390 static bool rpi_pico_is_clock_enabled(const struct device *dev, enum rpi_pico_clkid id)
391 {
392 const struct clock_control_rpi_pico_config *config = dev->config;
393
394 if (id == rpi_pico_clkid_clk_sys || id == rpi_pico_clkid_clk_ref) {
395 return true;
396 } else if (id == rpi_pico_clkid_clk_usb ||
397 id == rpi_pico_clkid_clk_peri ||
398 id == rpi_pico_clkid_clk_adc ||
399 id == rpi_pico_clkid_clk_rtc ||
400 id == rpi_pico_clkid_clk_gpout0 ||
401 id == rpi_pico_clkid_clk_gpout1 ||
402 id == rpi_pico_clkid_clk_gpout2 ||
403 id == rpi_pico_clkid_clk_gpout3) {
404 clock_hw_t *clock_hw = &config->clocks_regs->clk[id];
405
406 if (clock_hw->ctrl & CTRL_ENABLE_BITS) {
407 return true;
408 }
409 } else if (id == rpi_pico_clkid_pll_sys || id == rpi_pico_clkid_pll_usb) {
410 pll_hw_t *pll = (id == rpi_pico_clkid_pll_sys) ? config->pll_sys_regs
411 : config->pll_usb_regs;
412
413 if (!(pll->pwr & (PLL_PWR_VCOPD_BITS | PLL_PWR_POSTDIVPD_BITS | PLL_PWR_PD_BITS))) {
414 return true;
415 }
416 } else if (id == rpi_pico_clkid_xosc) {
417 if (config->xosc_regs->status & XOSC_STATUS_ENABLED_BITS) {
418 return true;
419 }
420 } else if (id == rpi_pico_clkid_rosc || id == rpi_pico_clkid_rosc_ph) {
421 return true;
422 }
423
424 return false;
425 }
426
427 /**
428 * Calculate clock frequency with traversing clock tree.
429 *
430 * @param dev pointer to clock device
431 * @param id id of clock
432 * @return frequency value or 0 if disabled
433 */
rpi_pico_calc_clock_freq(const struct device * dev,enum rpi_pico_clkid id)434 static float rpi_pico_calc_clock_freq(const struct device *dev, enum rpi_pico_clkid id)
435 {
436 const struct clock_control_rpi_pico_config *config = dev->config;
437 struct clock_control_rpi_pico_data *data = dev->data;
438 float freq = 0.f;
439
440 if (!rpi_pico_is_clock_enabled(dev, id)) {
441 return freq;
442 }
443
444 if (id == rpi_pico_clkid_clk_sys ||
445 id == rpi_pico_clkid_clk_usb ||
446 id == rpi_pico_clkid_clk_adc ||
447 id == rpi_pico_clkid_clk_rtc ||
448 id == rpi_pico_clkid_clk_ref ||
449 id == rpi_pico_clkid_clk_gpout0 ||
450 id == rpi_pico_clkid_clk_gpout1 ||
451 id == rpi_pico_clkid_clk_gpout2 ||
452 id == rpi_pico_clkid_clk_gpout3) {
453 clock_hw_t *clock_hw = &config->clocks_regs->clk[id];
454
455 freq = rpi_pico_calc_clock_freq(dev, rpi_pico_get_clock_src(dev, id)) /
456 (((clock_hw->div & DIV_INT_BITS) >> DIV_INT_LSB) +
457 ((clock_hw->div & DIV_FRAC_BITS) / (float)DIV_FRAC_BITS));
458 } else if (id == rpi_pico_clkid_clk_peri) {
459 freq = rpi_pico_calc_clock_freq(dev, rpi_pico_get_clock_src(dev, id));
460 } else if (id == rpi_pico_clkid_pll_sys || id == rpi_pico_clkid_pll_usb) {
461 pll_hw_t *pll = (id == rpi_pico_clkid_pll_sys) ? config->pll_sys_regs
462 : config->pll_usb_regs;
463 freq = rpi_pico_calc_clock_freq(dev, rpi_pico_get_clock_src(dev, id)) *
464 (pll->fbdiv_int) / (pll->cs & PLL_CS_REFDIV_BITS) /
465 ((pll->prim & PLL_PRIM_POSTDIV1_BITS) >> PLL_PRIM_POSTDIV1_LSB) /
466 ((pll->prim & PLL_PRIM_POSTDIV2_BITS) >> PLL_PRIM_POSTDIV2_LSB);
467 } else if (id == rpi_pico_clkid_xosc) {
468 freq = CLOCK_FREQ_xosc;
469 } else if (id == rpi_pico_clkid_rosc) {
470 freq = data->rosc_freq;
471 } else if (id == rpi_pico_clkid_rosc_ph) {
472 freq = data->rosc_ph_freq;
473 }
474
475 return freq;
476 }
477
rpi_pico_is_valid_clock_index(enum rpi_pico_clkid index)478 static int rpi_pico_is_valid_clock_index(enum rpi_pico_clkid index)
479 {
480 if (index >= END_OF_RPI_PICO_CLKID) {
481 return -EINVAL;
482 }
483
484 return 0;
485 }
486
clock_control_rpi_pico_on(const struct device * dev,clock_control_subsys_t sys)487 static int clock_control_rpi_pico_on(const struct device *dev, clock_control_subsys_t sys)
488 {
489 const struct clock_control_rpi_pico_config *config = dev->config;
490 enum rpi_pico_clkid clkid = (enum rpi_pico_clkid)sys;
491 clocks_hw_t *clocks_regs = config->clocks_regs;
492
493 if (rpi_pico_is_valid_clock_index(clkid) < 0) {
494 return -EINVAL;
495 }
496
497 hw_set_bits(&clocks_regs->clk[clkid].ctrl, CTRL_ENABLE_BITS);
498
499 return 0;
500 }
501
clock_control_rpi_pico_off(const struct device * dev,clock_control_subsys_t sys)502 static int clock_control_rpi_pico_off(const struct device *dev, clock_control_subsys_t sys)
503 {
504 const struct clock_control_rpi_pico_config *config = dev->config;
505 enum rpi_pico_clkid clkid = (enum rpi_pico_clkid)sys;
506 clocks_hw_t *clocks_regs = config->clocks_regs;
507
508 if (rpi_pico_is_valid_clock_index(clkid) < 0) {
509 return -EINVAL;
510 }
511
512 hw_clear_bits(&clocks_regs->clk[clkid].ctrl, CTRL_ENABLE_BITS);
513
514 return 0;
515 }
516
clock_control_rpi_pico_get_status(const struct device * dev,clock_control_subsys_t sys)517 static enum clock_control_status clock_control_rpi_pico_get_status(const struct device *dev,
518 clock_control_subsys_t sys)
519 {
520 enum rpi_pico_clkid clkid = (enum rpi_pico_clkid)sys;
521
522 if (rpi_pico_is_valid_clock_index(clkid) < 0) {
523 return -EINVAL;
524 }
525
526 if (rpi_pico_is_clock_enabled(dev, clkid)) {
527 return CLOCK_CONTROL_STATUS_ON;
528 }
529
530 return CLOCK_CONTROL_STATUS_OFF;
531 }
532
clock_control_rpi_pico_get_rate(const struct device * dev,clock_control_subsys_t sys,uint32_t * rate)533 static int clock_control_rpi_pico_get_rate(const struct device *dev, clock_control_subsys_t sys,
534 uint32_t *rate)
535 {
536 struct clock_control_rpi_pico_data *data = dev->data;
537 enum rpi_pico_clkid clkid = (enum rpi_pico_clkid)sys;
538
539 if (rpi_pico_is_valid_clock_index(clkid) < 0) {
540 return -EINVAL;
541 }
542
543 if (IS_ENABLED(CONFIG_RPI_PICO_ROSC_USE_MEASURED_FREQ)) {
544 if (clkid == rpi_pico_clkid_rosc) {
545 data->rosc_freq = rpi_pico_frequency_count(dev, sys);
546 } else if (clkid == rpi_pico_clkid_rosc_ph) {
547 data->rosc_ph_freq = rpi_pico_frequency_count(dev, sys);
548 }
549 }
550
551 *rate = (int)rpi_pico_calc_clock_freq(dev, clkid);
552
553 return 0;
554 }
555
rpi_pico_clkid_tuple_swap(struct rpi_pico_clkid_tuple * lhs,struct rpi_pico_clkid_tuple * rhs)556 void rpi_pico_clkid_tuple_swap(struct rpi_pico_clkid_tuple *lhs, struct rpi_pico_clkid_tuple *rhs)
557 {
558 struct rpi_pico_clkid_tuple tmp = *lhs;
559 *lhs = *rhs;
560 *rhs = tmp;
561 }
562
rpi_pico_clkid_tuple_reorder_by_dependencies(struct rpi_pico_clkid_tuple * tuples,size_t len)563 void rpi_pico_clkid_tuple_reorder_by_dependencies(struct rpi_pico_clkid_tuple *tuples, size_t len)
564 {
565 uint32_t sorted_idx = 0;
566 uint32_t checked_idx = 0;
567 uint32_t target = -1;
568
569 while (sorted_idx < len) {
570 for (uint32_t i = sorted_idx; i < len; i++) {
571 if (tuples[i].parent == target) {
572 rpi_pico_clkid_tuple_swap(&tuples[sorted_idx], &tuples[i]);
573 sorted_idx++;
574 }
575 }
576 target = tuples[checked_idx++].clk;
577 }
578 }
579
clock_control_rpi_pico_init(const struct device * dev)580 static int clock_control_rpi_pico_init(const struct device *dev)
581 {
582 const struct clock_control_rpi_pico_config *config = dev->config;
583 struct clock_control_rpi_pico_data *data = dev->data;
584 clocks_hw_t *clocks_regs = config->clocks_regs;
585 rosc_hw_t *rosc_regs = config->rosc_regs;
586 pll_hw_t *plls[] = {config->pll_sys_regs, config->pll_usb_regs};
587 struct rpi_pico_clkid_tuple tuples[] = {
588 DT_INST_FOREACH_PROP_ELEM_SEP(0, clock_names, TUPLE_ENTRY, (,))};
589 uint32_t rosc_div;
590 int ret;
591
592 /* Reset all function before clock configuring */
593 reset_block(~(RESETS_RESET_IO_QSPI_BITS | RESETS_RESET_PADS_QSPI_BITS |
594 RESETS_RESET_PLL_USB_BITS | RESETS_RESET_USBCTRL_BITS |
595 RESETS_RESET_PLL_USB_BITS | RESETS_RESET_SYSCFG_BITS |
596 RESETS_RESET_PLL_SYS_BITS));
597
598 unreset_block_wait(RESETS_RESET_BITS &
599 ~(RESETS_RESET_ADC_BITS | RESETS_RESET_RTC_BITS |
600 RESETS_RESET_SPI0_BITS | RESETS_RESET_SPI1_BITS |
601 RESETS_RESET_UART0_BITS | RESETS_RESET_UART1_BITS |
602 RESETS_RESET_USBCTRL_BITS | RESETS_RESET_PWM_BITS));
603
604 /* Start tick in watchdog */
605 watchdog_hw->tick = ((CLOCK_FREQ_xosc/1000000) | WATCHDOG_TICK_ENABLE_BITS);
606
607 clocks_regs->resus.ctrl = 0;
608
609 /* Configure xosc */
610 xosc_init();
611
612 /* Before we touch PLLs, switch sys and ref cleanly away from their aux sources. */
613 clocks_hw->clk[RPI_PICO_CLKID_CLK_SYS].ctrl &= ~CTRL_SRC_BITS;
614 while (clocks_hw->clk[RPI_PICO_CLKID_CLK_SYS].selected != 0x1) {
615 ;
616 }
617 clocks_hw->clk[RPI_PICO_CLKID_CLK_REF].ctrl &= ~CTRL_SRC_BITS;
618 while (clocks_hw->clk[RPI_PICO_CLKID_CLK_REF].selected != 0x1) {
619 ;
620 }
621
622 /* Configure pll */
623 for (uint32_t i = 0; i < RPI_PICO_PLL_COUNT; i++) {
624 pll_init(plls[i], config->plls_data[i].ref_div,
625 CLOCK_FREQ_xosc * config->plls_data[i].fb_div,
626 config->plls_data[i].post_div1, config->plls_data[i].post_div2);
627 }
628
629 /* Configure clocks */
630 rpi_pico_clkid_tuple_reorder_by_dependencies(tuples, ARRAY_SIZE(tuples));
631 for (uint32_t i = 0; i < ARRAY_SIZE(tuples); i++) {
632 if (tuples[i].clk < 0 || tuples[i].clk >= RPI_PICO_CLOCK_COUNT) {
633 continue;
634 }
635
636 if (!(clock_configure(tuples[i].clk, config->clocks_data[tuples[i].clk].source,
637 config->clocks_data[tuples[i].clk].aux_source,
638 config->clocks_data[tuples[i].clk].source_rate,
639 config->clocks_data[tuples[i].clk].rate))) {
640 return -EINVAL;
641 }
642 }
643
644 hw_clear_bits(&clocks_regs->clk[rpi_pico_clkid_clk_gpout0].ctrl, CTRL_ENABLE_BITS);
645 hw_clear_bits(&clocks_regs->clk[rpi_pico_clkid_clk_gpout1].ctrl, CTRL_ENABLE_BITS);
646 hw_clear_bits(&clocks_regs->clk[rpi_pico_clkid_clk_gpout2].ctrl, CTRL_ENABLE_BITS);
647 hw_clear_bits(&clocks_regs->clk[rpi_pico_clkid_clk_gpout3].ctrl, CTRL_ENABLE_BITS);
648
649 /* Configure rosc */
650 ret = rpi_pico_rosc_write(dev, &rosc_regs->phase,
651 (ROSC_PHASE_PASSWD_VALUE_PASS << ROSC_PHASE_PASSWD_LSB) |
652 config->rosc_data.phase);
653 if (ret < 0) {
654 return ret;
655 }
656
657 ret = rpi_pico_rosc_write(dev, &rosc_regs->ctrl,
658 (ROSC_CTRL_ENABLE_VALUE_ENABLE << ROSC_CTRL_ENABLE_LSB) |
659 config->rosc_data.range);
660 if (ret < 0) {
661 return ret;
662 }
663
664 if (config->rosc_data.div <= 0) {
665 rosc_div = ROSC_DIV_VALUE_PASS + 1;
666 } else if (config->rosc_data.div > 31) {
667 rosc_div = ROSC_DIV_VALUE_PASS;
668 } else {
669 rosc_div = ROSC_DIV_VALUE_PASS + config->rosc_data.div;
670 }
671
672 ret = rpi_pico_rosc_write(dev, &rosc_regs->div, rosc_div);
673 if (ret < 0) {
674 return ret;
675 }
676
677 ret = rpi_pico_rosc_write(dev, &rosc_regs->freqa,
678 (ROSC_FREQA_PASSWD_VALUE_PASS << ROSC_FREQA_PASSWD_LSB) |
679 (config->rosc_data.code & UINT16_MAX));
680 if (ret < 0) {
681 return ret;
682 }
683
684 ret = rpi_pico_rosc_write(dev, &rosc_regs->freqb,
685 (ROSC_FREQA_PASSWD_VALUE_PASS << ROSC_FREQA_PASSWD_LSB) |
686 (config->rosc_data.code >> 16));
687 if (ret < 0) {
688 return ret;
689 }
690
691 unreset_block_wait(RESETS_RESET_BITS);
692
693 if (IS_ENABLED(CONFIG_RPI_PICO_ROSC_USE_MEASURED_FREQ)) {
694 data->rosc_freq =
695 rpi_pico_frequency_count(dev, (clock_control_subsys_t)rpi_pico_clkid_rosc);
696 data->rosc_ph_freq = rpi_pico_frequency_count(
697 dev, (clock_control_subsys_t)rpi_pico_clkid_rosc_ph);
698 }
699
700 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
701 if (ret < 0) {
702 return ret;
703 }
704
705 return 0;
706 }
707
708 static const struct clock_control_driver_api clock_control_rpi_pico_api = {
709 .on = clock_control_rpi_pico_on,
710 .off = clock_control_rpi_pico_off,
711 .get_rate = clock_control_rpi_pico_get_rate,
712 .get_status = clock_control_rpi_pico_get_status,
713 };
714
715 BUILD_ASSERT((VCO_FREQ(pll_sys) >= PLL_VCO_FREQ_MIN) && (VCO_FREQ(pll_sys) <= PLL_VCO_FREQ_MAX) &&
716 (VCO_FREQ(pll_sys) >= (CLOCK_FREQ_xosc / REF_DIV(pll_sys) * 16)),
717 "pll_sys: vco_freq is out of range");
718 BUILD_ASSERT((FB_DIV(pll_sys) >= PLL_FB_DIV_MIN) && (FB_DIV(pll_sys) <= PLL_FB_DIV_MAX),
719 "pll_sys: fb-div is out of range");
720 BUILD_ASSERT((POST_DIV1(pll_sys) >= PLL_POST_DIV_MIN) && (POST_DIV1(pll_sys) <= PLL_POST_DIV_MAX),
721 "pll_sys: post-div1 is out of range");
722 BUILD_ASSERT((POST_DIV2(pll_sys) >= PLL_POST_DIV_MIN) && (POST_DIV2(pll_sys) <= PLL_POST_DIV_MAX),
723 "pll_sys: post-div2 is out of range");
724
725 BUILD_ASSERT((VCO_FREQ(pll_usb) >= PLL_VCO_FREQ_MIN) && (VCO_FREQ(pll_usb) <= PLL_VCO_FREQ_MAX) &&
726 (VCO_FREQ(pll_usb) >= (CLOCK_FREQ_xosc / REF_DIV(pll_usb) * 16)),
727 "pll_usb: vco_freq is out of range");
728 BUILD_ASSERT((FB_DIV(pll_usb) >= PLL_FB_DIV_MIN) && (FB_DIV(pll_usb) <= PLL_FB_DIV_MAX),
729 "pll_usb: fb-div is out of range");
730 BUILD_ASSERT((POST_DIV1(pll_usb) >= PLL_POST_DIV_MIN) && (POST_DIV1(pll_usb) <= PLL_POST_DIV_MAX),
731 "pll_usb: post-div is out of range");
732 BUILD_ASSERT((POST_DIV2(pll_usb) >= PLL_POST_DIV_MIN) && (POST_DIV2(pll_usb) <= PLL_POST_DIV_MAX),
733 "pll_usb: post-div is out of range");
734
735 BUILD_ASSERT(SRC_CLOCK_FREQ(clk_ref) >= CLOCK_FREQ_clk_ref,
736 "clk_ref: clock divider is out of range");
737 BUILD_ASSERT(SRC_CLOCK_FREQ(clk_sys) >= CLOCK_FREQ_clk_sys,
738 "clk_sys: clock divider is out of range");
739 BUILD_ASSERT(SRC_CLOCK_FREQ(clk_usb) >= CLOCK_FREQ_clk_usb,
740 "clk_usb: clock divider is out of range");
741 BUILD_ASSERT(SRC_CLOCK_FREQ(clk_adc) >= CLOCK_FREQ_clk_adc,
742 "clk_adc: clock divider is out of range");
743 BUILD_ASSERT(SRC_CLOCK_FREQ(clk_rtc) >= CLOCK_FREQ_clk_rtc,
744 "clk_rtc: clock divider is out of range");
745 BUILD_ASSERT(SRC_CLOCK_FREQ(clk_peri) >= CLOCK_FREQ_clk_peri,
746 "clk_peri: clock divider is out of range");
747
748 BUILD_ASSERT(CLOCK_FREQ(rosc_ph) == CLOCK_FREQ(rosc), "rosc_ph: frequency must be equal to rosc");
749
750 PINCTRL_DT_INST_DEFINE(0);
751
752 static const struct clock_control_rpi_pico_config clock_control_rpi_pico_config = {
753 .clocks_regs = (clocks_hw_t *)DT_INST_REG_ADDR_BY_NAME(0, clocks),
754 .xosc_regs = (xosc_hw_t *)DT_INST_REG_ADDR_BY_NAME(0, xosc),
755 .pll_sys_regs = (pll_hw_t *)DT_INST_REG_ADDR_BY_NAME(0, pll_sys),
756 .pll_usb_regs = (pll_hw_t *)DT_INST_REG_ADDR_BY_NAME(0, pll_usb),
757 .rosc_regs = (rosc_hw_t *)DT_INST_REG_ADDR_BY_NAME(0, rosc),
758 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
759 .clocks_data = {
760 [RPI_PICO_CLKID_CLK_GPOUT0] = {
761 .source = 0,
762 .aux_source = CLOCK_AUX_SOURCE(clk_gpout0),
763 .source_rate = SRC_CLOCK_FREQ(clk_gpout0),
764 .rate = CLOCK_FREQ(clk_gpout0),
765 },
766 [RPI_PICO_CLKID_CLK_GPOUT1] = {
767 .source = 0,
768 .aux_source = CLOCK_AUX_SOURCE(clk_gpout1),
769 .source_rate = SRC_CLOCK_FREQ(clk_gpout1),
770 .rate = CLOCK_FREQ(clk_gpout1),
771 },
772 [RPI_PICO_CLKID_CLK_GPOUT2] = {
773 .source = 0,
774 .aux_source = CLOCK_AUX_SOURCE(clk_gpout2),
775 .source_rate = SRC_CLOCK_FREQ(clk_gpout2),
776 .rate = CLOCK_FREQ(clk_gpout2),
777 },
778 [RPI_PICO_CLKID_CLK_GPOUT3] = {
779 .source = 0,
780 .aux_source = CLOCK_AUX_SOURCE(clk_gpout3),
781 .source_rate = SRC_CLOCK_FREQ(clk_gpout3),
782 .rate = CLOCK_FREQ(clk_gpout3),
783 },
784 [RPI_PICO_CLKID_CLK_REF] = {
785 #if CLK_SRC_IS(clk_ref, rosc_ph)
786 .source = CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH,
787 .aux_source = 0,
788 #elif CLK_SRC_IS(clk_ref, xosc)
789 .source = CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC,
790 .aux_source = 0,
791 #else
792 .source = CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX,
793 #endif
794 .source_rate = SRC_CLOCK_FREQ(clk_ref),
795 .rate = CLOCK_FREQ(clk_ref),
796 },
797 [RPI_PICO_CLKID_CLK_SYS] = {
798 #if CLK_SRC_IS(clk_sys, clk_ref)
799 .source = CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF,
800 .aux_source = 0,
801 #else
802 .source = CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX,
803 .aux_source = CLOCK_AUX_SOURCE(clk_sys),
804 #endif
805 .source_rate = SRC_CLOCK_FREQ(clk_sys),
806 .rate = CLOCK_FREQ(clk_sys),
807 },
808 [RPI_PICO_CLKID_CLK_PERI] = {
809 .source = 0,
810 .aux_source = CLOCK_AUX_SOURCE(clk_peri),
811 .source_rate = SRC_CLOCK_FREQ(clk_peri),
812 .rate = CLOCK_FREQ(clk_peri),
813 },
814 [RPI_PICO_CLKID_CLK_USB] = {
815 .source = 0,
816 .aux_source = CLOCK_AUX_SOURCE(clk_usb),
817 .source_rate = SRC_CLOCK_FREQ(clk_usb),
818 .rate = CLOCK_FREQ(clk_usb),
819 },
820 [RPI_PICO_CLKID_CLK_ADC] = {
821 .source = 0,
822 .aux_source = CLOCK_AUX_SOURCE(clk_adc),
823 .source_rate = SRC_CLOCK_FREQ(clk_adc),
824 .rate = CLOCK_FREQ(clk_adc),
825 },
826 [RPI_PICO_CLKID_CLK_RTC] = {
827 .source = 0,
828 .aux_source = CLOCK_AUX_SOURCE(clk_rtc),
829 .source_rate = SRC_CLOCK_FREQ(clk_rtc),
830 .rate = CLOCK_FREQ(clk_rtc),
831 },
832 },
833 .plls_data = {
834 [RPI_PICO_PLL_SYS] = {
835 .ref_div = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_sys), clock_div),
836 .fb_div = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_sys), fb_div),
837 .post_div1 = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_sys), post_div1),
838 .post_div2 = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_sys), post_div2),
839 },
840 [RPI_PICO_PLL_USB] = {
841 .ref_div = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_usb), clock_div),
842 .fb_div = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_usb), fb_div),
843 .post_div1 = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_usb), post_div1),
844 .post_div2 = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_usb), post_div2),
845 },
846 },
847 .rosc_data = {
848 .phase = (COND_CODE_1(DT_NODE_HAS_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc),
849 phase_flip),
850 (ROSC_PHASE_FLIP_BITS), (0x0)) |
851 COND_CODE_1(DT_NODE_HAS_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc),
852 phase),
853 ((DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc), phase) &
854 ROSC_PHASE_SHIFT_BITS) | ROSC_PHASE_ENABLE_BITS), (0x0))),
855 .div = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc), clock_div),
856 .range = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc), range),
857 .code = (STAGE_DS(0) | STAGE_DS(1) | STAGE_DS(2) | STAGE_DS(3) |
858 STAGE_DS(4) | STAGE_DS(5) | STAGE_DS(6) | STAGE_DS(7)),
859 },
860 .gpin_data = {
861 [RPI_PICO_GPIN_0] = {
862 COND_CODE_1(DT_NODE_HAS_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, gpin0),
863 clock_frequency),
864 (.frequency = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, gpin0),
865 clock_frequency),),
866 (.frequency = 0,))
867 },
868 [RPI_PICO_GPIN_1] = {
869 COND_CODE_1(DT_NODE_HAS_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, gpin1),
870 clock_frequency),
871 (.frequency = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, gpin1),
872 clock_frequency),),
873 (.frequency = 0,))
874 },
875 },
876 };
877
878 static struct clock_control_rpi_pico_data clock_control_rpi_pico_data = {
879 .rosc_freq = CLOCK_FREQ(rosc),
880 .rosc_ph_freq = CLOCK_FREQ(rosc_ph),
881 };
882
883 DEVICE_DT_INST_DEFINE(0, &clock_control_rpi_pico_init, NULL, &clock_control_rpi_pico_data,
884 &clock_control_rpi_pico_config, PRE_KERNEL_1,
885 CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &clock_control_rpi_pico_api);
886
