Searched refs:tmp_reg (Results 1 – 3 of 3) sorted by relevance
| /Zephyr-latest/arch/arm/core/cortex_m/ |
| D | pm_s2ram.S | 33 #define SAVE_SPECIAL_REG(sr_name, cpu_ctx_reg, tmp_reg) \ argument
34 mrs tmp_reg, sr_name; \
35 str tmp_reg, [cpu_ctx_reg, # CPU_CTX_SR_OFFSET(sr_name)];
37 #define RESTORE_SPECIAL_REG(sr_name, cpu_ctx_reg, tmp_reg) \ argument
38 ldr tmp_reg, [cpu_ctx_reg, # CPU_CTX_SR_OFFSET(sr_name)]; \
39 msr sr_name, tmp_reg;
94 #define SAVE_FM_BP_REGS(cpu_ctx, tmp_reg) \ argument
95 SAVE_SPECIAL_REG(faultmask, cpu_ctx, tmp_reg) \
96 SAVE_SPECIAL_REG(basepri, cpu_ctx, tmp_reg)
98 #define RESTORE_FM_BP_REGS(cpu_ctx, tmp_reg) \ argument
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| /Zephyr-latest/soc/nxp/imxrt/imxrt10xx/ |
| D | lpm_rt1064.c | 311 uint32_t tmp_reg = 0; in clock_lpm_init() local
327 tmp_reg = XTALOSC24M->OSC_CONFIG0; in clock_lpm_init()
328 tmp_reg &= ~(XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK | in clock_lpm_init()
330 tmp_reg |= XTALOSC24M_OSC_CONFIG0_HYST_PLUS(3) | XTALOSC24M_OSC_CONFIG0_HYST_MINUS(3); in clock_lpm_init()
331 XTALOSC24M->OSC_CONFIG0 = tmp_reg; in clock_lpm_init()
333 tmp_reg = XTALOSC24M->OSC_CONFIG2; in clock_lpm_init()
334 tmp_reg &= ~XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK; in clock_lpm_init()
335 tmp_reg |= XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(0x2d7); in clock_lpm_init()
336 XTALOSC24M->OSC_CONFIG2 = tmp_reg; in clock_lpm_init()
338 tmp_reg = XTALOSC24M->OSC_CONFIG1; in clock_lpm_init()
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| /Zephyr-latest/drivers/adc/ |
| D | adc_mcux_gau_adc.c | 51 uint32_t tmp_reg; in mcux_gau_adc_channel_setup() local
69 tmp_reg = base->ADC_REG_INTERVAL; in mcux_gau_adc_channel_setup()
82 if (base->ADC_REG_INTERVAL != tmp_reg) { in mcux_gau_adc_channel_setup()
88 tmp_reg = base->ADC_REG_ANA; in mcux_gau_adc_channel_setup()
101 if (base->ADC_REG_ANA != tmp_reg) { in mcux_gau_adc_channel_setup()
107 tmp_reg = base->ADC_REG_ANA; in mcux_gau_adc_channel_setup()
120 if (base->ADC_REG_ANA != tmp_reg) { in mcux_gau_adc_channel_setup()
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