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Searched refs:t6 (Results 1 – 10 of 10) sorted by relevance

/Zephyr-Core-3.5.0/arch/riscv/core/
Dcoredump.c31 uint32_t t6; member
77 arch_blk.r.t6 = esf->t6; in arch_coredump_info_dump()
Dfatal.c46 LOG_ERR(" a6: " PR_REG " t6: " PR_REG, esf->a6, esf->t6); in z_riscv_fatal_error()
Disr.S32 RV_I( op t6, __z_arch_esf_t_t6_OFFSET(sp) );\
/Zephyr-Core-3.5.0/include/zephyr/arch/mips/
Dexp.h30 unsigned long t6; /* Caller-saved temporary register */ member
/Zephyr-Core-3.5.0/arch/mips/include/mips/
Dregdef.h38 #define t6 $14 macro
/Zephyr-Core-3.5.0/include/zephyr/arch/riscv/
Dexp.h61 unsigned long t6; /* Caller-saved temporary register */ member
/Zephyr-Core-3.5.0/arch/mips/core/
Dfatal.c23 esf->t4, esf->t5, esf->t6, esf->t7); in z_mips_fatal_error()
Disr.S49 op t6, ESF_O(t6)(sp) ;\
/Zephyr-Core-3.5.0/arch/mips/core/offsets/
Doffsets.c34 GEN_OFFSET_SYM(z_arch_esf_t, t6);
/Zephyr-Core-3.5.0/arch/riscv/core/offsets/
Doffsets.c105 GEN_OFFSET_SYM(z_arch_esf_t, t6);