| /Zephyr-Core-3.5.0/drivers/serial/ |
| D | uart_cmsdk_apb.c | 66 uint32_t sys_clk_freq; member
108 if ((dev_data->baud_rate != 0U) && (dev_cfg->sys_clk_freq != 0U)) { in baudrate_set()
110 dev_cfg->uart->bauddiv = (dev_cfg->sys_clk_freq / dev_data->baud_rate); in baudrate_set()
486 .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(0, clocks, clock_frequency),
551 .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(1, clocks, clock_frequency),
616 .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(2, clocks, clock_frequency),
681 .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(3, clocks, clock_frequency),
746 .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(4, clocks, clock_frequency),
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| D | uart_sifive.c | 54 uint32_t sys_clk_freq; member
334 uart->div = cfg->sys_clk_freq / cfg->baud_rate - 1; in uart_sifive_init()
388 .sys_clk_freq = SIFIVE_PERIPHERAL_CLOCK_FREQUENCY,
431 .sys_clk_freq = SIFIVE_PERIPHERAL_CLOCK_FREQUENCY,
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| D | uart_pl011.c | 33 uint32_t sys_clk_freq; member
321 ret = config->clk_enable_func(dev, config->sys_clk_freq); in pl011_init()
328 ret = pl011_set_baudrate(dev, config->sys_clk_freq, in pl011_init()
421 .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(n, clocks, clock_frequency), \
431 .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(n, clocks, clock_frequency), \
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| D | uart_stellaris.c | 73 uint32_t sys_clk_freq; member
229 config->sys_clk_freq); in uart_stellaris_init()
584 .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(0, clocks, clock_frequency),
623 .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(1, clocks, clock_frequency),
662 .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(2, clocks, clock_frequency),
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| D | uart_miv.c | 132 uint32_t sys_clk_freq; member
348 uint16_t baud_value = (cfg->sys_clk_freq / (cfg->baud_rate * 16U)) - 1; in uart_miv_init()
398 .sys_clk_freq = DT_INST_PROP(0, clock_frequency),
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| D | uart_cdns.h | 132 uint32_t sys_clk_freq; member
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| D | uart_cdns.c | 51 uart_regs->baud_rate_gen = (dev_cfg->sys_clk_freq + ((dev_cfg->bdiv + 1) * baud_rate) / 2) / in uart_cdns_set_baudrate()
294 .sys_clk_freq = DT_INST_PROP(n, clock_frequency), \
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| D | uart_cc32xx.c | 24 uint32_t sys_clk_freq; member
330 .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(idx, clocks, clock_frequency),\
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| D | uart_ns16550.c | 251 uint32_t sys_clk_freq; member
474 if (dev_cfg->sys_clk_freq != 0U) {
475 pclk = dev_cfg->sys_clk_freq;
1130 if (dev_cfg->sys_clk_freq != 0U) {
1131 pclk = dev_cfg->sys_clk_freq;
1302 .sys_clk_freq = DT_INST_PROP(n, clock_frequency), \
1306 .sys_clk_freq = 0, \
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| D | uart_cc13xx_cc26xx.c | 27 uint32_t sys_clk_freq; member
167 config->sys_clk_freq, cfg->baudrate, in uart_cc13xx_cc26xx_configure()
616 .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(n, clocks, \
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| D | uart_xlnx_ps.c | 142 uint32_t sys_clk_freq; member
232 uint32_t clk_freq = dev_cfg->sys_clk_freq; in set_baudrate()
1160 .sys_clk_freq = DT_INST_PROP(port, clock_frequency), \
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| D | uart_mchp_xec.c | 184 uint32_t sys_clk_freq; member
296 if ((baud_rate != 0U) && (dev_cfg->sys_clk_freq != 0U)) { in set_baud_rate()
301 divisor = ((dev_cfg->sys_clk_freq + (baud_rate << 3)) in set_baud_rate()
1083 .sys_clk_freq = DT_INST_PROP(n, clock_frequency), \
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| D | uart_liteuart.c | 36 uint32_t sys_clk_freq; member
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| /Zephyr-Core-3.5.0/drivers/clock_control/ |
| D | clock_control_litex.c | 329 f = (uint64_t)ldev->sys_clk_freq * (uint64_t)mul; in litex_clk_calc_global_frequency()
1311 vco_freq = (uint64_t)ldev->sys_clk_freq * (uint64_t)mul; in litex_clk_calc_all_params()
1347 max = (uint64_t)ldev->sys_clk_freq * (uint64_t)ldev->clkfbout.max; in litex_clk_check_rate_range()
1352 min = ldev->sys_clk_freq * ldev->clkfbout.min; in litex_clk_check_rate_range()
1695 ldev->sys_clk_freq = SYS_CLOCK_FREQUENCY; in litex_clk_dts_global_read()
1782 .sys_clk_freq = SYS_CLOCK_FREQUENCY,
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| D | clock_control_litex.h | 246 uint32_t sys_clk_freq; /* input frequency */ member
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